Major Crystal Plane Or Axis Other Than (100), (110), Or (111) (e.g., (731) Axis, Crystal Plane Several Degrees From (100) Toward (011), Etc.) Patents (Class 257/628)
  • Patent number: 10199341
    Abstract: Provided is a substrate structure, including: a substrate body having a conductive contact; an insulating layer formed on the substrate body with the conductive contact exposed therefrom; and an insulating protection layer formed on a portion of a surface of the insulating layer, and having a plurality of openings corresponding to the conductive contact, wherein at least one of the openings is disposed at an outer periphery of the conductive contact. Accordingly, the insulating protection layer uses the openings to dissipate and disperse residual stresses in a manufacturing process of high operating temperatures.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: February 5, 2019
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Fang-Yu Liang, Hung-Hsien Chang, Yi-Che Lai, Wen-Tsung Tseng, Chen-Yu Huang
  • Patent number: 10121666
    Abstract: An ion implantation method for scanning an ion beam reciprocally in an x direction and moving a wafer reciprocally in a y direction to implant ions into the wafer is provided. The method includes: irradiating a first wafer arranged to meet a predetermined plane channeling condition with the ion beam and measuring resistance of the first wafer irradiated with the ion beam; irradiating a second wafer arranged to meet a predetermined axial channeling condition with the ion beam and measuring resistance of the second wafer irradiated with the ion beam; and adjusting an implant angle distribution of the ion beam by using results of measuring the resistance of the first and second wafers.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: November 6, 2018
    Assignee: SUMITOMO HEAVY INDUSTRIES ION TECHNOLOGY CO., LTD.
    Inventors: Yoji Kawasaki, Makoto Sano, Kazutaka Tsukahara
  • Patent number: 9566791
    Abstract: There is provided a method for manufacturing semiconductor chips in which the chips as many as possible are arranged on one substrate and these chips can be cut with high accuracy in a relatively simple process. For such occasion on a wafer, short sides of the semiconductor chips are laid out to be inclined at an angle of 5° or less to a crystal orientation of the wafer. Thereafter, a laser stealth dicing method is used to form a plurality of first dicing lines along long sides of the individual semiconductor chips and a plurality of second dicing lines along short sides thereof.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: February 14, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Takeshi Shibata
  • Patent number: 9236530
    Abstract: A method for providing (Al,Ga,In)N thin films on Ga-face c-plane (Al,Ga,In)N substrates using c-plane surfaces with a miscut greater than at least 0.35 degrees toward the m-direction. Light emitting devices are formed on the smooth (Al,Ga,In)N thin films. Devices fabricated on the smooth surfaces exhibit improved performance.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: January 12, 2016
    Assignee: Soraa, Inc.
    Inventors: Arpan Chakraborty, Michael Grundmann, Anurag Tyagi
  • Patent number: 9077151
    Abstract: An optoelectronic device grown on a miscut of GaN, wherein the miscut comprises a semi-polar GaN crystal plane (of the GaN) miscut x degrees from an m-plane of the GaN and in a c-direction of the GaN, where ?15<x<?1 and 1<x<15 degrees.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: July 7, 2015
    Assignee: The Regents of the University of California
    Inventors: Po Shan Hsu, Kathryn M. Kelchner, Robert M. Farrell, Daniel A. Haeger, Hiroaki Ohta, Anurag Tyagi, Shuji Nakamura, Steven P. DenBaars, S. James Speck
  • Patent number: 9018739
    Abstract: The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate; a first semiconductor layer on the semiconductor substrate; a second semiconductor layer surrounding the first semiconductor layer; a high k dielectric layer and a gate conductor formed on the first semiconductor layer; source/drain regions formed in the second semiconductor layer, wherein the second semiconductor layer has a slant sidewall in contact with the first semiconductor layer. The semiconductor device has an increased output current, an increased operating speed, and a reduced power consumption due to the channel region of high mobility.
    Type: Grant
    Filed: September 25, 2010
    Date of Patent: April 28, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Qingqing Liang, Zhijiong Luo, Haizhou Yin
  • Patent number: 8963294
    Abstract: A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jochen Beintner, Thomas Ludwig, Edward Joseph Nowak
  • Patent number: 8963165
    Abstract: A nitride semiconductor structure in which a first nitride semiconductor underlying layer is provided on a substrate having a recess portion and a projection portion provided between the recess portions at a surface thereof, the first nitride semiconductor underlying layer has at least 6 first oblique facet planes surrounding the projection portion on an outer side of the projection portion, and a second nitride semiconductor underlying layer buries the first oblique facet planes, a nitride semiconductor light emitting element, a nitride semiconductor transistor element, a method of manufacturing a nitride semiconductor structure, and a method of manufacturing a nitride semiconductor element are provided.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: February 24, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Araki, Shinya Yoshida, Haruhisa Takiguchi, Atsushi Ogawa, Takao Kinoshita, Tohru Murata, Takeshi Funaki, Masayuki Hoteida
  • Patent number: 8957402
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first nitride semiconductor layer, a nitride semiconductor light emitting layer, a second nitride semiconductor layer, a p-side electrode, and an n-side electrode. The nitride semiconductor light emitting layer is provided on the p-side region of the second face of the first nitride semiconductor layer. The second nitride semiconductor layer is provided on the nitride semiconductor light emitting layer. The p-side electrode is provided on the second nitride semiconductor layer. The n-side electrode is provided on the n-side region of the second face of the first nitride semiconductor layer. The nitride semiconductor light emitting layer has a first concave-convex face in a side of the first nitride semiconductor layer, and a second concave-convex face in a side of the second nitride semiconductor layer.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: February 17, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akihiro Kojima, Hideto Furuyama, Miyoko Shimada, Yosuke Akimoto
  • Patent number: 8946772
    Abstract: A substrate for epitaxial growth of the present invention comprises: a single crystal part comprising a material different from a GaN-based semiconductor at least in a surface layer part; and an uneven surface, as a surface for epitaxial growth, comprising a plurality of convex portions arranged so that each of the convex portions has three other closest convex portions in directions different from each other by 120 degrees and a plurality of growth spaces, each of which is surrounded by six of the convex portions, wherein the single crystal part is exposed at least on the growth space, which enables a c-axis-oriented GaN-based semiconductor crystal to grow from the growth space.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: February 3, 2015
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Hiroaki Okagawa, Hiromitsu Kudo, Teruhisa Nakai, Seong-Jin Kim
  • Patent number: 8933543
    Abstract: A nitride-based semiconductor device of the present invention includes: a nitride-based semiconductor multilayer structure 20 which includes a p-type semiconductor region with a surface 12 being inclined from the m-plane by an angle of not less than 1° and not more than 5°; and an electrode 30 provided on the p-type semiconductor region. The p-type semiconductor region is formed by an AlxInyGazN (where x+y+z=1, x?0, y?0, and z?0) layer 26. The electrode 30 includes a Mg layer 32 and an Ag layer 34 provided on the Mg layer 32. The Mg layer 32 is in contact with the surface 12 of the p-type semiconductor region of the semiconductor multilayer structure 20.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: January 13, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Toshiya Yokogawa, Mitsuaki Oya, Atsushi Yamada, Akihiro Isozaki
  • Patent number: 8933538
    Abstract: Oxygen can be doped into a gallium nitride crystal by preparing a non-C-plane gallium nitride seed crystal, supplying material gases including gallium, nitrogen and oxygen to the non-C-plane gallium nitride seed crystal, growing a non-C-plane gallium nitride crystal on the non-C-plane gallium nitride seed crystal and allowing oxygen to infiltrating via a non-C-plane surface to the growing gallium nitride crystal. Oxygen-doped {20-21}, {1-101}, {1-100}, {11-20} or {20-22} surface n-type gallium nitride crystals are obtained.
    Type: Grant
    Filed: January 3, 2014
    Date of Patent: January 13, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kensaku Motoki, Masaki Ueno
  • Publication number: 20150008563
    Abstract: Group-III nitride crystal composites made up of especially processed crystal slices, cut from III-nitride bulk crystal, whose major surfaces are of {1-10±2}, {11-2±2}, {20-2±1} or {22-4±1} orientation, disposed adjoining each other sideways with the major-surface side of each slice facing up, and III-nitride crystal epitaxially present on the major surfaces of the adjoining slices, with the III-nitride crystal containing, as principal impurities, either silicon atoms or oxygen atoms. With x-ray diffraction FWHMs being measured along an axis defined by a <0001> direction of the substrate projected onto either of the major surfaces, FWHM peak regions are present at intervals of 3 to 5 mm width. Also, with threading dislocation density being measured along a <0001> direction of the III-nitride crystal substrate, threading-dislocation-density peak regions are present at the 3 to 5 mm intervals.
    Type: Application
    Filed: September 19, 2014
    Publication date: January 8, 2015
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Publication number: 20140353804
    Abstract: A first side surface of post of the first stripe is formed so that a plane which is most parallel to the first side surface among low-index planes of the growing Group III nitride semiconductor is a m-plane (10-10), and a first angle between the first lateral vector obtained by orthogonally projecting a normal vector of the first side surfaces to the main surface and a m-axis projected vector obtained by orthogonally projecting a normal vector of the m-plane of the growing semiconductor to the main surface is from 0.5° to 6°. A second side surface of post of the second stripe is formed so that a plane which is most parallel to the second side surface among low-index planes of the growing semiconductor is an a-plane (11-20), and a second angle between the second lateral vector and an a-axis projected vector of the a-plane is from 0° to 10°.
    Type: Application
    Filed: May 29, 2014
    Publication date: December 4, 2014
    Applicant: TOYODA GOSEI CO., LTD.
    Inventors: Koji Okuno, Takahide Oshio, Naoki Shibata, Hiroshi Amano
  • Patent number: 8883609
    Abstract: According to an embodiment, a method for manufacturing a semiconductor structure includes providing a first monocrystalline semiconductor portion having a first lattice constant in a reference direction and forming a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Mathias Plappert, Hans-Joachim Schulze
  • Patent number: 8872309
    Abstract: Group-III nitride crystal composites made up of especially processed crystal slices, cut from III-nitride bulk crystal, whose major surfaces are of {1-10±2}, {11-2±2}, {20-2±1} or {22-4±1} orientation, disposed adjoining each other sideways with the major-surface side of each slice facing up, and III-nitride crystal epitaxially present on the major surfaces of the adjoining slices, with the III-nitride crystal containing, as principal impurities, either silicon atoms or oxygen atoms.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: October 28, 2014
    Assignee: Sumitomo Electronic Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Patent number: 8853746
    Abstract: The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xiangdong Chen, Thomas W. Dyer, Kenneth Settlemyer, Haining S. Yang
  • Patent number: 8836086
    Abstract: Disclosed is a semiconductor light emitting chip (20) that is composed of: a substrate (10), which has the C plane of a sapphire single crystal as the front surface, and the side surfaces (25, 26) configured of planes that intersect all the planes equivalent to the M plane of the sapphire single crystal, and which includes modified regions (23, 24) in the side surfaces (25, 26), the modified regions being formed by laser radiation; and a light emitting element (12), which is provided on the substrate front surface (10a) of the substrate (10). In the semiconductor light emitting chip, a tilt of the substrate side surfaces with respect to the substrate front surface is suppressed. Also disclosed is a method for processing the substrate.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: September 16, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Daisuke Hiraiwa, Takehiko Okabe
  • Patent number: 8829658
    Abstract: A method of manufacturing a nitride substrate includes the following steps. Firstly, a nitride crystal is grown. Then, the nitride substrate including a front surface is cut from the nitride crystal. In the step of cutting, the nitride substrate is cut such that an off angle formed between an axis orthogonal to the front surface and an m-axis or an a-axis is greater than zero. When the nitride crystal is grown in a c-axis direction, in the step of cutting, the nitride substrate is cut from the nitride crystal along a flat plane which passes through a front surface and a rear surface of the nitride crystal and does not pass through a line segment connecting a center of a radius of curvature of the front surface with a center of a radius of curvature of the rear surface of the nitride crystal.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: September 9, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Satoshi Arakawa, Michimasa Miyanaga, Takashi Sakurada, Yoshiyuki Yamamoto, Hideaki Nakahata
  • Patent number: 8829617
    Abstract: A method including providing a plurality of fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the plurality of fins and the nitride layer, removing a portion of the plurality of fins to form an opening, and forming a dielectric spacer on a sidewall of the opening. The method may also include filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer, removing the nitride layer to form a gap between the plurality of fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the plurality of fins and the fill material to widen.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: September 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Balasubramanian S. Haran, Sanjay Mehta, Shom Ponoth, Ravikumar Ramachandran, Stefan Schmitz, Theodorus E. Standaert
  • Patent number: 8823146
    Abstract: A semiconductor structure having a silicon substrate having a <111> crystallographic orientation, an insulating layer disposed over a first portion of the silicon substrate, a silicon layer having a <100> orientation disposed over the insulating layer, and a non-nitride column III-V semiconductor layer or column II-VI semiconductor layer having the same <111> crystallographic orientation as the silicon substrate, the non-nitride column III-V semiconductor layer or column II-VI semiconductor layer being in direct contact with a second portion of the silicon substrate. A column III-nitride is disposed on the surface of the third portion of the substrate.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: September 2, 2014
    Assignee: Raytheon Company
    Inventor: William E. Hoke
  • Patent number: 8823014
    Abstract: A method of epitaxial growth of a material on a crystalline substrate includes selecting a substrate having a crystal plane that includes a plurality of terraces with step risers that join adjacent terraces. Each terrace of the plurality or terraces presents a lattice constant that substantially matches a lattice constant of the material, and each step riser presents a step height and offset that is consistent with portions of the material nucleating on adjacent terraces being in substantial crystalline match at the step riser. The method also includes preparing a substrate by exposing the crystal plane; and epitaxially growing the material on the substrate such that the portions of the material nucleating on adjacent terraces merge into a single crystal lattice without defects at the step risers.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: September 2, 2014
    Assignees: Kansas State University Research Foundation, State University of New York Stony Brook, The University of Bristol
    Inventors: James Edgar, Michael Dudley, Martin Kuball, Yi Zhang, Guan Wang, Hui Chen, Yu Zhang
  • Patent number: 8803294
    Abstract: A substrate has a surface made of a semiconductor having a hexagonal single-crystal structure of polytype 4H. The surface of the substrate is constructed by alternately providing a first plane having a plane orientation of (0-33-8), and a second plane connected to the first plane and having a plane orientation different from the plane orientation of the first plane. A gate insulating film is provided on the surface of the substrate. A gate electrode is provided on the gate insulating film.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: August 12, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Shin Harada, Keiji Wada, Toru Hiyoshi
  • Patent number: 8795440
    Abstract: A method of growing non-polar m-plane III-nitride film, such as GaN, AlN, AlGaN or InGaN, wherein the non-polar m-plane III-nitride film is grown on a suitable substrate, such as an m-SiC, m-GaN, LiGaO2 or LiAlO2 substrate, using metalorganic chemical vapor deposition (MOCVD). The method includes performing a solvent clean and acid dip of the substrate to remove oxide from the surface, annealing the substrate, growing a nucleation layer, such as aluminum nitride (AlN), on the annealed substrate, and growing the non-polar m-plane III-nitride film on the nucleation layer using MOCVD.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: August 5, 2014
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Bilge M. Imer, James S. Speck, Steven P. DenBaars, Shuji Nakamura
  • Patent number: 8796721
    Abstract: A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of the protruding portions taken along planes orthogonal to the surface of the substrate may be semi-circular in shape. The cross sections of the protruding portions may in alternative be convex in shape. A buffer layer and a GaN layer may be formed on the substrate.
    Type: Grant
    Filed: December 28, 2012
    Date of Patent: August 5, 2014
    Assignee: Nichia Corporation
    Inventors: Isamu Niki, Motokazu Yamada, Masahiko Sano, Shuji Shioji
  • Patent number: 8779440
    Abstract: Some embodiments show a semiconductor structure including a substrate with a {100} crystal surface plane which includes a plurality of adjacent structured regions at a top side of the substrate. The plurality of adjacent structured regions includes adjacent substrate surfaces with {111} crystal planes and a III-V semiconductor material layer above the top side of the substrate. A semiconductor device region includes at least one semiconductor device structure. The semiconductor device region is arranged above the plurality of adjacent structured regions at the top side of the substrate.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: July 15, 2014
    Assignee: Infineon Technologies AG
    Inventor: Martin Henning Albrecht Vielemeyer
  • Patent number: 8766237
    Abstract: A homo-material heterophased quantum well includes a first structural layer, a second structural layer and a third structural layer. The second structural layer is sandwiched between the first and third structural layers. The first structural layer, second structural layer and third structural layer are formed by growing atoms of a single material in a single growth direction. The energy gap of the second structural layer is smaller than that of the first and third structural layers.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: July 1, 2014
    Assignee: National Sun Yat-Sen University
    Inventors: I-Kai Lo, Yu-Chi Hsu, Chia-Ho Hsieh, Wen-Yuan Pang, Ming-Chi Chou
  • Publication number: 20140175616
    Abstract: Group-III nitride crystal composites made up of especially processed crystal slices, cut from III-nitride bulk crystal, whose major surfaces are of {1-10±2}, {11-2±2}, {20-2±1} or {22-4±1} orientation, disposed adjoining each other sideways with the major-surface side of each slice facing up, and III-nitride crystal epitaxially present on the major surfaces of the adjoining slices, with the III-nitride crystal containing, as principal impurities, either silicon atoms or oxygen atoms.
    Type: Application
    Filed: March 3, 2014
    Publication date: June 26, 2014
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Patent number: 8749030
    Abstract: Optical devices such as LEDs and lasers are discloses. The devices include a non-polar gallium nitride substrate member having an off-axis non-polar oriented crystalline surface plane. The off-axis non-polar oriented crystalline surface plane can be up to about ?0.6 degrees in a c-plane direction and up to about ?20 degrees in a c-plane direction in certain embodiments. In certain embodiments, a gallium nitride containing epitaxial layer is formed overlying the off-axis non-polar oriented crystalline surface plane. In certain embodiments, devices include a surface region overlying the gallium nitride epitaxial layer that is substantially free of hillocks.
    Type: Grant
    Filed: September 17, 2012
    Date of Patent: June 10, 2014
    Assignee: Soraa, Inc.
    Inventors: James W. Raring, Christiane Elsass
  • Patent number: 8729676
    Abstract: The present invention includes a method for manufacturing a silicon epitaxial wafer having a silicon homoepitaxial layer formed on a surface of a silicon single crystal wafer, including the steps of: preparing the silicon single crystal wafer such that a plane orientation of the silicon single crystal wafer is tilted at an angle in the range from 0.1° to 8° in a <112> direction from a {110} plane; and growing the silicon homoepitaxial layer on the prepared silicon single crystal wafer. According to the present invention, a silicon epitaxial wafer using the {110} substrate with improved surface quality, such as Haze and surface roughness and a method for manufacturing the silicon epitaxial wafer are provided.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: May 20, 2014
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Yutaka Shiga, Hiroshi Takeno
  • Patent number: 8709923
    Abstract: Provided is a method of manufacturing III-nitride crystal having a major surface of plane orientation other than {0001}, designated by choice, the III-nitride crystal manufacturing method including: a step of slicing III-nitride bulk crystal through a plurality of planes defining a predetermined slice thickness in the direction of the designated plane orientation, to produce a plurality of III-nitride crystal substrates having a major surface of the designated plane orientation; a step of disposing the substrates adjoining each other sideways in a manner such that the major surfaces of the substrates parallel each other and such that any difference in slice thickness between two adjoining III-nitride crystal substrates is not greater than 0.1 mm; and a step of growing III-nitride crystal onto the major surfaces of the substrates.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: April 29, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Patent number: 8704340
    Abstract: A compound semiconductor substrate includes a first substrate and a second substrate made of single crystal gallium nitride. In each of the first substrate and the second substrate, one surface is a (0001) Ga-face and an opposite surface is a (000-1) N-face. The first substrate and the second substrate are bonded to each other in a state where the (000-1) N-face of the first substrate and the (000-1) N-face of the second substrate face each other, and the (0001) Ga-face of the first substrate and the (0001) Ga-face of the second substrate are exposed.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: April 22, 2014
    Assignee: DENSO CORPORATION
    Inventors: Hiroaki Fujibayashi, Masami Naito, Nobuyuki Ooya
  • Patent number: 8698173
    Abstract: Solid state lighting devices with semi-polar or non-polar surfaces and associated methods of manufacturing are disclosed herein. In one embodiment, a solid state lighting device includes a substrate material having a substrate surface and an epitaxial silicon structure in direct contact with the substrate surface. The epitaxial silicon structure has a sidewall extending away from the substrate surface. The solid state lighting device also includes a semiconductor material on at least a portion of the sidewall of the epitaxial silicon structure. The semiconductor material has a semiconductor surface that is spaced apart from the substrate surface and is located on a semi-polar or non-polar crystal plane of the semiconductor material.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: April 15, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Jaydeb Goswami
  • Patent number: 8698284
    Abstract: A nitride-based semiconductor substrate may includes a plurality of hollow member patterns arranged on a substrate, a nitride-based seed layer formed on the substrate between the plurality of hollow member patterns, and a nitride-based buffer layer on the nitride-based seed layer so as to cover the plurality of hollow member patterns, wherein the plurality of hollow member patterns contact the substrate in a first direction and both ends of each of the plurality of hollow member patterns are open in the first direction.
    Type: Grant
    Filed: April 1, 2011
    Date of Patent: April 15, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Moon Lee
  • Patent number: 8686435
    Abstract: A silicon carbide layer is epitaxially formed on a main surface of a substrate. The silicon carbide layer is provided with a trench having a side wall inclined relative to the main surface. The side wall has an off angle of not less than 50° and not more than 65° relative to a {0001} plane. A gate insulating film is provided on the side wall of the silicon carbide layer. The silicon carbide layer includes: a body region having a first conductivity type and facing a gate electrode with the gate insulating film being interposed therebetween; and a pair of regions separated from each other by the body region and having a second conductivity type. The body region has an impurity density of 5×1016 cm?3 or greater. This allows for an increased degree of freedom in setting a threshold voltage while suppressing decrease of channel mobility.
    Type: Grant
    Filed: March 29, 2012
    Date of Patent: April 1, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Toru Hiyoshi, Keiji Wada
  • Patent number: 8686561
    Abstract: A nitride-based semiconductor light-emitting device 100 includes a GaN substrate 10, of which the principal surface is an m-plane 12, a semiconductor multilayer structure 20 that has been formed on the m-plane 12 of the GaN-based substrate 10, and an electrode 30 arranged on the semiconductor multilayer structure 20. The electrode 30 includes an Mg layer 32, which contacts with the surface of a p-type semiconductor region in the semiconductor multilayer structure 20.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: April 1, 2014
    Assignee: Panasonic Corporation
    Inventors: Toshiya Yokogawa, Mitsuaki Oya, Atsushi Yamada, Ryou Kato
  • Patent number: 8686434
    Abstract: There is provided a silicon carbide semiconductor device having excellent electrical characteristics such as channel mobility, and a method for manufacturing the same. A semiconductor device includes a substrate made of silicon carbide and having an off-angle of greater than or equal to 50° and less than or equal to 65° with respect to a surface orientation of {0001}, a p-type layer serving as a semiconductor layer, and an oxide film serving as an insulating film. The p-type layer is formed on the substrate and is made of silicon carbide. The oxide film is formed to contact with a surface of the p-type layer. A maximum value of the concentration of nitrogen atoms in a region within 10 nm of an interface between the semiconductor layer and the insulating film (interface between a channel region and the oxide film) is greater than or equal to 1×1021 cm?3.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: April 1, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Shin Harada, Takeyoshi Masuda, Keiji Wada, Masato Tsumori
  • Patent number: 8686398
    Abstract: A semiconductor light emitting device includes a first conductivity-type first semiconductor layer, a second conductivity-type second semiconductor layer, a semiconductor light emitting layer, and first and second electrodes. The semiconductor light emitting layer is provided between the first semiconductor layer and the second semiconductor layer, and includes a multiple quantum well structure. The quantum well structure includes well layers and barrier layers each laminated alternately, each of the well layers being not less than 6 nm and not more than 10 nm. The first and second electrodes are electrically connected to the first and second semiconductor layers such that current flows in a direction substantially vertical to the main surface.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: April 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Tanaka, Yoko Motojima
  • Patent number: 8673697
    Abstract: A method of fabricating a thin film transistor, comprising steps of preparing a substrate; forming a polycrystalline silicon layer on the substrate; injecting impurities into the polycrystalline silicon layer for channel doping; patterning the polycrystalline silicon layer and forming a semiconductor layer; annealing the semiconductor layer in an H2O atmosphere, and forming a thermal oxide layer on the semiconductor layer; forming a silicon nitride layer on the thermal oxide layer; forming a gate electrode at a location corresponding to a predetermined region of the semiconductor layer; forming an interlayer insulating layer on the entire surface of the substrate; and forming source and drain electrodes electrically connected with the semiconductor layer.
    Type: Grant
    Filed: May 4, 2011
    Date of Patent: March 18, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Moon-Jin Kim, Kyoung-Bo Kim, Ki-Yong Lee, Han-Hee Yoon
  • Patent number: 8674433
    Abstract: A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate. An oxide layer is formed on the substrate without the fin-shaped structure being formed thereon. A gate is formed to cover a part of the oxide layer and a part of the fin-shaped structure. An etching process is performed to etch a part of the fin-shaped structure beside the gate, therefore at least a recess is formed in the fin-shaped structure. An epitaxial process is performed to form an epitaxial layer in the recess, wherein the epitaxial layer has a hexagon-shaped profile structure.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: March 18, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chin-I Liao, Chia-Lin Hsu, Ming-Yen Li, Hsin-Huei Wu, Yung-Lun Hsieh, Chien-Hao Chen, Bo-Syuan Lee
  • Patent number: 8652918
    Abstract: A structure method for producing same provides suppressed lattice defects when epitaxially forming nitride layers over non-c-plane oriented layers, such as a semi-polar oriented template layer or substrate. A patterned mask with “window” openings, or trenches formed in the substrate with appropriate vertical dimensions, such as the product of the window width times the cotangent of the angle between the surface normal and the c-axis direction, provides significant blocking of all diagonally running defects during growth. In addition, inclined posts of appropriate height and spacing provide a blocking barrier to vertically running defects is created. When used in conjunction with the aforementioned aspects of mask windows or trenches, the post structure provides significant blocking of both vertically and diagonally running defects during growth.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: February 18, 2014
    Assignee: Palo Alto Research Center Incorporated
    Inventor: Andre Strittmatter
  • Publication number: 20140008705
    Abstract: A semiconductor device includes field regions formed in a substrate, and n-type impurity regions disposed between the field regions. At least one of the side surfaces of the field regions has a {100}, {310}, or {311} plane.
    Type: Application
    Filed: March 15, 2013
    Publication date: January 9, 2014
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joon- Young Choi, Kyung-Ho Lee, Sang-Jun Choi, Tae-Hyoung Koo, Sam-Jong Choi
  • Patent number: 8618639
    Abstract: According to an embodiment, a semiconductor structure includes a first monocrystalline semiconductor portion having a first lattice constant in a reference direction; a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion; and a metal layer formed on and in contact with the second monocrystalline semiconductor portion.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: December 31, 2013
    Assignee: Infineon Technologies Austria AG
    Inventors: Mathias Plappert, Hans-Joachim Schulze
  • Patent number: 8592316
    Abstract: A nitride semiconductor substrate includes two principal surfaces including an upper surface that is a growth face and a lower surface on its opposite side. An FWHM in a surface layer region at depths of from 0 to 250 nm from the upper surface is narrower than an FWHM in an inner region at depths exceeding 5 ?m from the upper surface, where the FWHMs are obtained by X-ray rocking curve measurement using diffraction off a particular asymmetric plane inclined relative to the upper surface.
    Type: Grant
    Filed: August 2, 2010
    Date of Patent: November 26, 2013
    Assignee: Hitachi Cable, Ltd.
    Inventors: Yuichi Oshima, Takehiro Yoshida
  • Patent number: 8575728
    Abstract: An optical device, e.g., LED, laser. The device includes a non-polar gallium nitride substrate member having a slightly off-axis non-polar oriented crystalline surface plane. In a specific embodiment, the slightly off-axis non-polar oriented crystalline surface plane is up to about ?0.6 degrees in a c-plane direction, but can be others. In a specific embodiment, the present invention provides a gallium nitride containing epitaxial layer formed overlying the slightly off-axis non-polar oriented crystalline surface plane. In a specific embodiment, the device includes a surface region overlying the gallium nitride epitaxial layer that is substantially free of hillocks.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: November 5, 2013
    Assignee: Soraa, Inc.
    Inventors: James W. Raring, Christiane Poblenz
  • Patent number: 8575729
    Abstract: The semiconductor chip (18) of the present invention is a semiconductor chip (18) on which a power semiconductor device (10) is formed, and which includes a semiconductor substrate made from a hexagonal semiconductor, in which the semiconductor substrate has a shape of a rectangle on a principal surface, in which the rectangle is defined by two sides having lengths a and b equal to each other, and in which linear expansion coefficients in directions parallel to the two sides of the semiconductor substrate are equal to each other.
    Type: Grant
    Filed: May 13, 2011
    Date of Patent: November 5, 2013
    Assignee: Panasonic Corporation
    Inventors: Masao Uchida, Masashi Hayashi
  • Patent number: 8569106
    Abstract: A film of an epitaxial layer that allows the reduction in both the height of a bunching step and crystal defects caused by a failure in migration of reactive species on a terrace is formed on a SiC semiconductor substrate having an off angle of 5 degrees or less. A film of a first-layer epitaxial layer is formed on and in contact with a surface of the SiC semiconductor substrate having an off angle of 5 degrees or less. Subsequently, the temperature in a reactor is lowered. A second-layer epitaxial layer is caused to epitaxially grow on and in contact with a surface of the first-layer epitaxial layer. In the above-described manner, the epitaxial layer is structured with two layers, and the growth temperature for the second epitaxial layer is set lower than the growth temperature for the first epitaxial layer.
    Type: Grant
    Filed: February 15, 2010
    Date of Patent: October 29, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenichi Hamano, Kenichi Ohtsuka, Nobuyuki Tomita, Masayoshi Tarutani
  • Patent number: 8558354
    Abstract: According to one embodiment, a semiconductor device includes a plurality of silicon films. The plurality of silicon films are disposed on one plane and are made of polysilicon containing an impurity. A crystal orientation of each of the silicon films is a (311) orientation.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: October 15, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoko Iwakaji, Jun Hirota, Moto Yabuki, Wakana Kai, Hirokazu Ishida, Ichiro Mizushima
  • Patent number: RE45165
    Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wei Chen, Tang-Xuan Zhong, Sheng-Da Liu, Chang-Yu Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang
  • Patent number: RE45180
    Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wei Chen, Tang-Xuan Zhong, Sheng-Da Liu, Chang-Yun Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang