With Specified Crystal Plane Or Axis Patents (Class 257/627)
  • Patent number: 10403812
    Abstract: A magnetic memory device includes a reference magnetic structure, a free magnetic structure, and a tunnel barrier pattern between the reference magnetic structure and the free magnetic structure. The reference magnetic structure includes a first pinned pattern, a second pinned pattern between the first pinned pattern and the tunnel barrier pattern, and an exchange coupling pattern between the first and the second pinned pattern. The second pinned pattern includes a first magnetic pattern adjacent the exchange coupling pattern, a second magnetic pattern adjacent the tunnel barrier pattern, a third magnetic pattern between the first and the second magnetic pattern, a first non-magnetic pattern between the first and the third magnetic pattern, and a second non-magnetic pattern between the second and the third magnetic pattern. The first non-magnetic pattern has a different crystal structure from the second non-magnetic pattern, and at least a portion of the third magnetic pattern is amorphous.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: September 3, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung Chul Lee, Ki Woong Kim, Sang Hwan Park, Sechung Oh
  • Patent number: 10177167
    Abstract: A method for forming a hybrid complementary metal oxide semiconductor (CMOS) device includes orienting a semiconductor layer of a semiconductor-on-insulator (SOI) substrate with a base substrate of the SOI, exposing the base substrate in an N-well region by etching through a mask layer, a dielectric layer, the semiconductor layer and a buried dielectric to form a trench and forming spacers on sidewalls of the trench. The base substrate is epitaxially grown from a bottom of the trench to form an extended region. A fin material is epitaxially grown from the extended region within the trench. The mask layer and the dielectric layer are restored over the trench. P-type field-effect transistor (PFET) fins are etched on the base substrate, and N-type field-effect transistor (NFET) fins are etched in the semiconductor layer.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: January 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Chia-Yu Chen, Bruce B. Doris, Hong He, Rajasekhar Venigalla
  • Patent number: 9984874
    Abstract: Method of producing one or more transition metal dichalcogenide (MX2) layers on a substrate, comprising the steps of: obtaining a substrate having a surface and depositing MX2 on the surface using ALD deposition, starting from a metal halide precursor and a chalcogen source (H2X), at a deposition temperature of about 300° C. Suitable metals are Mo and W, suitable chalcogenides are S, Se and Te. The substrate may be (111) oriented. Also mixtures of two or more MX2 layers of different compositions can be deposited on the substrate, by repeating at least some of the steps of the method.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: May 29, 2018
    Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&D
    Inventors: Matty Caymax, Markus Heyne, Annelies Delabie
  • Patent number: 9831222
    Abstract: A display device including a substrate; a first electrode on the substrate; and a plurality of semiconductor light emitting devices disposed on the first electrode; and a second electrode. Further, at least one of the semiconductor light emitting devices includes a first conductive semiconductor layer; a second conductive semiconductor layer overlapping with the first conductive semiconductor layer; and an active layer between the first conductive semiconductor layer and the second conductive semiconductor layer. In addition, an upper surface of the second conductive layer includes a recess groove having a bottom portion and a lateral wall portion formed along an edge of the second conductive semiconductor layer, and the second electrode extends partially on the bottom portion of the groove and on the lateral wall portion.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: November 28, 2017
    Assignee: LG ELECTRONICS INC.
    Inventors: Eunah Lee, Sangwook Byun, Hwankuk Yuh
  • Patent number: 9812494
    Abstract: A ?LED device comprising: a substrate and an epitaxial layer grown on the substrate and comprising a semiconductor material, wherein at least a portion of the substrate and the epitaxial layer define a mesa; an active layer within the mesa and configured, on application of an electrical current, to generate light for emission through a light emitting surface of the substrate opposite the mesa, wherein the crystal lattice structure of the substrate and the epitaxial layer is arranged such that a c-plane of the crystal lattice structure is misaligned with respect to the light emitting surface.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: November 7, 2017
    Assignee: Oculus VR, LLC
    Inventor: Christopher Percival
  • Patent number: 9806036
    Abstract: A semiconductor wafer including a main body including first and second surfaces opposite each other, a notch including a recess on an outer periphery, a first bevel region formed along the outer periphery of the main body, including a first slope connecting the first and second surfaces and having a first height with respect to a straight line extending from a first point where the first surface and the first slope meet to a second point where the second surface and the first slope meet, and a second bevel region in contact with the recess or opening, including a second slope connecting the first and second surfaces and having a second height, different from the first height, with respect to a straight line extending from a third point where the first surface and the second slope meet to a fourth point where the second surface and the second slope meet.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: October 31, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong-soo Kim, Sam-jong Choi, Sue-ryeon Kim, Tae-hyoung Koo, Hyun-hee Ju, Cheong-jun Kim, Ji-won You
  • Patent number: 9760164
    Abstract: Present invention discloses a touch panel and a manufacturing method thereof, the touch panel comprises: a substrate; a silver nano-wire electrode layer provided on the substrate comprising a connecting area and a non-connecting area; a first protective layer provided on silver nano-wire electrode layer having a first hole corresponding to connecting area; a second protective layer provided on first protective layer having a second hole corresponding to position of first hole; and a connecting wire provided on second protective layer connected to silver nano-wire electrode layer in connecting area through second hole and first hole. With the touch panel, the problem that etching solution can't seep when a single protective layer is too thick and the problem that a silver nano-wire layer is easily oxidized and the adhesion of the silver nano-wire layer is poor when a single protective layer is too thin can be avoided.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: September 12, 2017
    Assignee: TPK Touch Solutions Inc.
    Inventors: Chen-Yu Liu, Li-Wei Kung, Hsi-Chien Lin
  • Patent number: 9577031
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises: a substrate; and a plurality of convex structures formed on a surface of the substrate and arranged in a longitudinal direction of the substrate, each convex structure having a top surface, a bottom surface located on the surface of the substrate, a first end surface and a second end surface parallel to each other, and a front side surface and a rear side surface parallel to each other, in which the rear side surface of one of two adjacent convex structures and the front side surface of the other are located on a same plane to allow the plurality of convex structures to form a zigzag structure.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: February 21, 2017
    Inventors: Yuan Li, Lei Guo
  • Patent number: 9559160
    Abstract: Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: January 31, 2017
    Assignee: Intel Corporation
    Inventors: Annalisa Cappellani, Peter G. Tolchinsky, Kelin J. Kuhn, Glenn A. Glass, Van H. Le
  • Patent number: 9553237
    Abstract: A light emitting element includes a semiconductor layer; an upper electrode disposed on an upper surface of the semiconductor layer; and a lower electrode disposed on a lower surface of the semiconductor later. In a plan view, the upper electrode includes a first extending portion extending in an approximately rectangular shape along an outer periphery of the semiconductor layer, a first pad portion connected to a first side among four sides of the first extending portion, a second pad portion connected to a second side that is opposite to the first side, among the four sides of the first extending portion, and a second extending portion and a third extending portion, each disposed in a region surrounded by the first extending portion, the second extending portion and the third extending portion each connecting the first pad portion and the second pad portion.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: January 24, 2017
    Assignee: NICHIA CORPORATION
    Inventor: Hidetoshi Tanaka
  • Patent number: 9548425
    Abstract: A light-emitting diode is provided to include: a transparent substrate having a first surface, a second surface, and a side surface; a first conductive semiconductor layer positioned on the first surface of the transparent substrate; a second conductive semiconductor layer positioned on the first conductive semiconductor layer; an active layer positioned between the first conductive semiconductor layer and the second conductive semiconductor layer; a first pad electrically connected to the first conductive semiconductor layer; and a second pad electrically connected to the second conductive semiconductor layer, wherein the transparent substrate is configured to discharge light generated by the active layer through the second surface of the transparent substrate, and the light-emitting diode has a beam angle of at least 140 degrees or more. Accordingly, a light-emitting diode suitable for a backlight unit or a surface lighting apparatus can be provided.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: January 17, 2017
    Assignee: SEOUL VIOSYS CO., LTD.
    Inventors: Jong Hyeon Chae, Joon Sup Lee, Won Young Roh, Min Woo Kang, Jong Min Jang, Hyun A Kim, Daewoong Suh
  • Patent number: 9502612
    Abstract: A light emitting diode (LED) device and packaging with enhance heat conduction. An LED in a wafer level processing (WLP) package is disclosed using vias in the silicon to route the electrical connections to the LED backside and a dedicated hole in the silicon with a direct heat conduction route from the LED to the printed circuit board. Certain layers act to promote mechanical, electrical, thermal, or optical characteristics of the device. The device avoids or ameliorates heat dissipation problems found in conventional LED devices. Some embodiments include a plurality of optically permissive layers, including an optically permissive cover substrate comprising phosphors and/or quantum dots.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: November 22, 2016
    Assignee: Viagan Ltd.
    Inventor: Mordehai Margalit
  • Patent number: 9502595
    Abstract: A ?LED device comprising: a substrate and an epitaxial layer grown on the substrate and comprising a semiconductor material, wherein at least a portion of the substrate and the epitaxial layer define a mesa; an active layer within the mesa and configured, on application of an electrical current, to generate light for emission through a light emitting surface of the substrate opposite the mesa, wherein the crystal lattice structure of the substrate and the epitaxial layer is arranged such that a c-plane of the crystal lattice structure is misaligned with respect to the light emitting surface.
    Type: Grant
    Filed: May 6, 2015
    Date of Patent: November 22, 2016
    Assignee: Oculus VR, LLC
    Inventor: Christopher Percival
  • Patent number: 9355908
    Abstract: According to an embodiment, a semiconductor device includes an underlying layer and a plurality of transistors. The underlying layer includes a first region and a second region provided adjacently to the first region. The transistors are arranged in a plane parallel to an upper surface of the underlying layer. Each transistor includes a channel allowing a current to flow in a first direction intersecting the plane. The plurality of transistors includes a first transistor provided on the first region and a second transistor provided on the second region, a first channel of the first transistor having a first crystal orientation, and a second channel of the second transistor having a second crystal orientation different from the first crystal orientation.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: May 31, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masumi Saitoh
  • Patent number: 9240412
    Abstract: Semiconductor structures, devices, and methods of forming the structures and device are disclosed. Exemplary structures include multi-gate or FinFET structures that can include both re-channel MOS (NMOS) and p-channel MOS (PMOS) devices to form CMOS structures and devices on a substrate. The devices can be formed using selective epitaxy and shallow trench isolation techniques.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: January 19, 2016
    Assignee: ASM IP Holding B.V.
    Inventors: Qi Xie, Vladimir Machkaoutsan, Jan Willem Maes
  • Patent number: 9214597
    Abstract: A method for manufacturing a semiconductor device, includes: a step of etching a Si (111) substrate along a (111) plane of the Si (111) substrate to separate a Si (111) thin-film device having a separated surface along the (111) plane.
    Type: Grant
    Filed: June 6, 2013
    Date of Patent: December 15, 2015
    Assignee: Oki Data Corporation
    Inventors: Mitsuhiko Ogihara, Tomohiko Sagimori, Takahito Suzuki, Masataka Muto
  • Patent number: 9190555
    Abstract: Solar cell structures formed using molecular beam epitaxy (MBE) that can achieve improved power efficiencies in relation to prior art thin film solar cell structures are provided. A reverse p-n junction solar cell device and methods for forming the reverse p-n junction solar cell device using MBE are described. A variety of n-p junction and reverse p-n junction solar cell devices and related methods of manufacturing are provided. N-intrinsic-p junction and reverse p-intrinsic-n junction solar cell devices are also described.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: November 17, 2015
    Assignee: URIEL SOLAR, INC.
    Inventor: James David Garnett
  • Patent number: 9089057
    Abstract: An electronic device includes a conductor plate, a circuit board placed with a distance to a surface of the conductor plate, a connector provided on the circuit board, a flexible cable having one end connected to the connector and laid down along the surface of the conductor plate, and a cable holding member which includes a sloped holding surface for holding at least part of a portion of the flexible cable ranging from the connector to the surface of the conductor plate and which is electrically connected to the conductor plate.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: July 21, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Kohei Masuda, Osamu Shibata, Yoshiyuki Saito
  • Patent number: 9070816
    Abstract: A thermoelectric conversion material in which the electron spatial distribution assumes a wire structure or a quasi-one-dimensional structure is fabricated. A mode of the present invention provides a thermoelectric conversion structure 100 of a single crystal 10 of SrTiO3 having a (210) plane surface or interface, and having, in the surface or interface, a concave-convex structure including terrace portions 12, 14 in (100) planes and step portions 16 extending along the surface in-plane [001] axis.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: June 30, 2015
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Yasushi Ogimoto
  • Patent number: 9024331
    Abstract: Disclosed is a semiconductor light emitting element (LC) provided with a substrate (110) having one surface on which plural hexagonal-pyramid-shaped protrusions (110b) are provided, a base layer (130) provided so as to be in contact with the surface on which the protrusions (110b) are provided, an n-type semiconductor layer (140) provided so as to be in contact with the base layer (130), a light emitting layer (150) provided so as to be in contact with the n-type semiconductor layer (140), and a p-type semiconductor layer (160) provided so as to be in contact with the light emitting layer (150). Each protrusion (110b) scatters light in lateral and oblique directions within the semiconductor light emitting element (LC). The protrusions are densely arranged on a substrate on which semiconductor layers are laminated, so that the light extraction efficiency is improved.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: May 5, 2015
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Yohei Sakano
  • Publication number: 20150115414
    Abstract: A sapphire structure with a metal substructure is disclosed. The sapphire structure with a metal substructure includes a sapphire structure and a metal substructure. The sapphire structure includes a flat surface and a concave portion on the flat surface. The metal substructure in the concave portion is bonded to an inner surface of the concave portion and includes a surface portion that is substantially flush with the flat surface.
    Type: Application
    Filed: August 18, 2014
    Publication date: April 30, 2015
    Inventors: Motohiro Umehara, Yoshinori Kubo
  • Patent number: 9018739
    Abstract: The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a semiconductor substrate; a first semiconductor layer on the semiconductor substrate; a second semiconductor layer surrounding the first semiconductor layer; a high k dielectric layer and a gate conductor formed on the first semiconductor layer; source/drain regions formed in the second semiconductor layer, wherein the second semiconductor layer has a slant sidewall in contact with the first semiconductor layer. The semiconductor device has an increased output current, an increased operating speed, and a reduced power consumption due to the channel region of high mobility.
    Type: Grant
    Filed: September 25, 2010
    Date of Patent: April 28, 2015
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Huilong Zhu, Qingqing Liang, Zhijiong Luo, Haizhou Yin
  • Patent number: 9018735
    Abstract: A silicon wafer and fabrication method thereof are provided. The silicon wafer includes a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer, the first denuded zone being formed with a depth ranging from approximately 20 ?m to approximately 80 ?m from the top surface, and a bulk area formed between the first denuded zone and a backside of the silicon wafer, the bulk area having a concentration of oxygen uniformly distributed within a variation of 10% over the bulk area.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: April 28, 2015
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Jung-Goo Park
  • Patent number: 9012253
    Abstract: Gallium nitride wafer substrate for solid state lighting devices, and associated systems and methods. A method for making an SSL device substrate in accordance with one embodiment of the disclosure includes forming multiple crystals carried by a support member, with the crystals having an orientation selected to facilitate formation of gallium nitride. The method can further include forming a volume of gallium nitride carried by the crystals, with the selected orientation of the crystals at least partially controlling a crystal orientation of the gallium nitride, and without bonding the gallium nitride, as a unit, to the support member. In other embodiments, the number of crystals can be increased by a process that includes annealing a region in which the crystals are present, etching the region to remove crystals having an orientation other than the selected orientation, and/or growing the crystals having the selected orientation.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: April 21, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Anthony Lochtefeld, Hugues Marchand
  • Patent number: 9012887
    Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior to the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device including a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.
    Type: Grant
    Filed: October 24, 2011
    Date of Patent: April 21, 2015
    Assignee: Qunano AB
    Inventors: Lars Samuelson, Jonas Ohlsson, Thomas Mårtensson, Patrik Svensson
  • Publication number: 20150102469
    Abstract: A semiconductor structure includes a substrate and first and second crystalline semiconductor layers. The first crystalline semiconductor layer has a first crystal orientation, and includes a crystallized amorphous region formed on the substrate. The second crystalline semiconductor layer is formed on the substrate, is laterally disposed of the first crystalline semiconductor layer, and has a second crystal orientation different from the first crystal orientation. A method of fabricating the semiconductor structure is also disclosed.
    Type: Application
    Filed: September 5, 2014
    Publication date: April 16, 2015
    Inventors: JEAN-PIERRE COLINGE, CARLOS H. DIAZ
  • Patent number: 9000449
    Abstract: A semiconductor substrate that includes a semiconductor layer that exhibits high crystallinity includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine, and a semiconductor layer that is grown on the surface of the graphite layer, or includes a substrate that includes a graphite layer formed of a heterocyclic polymer obtained by condensing an aromatic tetracarboxylic acid and an aromatic tetramine on its surface, a buffer layer that is grown on the surface of the graphite layer, and a semiconductor layer that is grown on the surface of the buffer layer.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: April 7, 2015
    Assignees: The University of Tokyo, Tokai Carbon Co., Ltd., National Institute of Advanced Industrial Science and Technology
    Inventors: Hiroshi Fujioka, Tetsuro Hirasaki, Hitoshi Ue, Junya Yamashita, Hiroaki Hatori
  • Publication number: 20150069583
    Abstract: Provided are a III nitride semiconductor device which can be operated at a lower voltage can be provided, in which device a good ohmic contact is achieved between the (000-1) plane side of the III nitride semiconductor layer and the electrode and a method of producing the III nitride semiconductor device. A III nitride semiconductor device of the present invention includes a plurality of protrusions rounded like domes in a predetermined region on the (000-1) plane side of the III nitride semiconductor layer; and an electrode on the upper surface of the predetermined region.
    Type: Application
    Filed: December 12, 2012
    Publication date: March 12, 2015
    Inventors: Yoshitaka Kadowaki, Tatsunori Toyota
  • Patent number: 8963294
    Abstract: A method, structure and alignment procedure, for forming a finFET. The method including, defining a first fin of the finFET with a first mask and defining a second fin of the finFET with a second mask. The structure including integral first and second fins of single-crystal semiconductor material and longitudinal axes of the first and second fins aligned in the same crystal direction but offset from each other. The alignment procedure including simultaneously aligning alignment marks on a gate mask to alignment targets formed separately by a first masked used to define the first fin and a second mask used to define the second fin.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Jochen Beintner, Thomas Ludwig, Edward Joseph Nowak
  • Patent number: 8963165
    Abstract: A nitride semiconductor structure in which a first nitride semiconductor underlying layer is provided on a substrate having a recess portion and a projection portion provided between the recess portions at a surface thereof, the first nitride semiconductor underlying layer has at least 6 first oblique facet planes surrounding the projection portion on an outer side of the projection portion, and a second nitride semiconductor underlying layer buries the first oblique facet planes, a nitride semiconductor light emitting element, a nitride semiconductor transistor element, a method of manufacturing a nitride semiconductor structure, and a method of manufacturing a nitride semiconductor element are provided.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: February 24, 2015
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Masahiro Araki, Shinya Yoshida, Haruhisa Takiguchi, Atsushi Ogawa, Takao Kinoshita, Tohru Murata, Takeshi Funaki, Masayuki Hoteida
  • Patent number: 8961685
    Abstract: P-type silicon single crystals from which wafers having high resistivity, good radial uniformity of resistivity and less variation in resistivity can be obtained, are manufactured by the Czochralski method from an initial silicon melt in which boron and phosphorus are present, the boron concentration is not higher than 4E14 atoms/cm3 and the ratio of the phosphorus concentration to the boron concentration is not lower than 0.42 and not higher than 0.50.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: February 24, 2015
    Assignee: Siltronic AG
    Inventors: Katsuhiko Nakai, Masamichi Ohkubo
  • Patent number: 8946772
    Abstract: A substrate for epitaxial growth of the present invention comprises: a single crystal part comprising a material different from a GaN-based semiconductor at least in a surface layer part; and an uneven surface, as a surface for epitaxial growth, comprising a plurality of convex portions arranged so that each of the convex portions has three other closest convex portions in directions different from each other by 120 degrees and a plurality of growth spaces, each of which is surrounded by six of the convex portions, wherein the single crystal part is exposed at least on the growth space, which enables a c-axis-oriented GaN-based semiconductor crystal to grow from the growth space.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: February 3, 2015
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Hiroaki Okagawa, Hiromitsu Kudo, Teruhisa Nakai, Seong-Jin Kim
  • Patent number: 8933543
    Abstract: A nitride-based semiconductor device of the present invention includes: a nitride-based semiconductor multilayer structure 20 which includes a p-type semiconductor region with a surface 12 being inclined from the m-plane by an angle of not less than 1° and not more than 5°; and an electrode 30 provided on the p-type semiconductor region. The p-type semiconductor region is formed by an AlxInyGazN (where x+y+z=1, x?0, y?0, and z?0) layer 26. The electrode 30 includes a Mg layer 32 and an Ag layer 34 provided on the Mg layer 32. The Mg layer 32 is in contact with the surface 12 of the p-type semiconductor region of the semiconductor multilayer structure 20.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: January 13, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Toshiya Yokogawa, Mitsuaki Oya, Atsushi Yamada, Akihiro Isozaki
  • Publication number: 20140361414
    Abstract: Process and system for processing a thin film sample, as well as at least one portion of the thin film structure are provided. Irradiation beam pulses can be shaped to define at least one line-type beam pulse, which includes a leading portion, a top portion and a trailing portion, in which at least one part has an intensity sufficient to at least partially melt a film sample. Irradiating a first portion of the film sample to at least partially melt the first portion, and allowing the first portion to resolidify and crystallize to form an approximately uniform area therein. After the irradiation of the first portion of the film sample, irradiating a second portion using a second one of the line-type beam pulses to at least partially melt the second portion, and allowing the second portion to resolidify and crystallize to form an approximately uniform area therein.
    Type: Application
    Filed: June 23, 2014
    Publication date: December 11, 2014
    Inventors: James S Im, Paul Christiaan van der Wilt
  • Publication number: 20140345686
    Abstract: A method for forming wires, including providing catalytic seed particles suspended in a gas, providing gaseous precursors that comprise constituents of the wires to be formed and growing the wires from the catalytic seed particles. The wires may be grown in a temperature range between 425 and 525 C and may have a pure zincblende structure. The wires may be III-V semiconductor nanowires having a Group V terminated surface and a <111>B crystal growth direction.
    Type: Application
    Filed: February 1, 2013
    Publication date: November 27, 2014
    Inventors: Magnus Heurlin, Martin H. Magnusson, Knut Deppert, Lars Samuelson
  • Patent number: 8895448
    Abstract: To form a single crystal silicon membrane with a suspension layer, a single crystal silicon substrate with crystal orientation <111> is prepared. A doped layer is formed on the top surface of the single crystal silicon substrate. Multiple main etching windows are formed through the doped layer. A cavity is formed through the single crystal silicon substrate by anisotropic etching. The doped layer is above the cavity to form a suspension layer. If two electrode layers are formed on the two ends of the suspension layer, a micro-heater is constructed. The main etching windows extend in parallel to a crystal plane {111}. By both the single crystal structure and different impurity concentrations of the single crystal silicon substrate, the single crystal silicon substrate has a higher etch selectivity. When a large-area cavity is formed, the thickness of the suspension layer is still controllable.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: November 25, 2014
    Assignee: National Kaohsiung University of Applied Sciences
    Inventor: Chung-Nan Chen
  • Publication number: 20140335412
    Abstract: A process is provided for etching a silicon-containing substrate to form nanowire arrays. In this process, one deposits nanoparticles and a metal film onto the substrate in such a way that the metal is present and touches silicon where etching is desired and is blocked from touching silicon or not present elsewhere. One submerges the metallized substrate into an etchant aqueous solution comprising HF and an oxidizing agent. In this way arrays of nanowires with controlled diameter and length are produced.
    Type: Application
    Filed: July 28, 2014
    Publication date: November 13, 2014
    Applicant: BANDGAP ENGINEERING, INC.
    Inventors: Brent Buchine, Marcie R. Black, Faris Modawar
  • Patent number: 8883609
    Abstract: According to an embodiment, a method for manufacturing a semiconductor structure includes providing a first monocrystalline semiconductor portion having a first lattice constant in a reference direction and forming a second monocrystalline semiconductor portion having a second lattice constant in the reference direction, which is different to the first lattice constant, on the first monocrystalline semiconductor portion.
    Type: Grant
    Filed: November 21, 2013
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Mathias Plappert, Hans-Joachim Schulze
  • Patent number: 8878345
    Abstract: A structural body includes a sapphire underlying substrate; and a semiconductor layer of a group III nitride semiconductor disposed on the underlying substrate. An upper surface of the underlying substrate is a crystal surface tilted at an angle of 0.5° or larger and 4° or smaller with respect to a normal line of an a-plane which is orthogonal to an m-plane and belongs to a {11-20} plane group, from the m-plane which belongs to a {1-100} plane group.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: November 4, 2014
    Assignee: AETech Corporation
    Inventors: Takafumi Yao, Hyun-Jae Lee, Katsushi Fujii
  • Patent number: 8878230
    Abstract: A large-area, high-purity, low-cost single crystal semi-insulating gallium nitride that is useful as substrates for fabricating GaN devices for electronic and/or optoelectronic applications is provided. The gallium nitride is formed by doping gallium nitride material during ammonothermal growth with a deep acceptor dopant species, e.g., Mn, Fe, Co, Ni, Cu, etc., to compensate donor species in the gallium nitride, and impart semi-insulating character to the gallium nitride.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: November 4, 2014
    Assignee: Soraa, Inc.
    Inventor: Mark P. D'Evelyn
  • Publication number: 20140319513
    Abstract: A semiconductor device includes a substrate having a hexagonal crystalline structure and a (0001) surface, and conductive films on the surface of the substrate. The conductive films include a first conductive film and a second conductive film located above the first conductive film with respect to the surface, wherein the first conductive film has a crystalline structure which does not have a plane that has a symmetry equivalent to the symmetry of atomic arrangement in the surface of the substrate, the second conductive film has a crystalline structure having at least one plane that has a symmetry equivalent to the symmetry of atomic arrangement in the surface of the substrate, and the second conductive film is polycrystalline and has a grain size no larger than 15 ?m.
    Type: Application
    Filed: January 24, 2014
    Publication date: October 30, 2014
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kazuhiro Maeda, Toshihiko Shiga
  • Patent number: 8872309
    Abstract: Group-III nitride crystal composites made up of especially processed crystal slices, cut from III-nitride bulk crystal, whose major surfaces are of {1-10±2}, {11-2±2}, {20-2±1} or {22-4±1} orientation, disposed adjoining each other sideways with the major-surface side of each slice facing up, and III-nitride crystal epitaxially present on the major surfaces of the adjoining slices, with the III-nitride crystal containing, as principal impurities, either silicon atoms or oxygen atoms.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: October 28, 2014
    Assignee: Sumitomo Electronic Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Publication number: 20140299974
    Abstract: A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of the protruding portions taken along planes orthogonal to the surface of the substrate may be semi-circular in shape. The cross sections of the protruding portions may in alternative be convex in shape. A buffer layer and a GaN layer may be formed on the substrate.
    Type: Application
    Filed: June 26, 2014
    Publication date: October 9, 2014
    Inventors: Isamu NIKI, Motokazu YAMADA, Masahiko SANO, Shuji SHIOJI
  • Patent number: 8853746
    Abstract: The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xiangdong Chen, Thomas W. Dyer, Kenneth Settlemyer, Haining S. Yang
  • Patent number: 8847363
    Abstract: A method for producing a Group III nitride crystal includes the steps of cutting a plurality of Group III nitride crystal substrates 10p and 10q having a major surface from a Group III nitride bulk crystal 1, the major surfaces 10pm and 10qm having a plane orientation with an off-angle of five degrees or less with respect to a crystal-geometrically equivalent plane orientation selected from the group consisting of {20?21}, {20?2?1}, {22?41}, and {22?4?1}, transversely arranging the substrates 10p and 10q adjacent to each other such that the major surfaces 10pm and 10qm of the substrates 10p and 10q are parallel to each other and each [0001] direction of the substrates 10p and 10q coincides with each other, and growing a Group III nitride crystal 20 on the major surfaces 10pm and 10qm of the substrates 10p and 10q.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: September 30, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Koji Uematsu, Hideki Osada, Seiji Nakahata, Shinsuke Fujiwara
  • Patent number: 8841756
    Abstract: Methods for forming {110} type facets on a (001) oriented substrate of Group III-V compounds and Group IV semiconductors using selective epitaxial growth is provided. The methods include forming a dielectric film on a (100) substrate. The dielectric film can then be patterned to expose a portion of the substrate and to form a substrate-dielectric film boundary substantially parallel to a <110> direction. A {110} type sidewall facet can then be formed by epitaxially growing a semiconductor layer on the exposed portion of the substrate and the dielectric film.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: September 23, 2014
    Assignee: STC.UNM
    Inventors: Seung-Chang Lee, Steven R. J. Brueck
  • Publication number: 20140264325
    Abstract: One aspect of the present invention is a double sided hybrid crystal structure including a trigonal Sapphire wafer containing a (0001) C-plane and having front and rear sides. The Sapphire wafer is substantially transparent to light in the visible and infrared spectra, and also provides insulation with respect to electromagnetic radio frequency noise. A layer of crystalline Si material having a cubic diamond structure aligned with the cubic <111> direction on the (0001) C-plane and strained as rhombohedron to thereby enable continuous integration of a selected (SiGe) device onto the rear side of the Sapphire wafer. The double sided hybrid crystal structure further includes an integrated III-Nitride crystalline layer on the front side of the Sapphire wafer that enables continuous integration of a selected III-Nitride device on the front side of the Sapphire wafer.
    Type: Application
    Filed: March 11, 2014
    Publication date: September 18, 2014
    Applicant: U.S.A. as represented by the Administrator of the National Aeronautics and Space Administration
    Inventors: Yeonjoon Park, Sang Hyouk Choi
  • Publication number: 20140264776
    Abstract: A semiconductor wafer contains the following layers in the given order: a monocrystalline substrate wafer (1) consisting predominantly of silicon and having a (111) surface orientation, a monocrystalline layer (3) of Sc2O3 having a (111) surface orientation, a monocrystalline layer (4) of ScN having a (111) surface orientation, and a monocrystalline layer (6) of AlzGa1-zN with 0?z?1 having a (0001) surface orientation, the semiconductor wafers are produced by appropriate deposition of the respective layers.
    Type: Application
    Filed: March 5, 2014
    Publication date: September 18, 2014
    Applicant: Siltronic AG
    Inventors: Sarad Bahadur Thapa, Thomas Schroeder, Lidia Tarnawska
  • Patent number: RE45165
    Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: September 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wei Chen, Tang-Xuan Zhong, Sheng-Da Liu, Chang-Yu Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang
  • Patent number: RE45180
    Abstract: A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: October 7, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Wei Chen, Tang-Xuan Zhong, Sheng-Da Liu, Chang-Yun Chang, Ping-Kun Wu, Chao-Hsiung Wang, Fu-Liang Yang