Major Crystal Plane Or Axis Other Than (100), (110), Or (111) (e.g., (731) Axis, Crystal Plane Several Degrees From (100) Toward (011), Etc.) Patents (Class 257/628)
  • Patent number: 7615849
    Abstract: In a semiconductor device having SiC vertical trench MOSFETs, it is aimed to prevent the generation of large scattering in the channel resistance without largely increasing the average value of channel resistance. A 4H-SiC substrate having a major face thereof that is generally a {0001} face and having an off angle ?. The trench is formed with the standard deviation ? in scattering of the angle formed by a trench side wall face and a substrate major face within a wafer face. By setting the designed value of the angle formed by the trench side wall face and the substrate major face at an any angle ranging from [(60 degrees)+2?] to [(90 degrees)?tan?1 (0.87×tan ?)?2?] in forming the trench in the SiC substrate, a semiconductor device in which the angle formed by the trench side wall face and the substrate major face is 60 degrees or more but not more than [(90 degrees)?tan?1 (0.87×tan ?)] can be obtained.
    Type: Grant
    Filed: September 11, 2006
    Date of Patent: November 10, 2009
    Assignee: Fuji Electric Holdings Co., Ltd.
    Inventors: Shun-Ichi Nakamura, Yoshiyuki Yonezawa, Hiroyuki Fujisawa, Takashi Tsuji
  • Publication number: 20090267196
    Abstract: The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.
    Type: Application
    Filed: July 9, 2009
    Publication date: October 29, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas W. Dyer, Haining S. Yang
  • Patent number: 7608525
    Abstract: A method for manufacturing a nitride semiconductor substrate comprises the steps of: growing a first nitride semiconductor on a substrate, patterning the first nitride semiconductor to obtain a pattern surrounded by a plane equivalent to the (11-20) plane and having at least two concave portions that are similar in their planar shape, and growing a second nitride semiconductor layer, using a plane equivalent to the (11-20) plane in the first nitride semiconductor pattern as a growth nucleus.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: October 27, 2009
    Assignee: Nichia Corporation
    Inventor: Toru Takasone
  • Patent number: 7605447
    Abstract: The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.
    Type: Grant
    Filed: September 22, 2005
    Date of Patent: October 20, 2009
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Gregory Costrini, Oleg Gluschenkov, Meikei Ieong, Nakgeuon Seong
  • Patent number: 7595544
    Abstract: An object of the present invention is to provide a semiconductor device and a manufacturing method thereof which can realize a normally-off field-effect transistor made of a III group nitride semiconductor. The present invention includes: placing a sapphire substrate in a crystal growth chamber; forming a low-temperature GaN buffer layer made of GaN as the III group nitride semiconductor, on a main surface of the sapphire substrate by a MOCVD method; and forming a GaN layer on the low-temperature GaN buffer layer by the MOCVD method. Here, a [11-20] axis of the GaN layer is perpendicular to the main surface of the sapphire substrate.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: September 29, 2009
    Assignee: Panasonic Corporation
    Inventors: Masayuki Kuroda, Hidetoshi Ishida, Tetsuzo Ueda
  • Patent number: 7582516
    Abstract: The present invention relates to a semiconductor substrate comprising at least first and second device regions. The first device region has a substantially planar surface oriented along one of a first set of equivalent crystal planes, and the second device region contains a protruding semiconductor structure having multiple intercepting surfaces oriented along a second, different set of equivalent crystal planes. A semiconductor device structure can be formed using such a semiconductor substrate. Specifically, a first field effect transistor (FET) can be formed at the first device region, which comprises a channel that extends along the substantially planar surface of the first device region. A second, complementary FET can be formed at the second device region, while the second, complementary FET comprises a channel that extends along the multiple intercepting surfaces of the protruding semiconductor structure at the second device region.
    Type: Grant
    Filed: June 6, 2006
    Date of Patent: September 1, 2009
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Sunfei Fang, Judson R. Holt
  • Patent number: 7573123
    Abstract: Provided are a semiconductor device, and a method of forming the same. In one embodiment, the semiconductor device includes a semiconductor layer, first and second semiconductor fins, an insulating layer, and an inter-fin connection member. The first and second semiconductor fins are placed on the semiconductor layer, and have different crystal directions. The first semiconductor fin is connected to the semiconductor layer, and has the equivalent crystal direction as that of the semiconductor layer. The insulating layer is interposed between the second semiconductor fin and the semiconductor layer, and has an opening in which the first semiconductor fin is inserted. The inter-fin connection member connects the first semiconductor fin and the second semiconductor fin together on the insulating layer.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: August 11, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Soo Park, Kyoo-Chul Cho, Hee-Sung Kim, Tae-Soo Kang, Sam-Jong Choi
  • Patent number: 7566949
    Abstract: The present invention relates to high performance three-dimensional (3D) field effect transistors (FETs). Specifically, a 3D semiconductor structure having a bottom surface oriented along one of a first set of equivalent crystal planes and multiple additional surfaces oriented along a second, different set of equivalent crystal planes can be used to form a high performance 3D FET with carrier channels oriented along the second, different set of equivalent crystal planes. More importantly, such a 3D semiconductor structure can be readily formed over the same substrate with an additional 3D semiconductor structure having a bottom surface and multiple additional surfaces all oriented along the first set of equivalent crystal planes. The additional 3D semiconductor structure can be used to form an additional 3D FET, which is complementary to the above-described 3D FET and has carrier channels oriented along the first set of equivalent crystal planes.
    Type: Grant
    Filed: April 28, 2006
    Date of Patent: July 28, 2009
    Assignee: International Business Machines Corporation
    Inventors: Thomas W. Dyer, Haining S. Yang
  • Publication number: 20090179269
    Abstract: A chip can include a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. An SOI device is disposed in a semiconductor-on-insulator (“SOI”) layer separated from the bulk region of the substrate by a buried dielectric layer, the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor (“PFET”) and the SOI device includes an n-type field effect transistor (“NFET”) device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor in conductive communication with a gate conductor of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region.
    Type: Application
    Filed: December 22, 2008
    Publication date: July 16, 2009
    Inventors: Terence B. Hook, Anda C. Mocuta, Jeffrey W. Sleight, Anthony K. Stamper
  • Patent number: 7524708
    Abstract: A light emitting diode includes a substrate tilted toward first and second directions simultaneously, a first cladding layer formed with a semiconductor material of a first conductive type on the substrate, an active layer formed on the first cladding layer, and a second cladding layer formed with a semiconductor material of a second conductive type on the active layer, wherein concavo-convexes are formed on the interfaces of the first cladding layer, the second cladding layer, and the active layer.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: April 28, 2009
    Assignee: NeosemiTech Corporation
    Inventors: Joon-Suk Song, Soo-Hyung Seo, Myung-Hwan Oh
  • Patent number: 7521777
    Abstract: The object of the present invention is to provide a gallium nitride-based compound semiconductor multilayer structure useful for manufacturing a gallium nitride-based compound semiconductor light-emitting device which requires a low operating voltage and from which a good emission output can be obtained. The present gallium nitride-based compound semiconductor multilayer structure comprises a substrate having thereon an n-type layer, a light-emitting layer and a p-type layer, the light-emitting layer having a multiple quantum well structure in which a well layer and a barrier layer are alternately stacked repeatedly and the light-emitting layer being provided between the n-type layer and the p-type layer, wherein the well layers consisting of the multiple quantum well structure comprise a well layer having an ununiform thickness and a well layer having a uniform thickness.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: April 21, 2009
    Assignee: Showa Denko K.K.
    Inventors: Hisao Sato, Hisayuki Miki
  • Patent number: 7494918
    Abstract: Semiconductor structures and methods for fabrication thereof are predicated upon epitaxial growth of an epitaxial surface semiconductor layer upon a semiconductor substrate having a first crystallographic orientation. The semiconductor substrate is exposed within an aperture within a semiconductor-on-insulator structure. The epitaxial surface semiconductor layer alternatively contacts or is isolated from a surface semiconductor layer having a second crystallographic orientation within the semiconductor-on-insulator structure. A recess of the semiconductor surface layer with respect to a buried dielectric layer thereunder and a hard mask layer thereover provides for inhibited second crystallographic phase growth within the epitaxial surface semiconductor layer.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: February 24, 2009
    Assignees: International Business Machines Corporation, Advanced Micro Devices, Inc. (AMD)
    Inventors: Byeong Y. Kim, Xiaomeng Chen, Judson R. Holt, Christopher D. Sheraw, Linda Black, Igor Peidous
  • Publication number: 20090014844
    Abstract: A semiconductor device includes a first substrate, a plurality of cell transistors and a second substrate. The first substrate has a first surface and a second surface opposite to the first surface. The plurality of cell transistors is formed extending on the first surface of the first substrate in a direction. The second substrate has an upper surface making contact with the second surface of the first substrate. Further, the upper surface of the second substrate has a bent structure to apply tensile stresses to the first substrate in the extending direction of the plurality of cell transistors. Thus, tensile stresses may be applied to the first substrate to improve the mobility of carriers in a channel region of the cell transistors.
    Type: Application
    Filed: July 3, 2008
    Publication date: January 15, 2009
    Inventors: CHOONG-HO LEE, HEE-SOO KANG, KYU-CHARN PARK
  • Patent number: 7473946
    Abstract: A complementary metal oxide semiconductor (CMOS) structure includes a semiconductor substrate having first mesa having a first ratio of channel effective horizontal surface area to channel effective vertical surface area. The CMOS structure also includes a second mesa having a second ratio of the same surface areas that is greater than the first ratio. A first device having a first polarity uses the first mesa as a channel and benefits from the enhanced vertical crystallographic orientation. A second device having a second polarity different from the first polarity uses the second mesa as a channel and benefits from the enhanced horizontal crystallographic orientation.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: January 6, 2009
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
  • Patent number: 7473985
    Abstract: A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided.
    Type: Grant
    Filed: June 16, 2005
    Date of Patent: January 6, 2009
    Assignee: International Business Machines Corporation
    Inventors: Louis Lu-Chen Hsu, Jack Allan Mandelman, William Robert Tonti
  • Patent number: 7470973
    Abstract: In each of a p-channel MOS transistor and an n-channel MOS transistor, a channel direction is set in the <100> direction and a first stressor film accumulating therein a tensile stress is formed in a STI device isolation structure. Further, a second stressor film accumulating therein a tensile stress is formed on a silicon substrate so as to cover the device isolation structure.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: December 30, 2008
    Assignee: Fujitsu Limited
    Inventor: Yoshihiro Takao
  • Patent number: 7459720
    Abstract: The present invention provides a single crystal wafer, wherein the main surface has a plane or a plane equivalent to a plane tilting with respect to a [100] axis of single crystal by angles of ? (0°<?<90°) for the [011] direction, ? (0°<?<90°) for the [01-1] direction and ? (0°??<45°) for the [10-1] or [101] direction. Thus, a single crystal wafer that can sufficiently bear device production processes even with a small wafer thickness is provided and thereby loss of single crystal raw material is reduced. Further, by using such a wafer, MIS type semiconductor devices and solar cells are provided at a low cost.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: December 2, 2008
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Tatsuo Ito, Koichi Kanaya
  • Patent number: 7456040
    Abstract: The present invention is to provide a method for manufacturing a semiconductor optical device, in which the unevenness of the burying of the mesa structure may be reduced. The process is configured to form a mask extending along [011] direction on the cap layer, to form a mesa structure by etching the upper cladding layer made of InP, the active region, and the lower cladding layer, to form a surfaces with the (01-1) and the (0-11) planes on both sides of the mesa structure, respectively, by causing the mass transportation, and finally to form the blocking layer by using the mask formed in advance. A semiconductor region with the second conduction type, which is the same with that of the upper cladding layer and is different from that of the lower cladding layer, is grown on the upper cladding layer after removing the mask and the cap layer.
    Type: Grant
    Filed: December 11, 2006
    Date of Patent: November 25, 2008
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kouichiro Yamazaki, Kenji Hiratsuka
  • Publication number: 20080283851
    Abstract: GaN substrate (30) whose growth plane (30a) is oriented off-axis with respect to either the m-plane or the a-plane. That is, in the GaN substrate (30), the growth plane (30a) is either an m-plane or an a-plane that has been misoriented. Inasmuch as the m-plane and the a-plane are nonpolar, utilizing the GaN substrate (30) to fabricate a semiconductor light-emitting device (60) averts the influence of piezoelectric fields, making it possible to realize superior emission efficiency. Imparting to the growth plane the off-axis angle in terms of either the m-plane or the a-plane realizes high-quality morphology in crystal grown on the substrate. Utilizing the GaN substrate to fabricate semiconductor light-emitting devices enables as a result the realization of further improved emission efficiency.
    Type: Application
    Filed: May 14, 2008
    Publication date: November 20, 2008
    Applicant: Sumitomo Electric Industries, Ltd.
    Inventor: Katsushi Akita
  • Patent number: 7449767
    Abstract: The present disclosure relates, generally, to a semiconductor substrate with a planarized surface comprising mixed single-crystal orientation regions and/or mixed single-crystal semiconductor material regions, where each region is electrically isolated. In accordance with one embodiment of the disclosure CMOS devices on SOI regions are manufactured on semiconductors having different orientations. According to another embodiment, an SOI device is contemplated as having a plurality of semiconductor regions having at least one of a different semiconductor material, crystalline lattice constant or lattice strain. Methods and processes for fabricating the different embodiments of the invention is also disclosed.
    Type: Grant
    Filed: September 19, 2006
    Date of Patent: November 11, 2008
    Assignee: International Business Machines Corporation
    Inventors: Guy M. Cohen, Alexander Reznicek, Katherine L. Saenger, Min Yang
  • Patent number: 7446361
    Abstract: A capacitor includes a pair of electrodes and a ferroelectric film sandwiched between the electrodes. The electrodes are provided perpendicular to the direction of the polarization axis of the ferroelectric film.
    Type: Grant
    Filed: May 4, 2005
    Date of Patent: November 4, 2008
    Assignee: Fujitsu Limited
    Inventor: Kenji Maruyama
  • Patent number: 7432570
    Abstract: A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: October 7, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masato Koyama, Reika Ichihara, Yoshinori Tsuchiya, Yuuichi Kamimuta, Akira Nishiyama
  • Patent number: 7432558
    Abstract: A semiconductor device may include a substrate and an insulating layer formed on the substrate. A fin may be formed on the insulating layer. The fin may include a side surface and a top surface, and the side surface may have a <100> orientation. A first gate may be formed on the insulating layer proximate to the side surface of the fin.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: October 7, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Shibly S. Ahmed, Judy Xilin An, Srikanteswara Dakshina-Murthy, Cyrus E. Tabery, Bin Yu
  • Patent number: 7429763
    Abstract: One aspect of the present invention relates to a method for forming a strained semiconductor structure. In various embodiments, at least two strong bonding regions are defined for a desired bond between a crystalline semiconductor membrane and a crystalline semiconductor substrate. The two strong bonding regions are separated by a weak bonding region. The membrane is bonded to the substrate at a predetermined misorientation. The membrane is pinned to the substrate in the strong bonding regions. The predetermined misorientation provides the membrane in the weak bonding region with a desired strain. In various embodiments, the membrane is bonded to the substrate at a predetermined twist angle to biaxially strain the membrane in the weak bonding region. In various embodiments, the membrane is bonded to the substrate at a predetermined tilt angle to uniaxially strain the membrane in the weak bonding region. Other aspects are provided herein.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: September 30, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Publication number: 20080217745
    Abstract: A nitride semiconductor substrate having properties preferable for the manufacture of various nitride semiconductor devices is made available, by specifying or controlling the local variation in the off-axis angle of the principal surface of the nitride semiconductor substrate. The substrate, being misoriented, is manufactured to have an off-axis angle distribution across its principal surface such that variation ?? in the off-axis angle is continuous within a predetermined angular range.
    Type: Application
    Filed: May 19, 2008
    Publication date: September 11, 2008
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Michimasa Miyanaga, Koji Uematsu, Takuji Okahisa
  • Patent number: 7420261
    Abstract: The invention relates to a substrate for epitaxy, especially for preparation of nitride semiconductor layers. Invention covers a bulk nitride mono-crystal characterized in that it is a mono-crystal of gallium nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium nitride has a surface area greater than 100 mm2, it is more than 1,0 ?m thick and its C-plane surface dislocation density is less than 106/cm2, while its volume is sufficient to produce at least one further-processable non-polar A-plane or M-plane plate having a surface area at least 100 mm2. More generally, the present invention covers a bulk nitride mono-crystal which is characterized in that it is a mono-crystal of gallium-containing nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium-containing nitride has a surface area greater than 100 mm2, it is more 1,0-?m thick and its surface dislocation density is less than 106/cm2.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: September 2, 2008
    Assignees: AMMONO Sp. z o.o., Nichia Corporation
    Inventors: Robert Dwiliński, Roman Doradziński, Jerzy Garczynski, Leszek P. Sierzputowski, Yasuo Kanbara
  • Patent number: 7411273
    Abstract: In an independent GaN film manufactured by creating a GaN layer on a base heterosubstrate using vapor-phase deposition and then removing the base substrate, owing to layer-base discrepancy in thermal expansion coefficient and lattice constant, bow will be a large ±40 ?m to ±100 ?m. Since with that bow device fabrication by photolithography is challenging, reducing the bow to +30 ?m to ?20 ?m is the goal. The surface deflected concavely is ground to impart to it a damaged layer that has a stretching effect, making the surface become convex. The damaged layer on the surface having become convex is removed by etching, which curtails the bow. Alternatively, the convex surface on the side opposite the surface having become convex is ground to generate a damaged layer. With the concave surface having become convex due to the damaged layer, suitably etching off the damaged layer curtails the bow.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: August 12, 2008
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Naoki Matsumoto
  • Patent number: 7411274
    Abstract: The present invention has been made in order to manufacture a silicon semiconductor substrate used for a semiconductor integrated circuit device, higher in carrier mobility, especially in electron mobility, which is a carrier of an n-type FET, on a {100} plane as a main surface, and provides a silicon semiconductor substrate and a method for manufacturing the same, wherein the conventional RCA cleaning is employed without the use of special cleaning and the surface of the substrate is planarized at an atomic level to thereby decrease the surface roughness thereof without the use of the radical oxidation. The present invention provides a silicon semiconductor substrate comprising: a {110} plane or a plane inclined from a {110} plane as a main surface of the substrate; and steps arranged at an atomic level along a <110> orientation on the main surface.
    Type: Grant
    Filed: January 29, 2004
    Date of Patent: August 12, 2008
    Assignees: Shin-Etsu Handotai Co., Ltd.
    Inventors: Hideki Yamanaka, Kiyoshi Demizu, Tadahiro Ohmi, Akinobu Teramoto, Shigetoshi Sugawa
  • Patent number: 7400030
    Abstract: In the present invention, there is provided semiconductor devices such as a Schottky UV photodetector fabricated on n-type ZnO and MgxZn1-xO epitaxial films. The ZnO and MgxZn1-xO films are grown on R-plane sapphire substrates and the Schottky diodes are fabricated on the ZnO and MgxZn1-xO films using silver and aluminum as Schottky and ohmic contact metals, respectively. The Schottky diodes have circular patterns, where the inner circle is the Schottky contact, and the outside ring is the ohmic contact. Ag Schottky contact patterns are fabricated using standard liftoff techniques, while the Al ohmic contact patterns are formed using wet chemical etching. These detectors show low frequency photoresponsivity, high speed photoresponse, lower leakage current and low noise performance as compared to their photoconductive counterparts. This invention is also applicable to optical modulators, Metal Semiconductor Field Effect Transistors (MESFETs) and more.
    Type: Grant
    Filed: January 25, 2005
    Date of Patent: July 15, 2008
    Assignee: Rutgers, the State University of New Jersey
    Inventors: Yicheng Lu, Haifeng Sheng, Sriram Muthukumar, Nuri William Emanetoglu, Jian Zhong, Shaohua Liang
  • Publication number: 20080164578
    Abstract: A sapphire substrate includes a generally planar surface having a crystallographic orientation selected from the group consisting of a-plane, r-plane, m-plane, and c-plane orientations, and having a nTTV of not greater than about 0.037 ?m/cm2, wherein nTTV is total thickness variation normalized for surface area of the generally planar surface, the substrate having a diameter not less than about 9.0 cm.
    Type: Application
    Filed: December 21, 2007
    Publication date: July 10, 2008
    Applicant: SAINT-GOBAIN CERAMICS & PLASTICS, INC.
    Inventors: Brahmanandam V. Tanikella, Matthew A. Simpson, Palaniappan Chinnakaruppan, Robert A. Rizzuto, Isaac K. Cherian, Ramanujam Vedantham
  • Patent number: 7381993
    Abstract: In a semiconductor device of the present invention, the top surface of an n-type silicon carbide layer formed on a silicon carbide substrate is miscut from the (0001) plane in the <11-20> direction. A gate electrode, a source electrode and other elements are arranged such that in a channel region, the dominating current flows along a miscut direction. In the present invention, a gate insulating film is formed and then heat treatment is performed in an atmosphere containing a group-V element. In this way, the interface state density at the interface between the silicon carbide layer and the gate insulating film is reduced. As a result, the electron mobility becomes higher in a miscut direction A than in the direction perpendicular to the miscut direction A.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: June 3, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masao Uchida, Makoto Kitabatake, Osamu Kusumoto, Kenya Yamashita, Kunimasa Takahashi, Ryoko Miyanaga
  • Patent number: 7368763
    Abstract: A high quality silicon carbide (SiC) layer being substantially lower in threading dislocation density than a prior layer is formed on silicon (Si) substrate. A semiconductor device is fabricated in such a way that a semiconductor buffer layer containing Si in part and being higher in defect density than a Si substrate is formed on the Si substrate on the upper portion of which are formed a plurality of pairs of facets being mirror-symmetrical to the surface orientation of a semiconductor substrate, further on the top of the layer a SiC layer is sequentially formed.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: May 6, 2008
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Miura, Katsuya Oda, Katsuyoshi Washio
  • Patent number: 7348611
    Abstract: The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that the CMOS device channels are located along the <100> direction. Strain can be induced upon the CMOS structure including at least a pFET and optionally an nFET, particularly the channels, by forming a stressed liner about the FET, by forming embedded stressed wells in the substrate, or by utilizing a combination of embedded stressed wells and a stressed liner. The present invention also provides methods for fabricating the aforesaid semiconductor structures.
    Type: Grant
    Filed: April 22, 2005
    Date of Patent: March 25, 2008
    Assignee: International Business Machines Corporation
    Inventors: Meikei Ieong, Qiqing C. Ouyang, Kern Rim
  • Patent number: 7339255
    Abstract: A semiconductor substrate encompasses a GaN substrate and a single-crystal layer formed of III-V nitride compound semiconductor epitaxially grown on the GaN substrate. The GaN substrate has a surface orientation defined by an absolute value of an off-angle of the surface from {0001} plane towards <1?100> direction lying in a range of 0.12 degree to 0.35 degree and by an absolute value of an off-angle of the surface from {0001} plane towards <11?20> direction lying in a range of 0.00 degree to 0.06 degree.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: March 4, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Chie Hongo, Shinya Nunoue, Masaaki Onomura
  • Patent number: 7335910
    Abstract: An object of the present invention is to provide a thin film transistor having a high mobility and having fewer fluctuations in the mobility or threshold voltage characteristics. A non-single-crystal semiconductor thin film having a thickness of less than 50 nm and disposed on an insulating substrate is irradiated with laser light having an inverse-peak-patterned light intensity distribution to grow crystals unidirectionally in a lateral direction. Thus, band-like crystal grains having a dimension in a crystal growth direction, which is longer than a width, are arranged adjacent to each other in a width direction to form a crystal grain array. A source region and a drain region of a TFT are formed so that a current flows in the crystal growth direction in an area including a plurality of crystal grains of this crystal grain array.
    Type: Grant
    Filed: May 12, 2006
    Date of Patent: February 26, 2008
    Assignee: Advanced LCD Technologies Development Center Co., Ltd.
    Inventors: Tomoya Kato, Masakiyo Matsumura, Yoshiaki Nakazaki
  • Publication number: 20080029756
    Abstract: A composite buffer architecture for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm?2 to be formed on silicon substrates. In an embodiment of the present invention, a dual buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations and provide electrical isolation. In an embodiment of the present invention, the material of each buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a GaSb/AlSb buffer is utilized to form an InSb-based quantum well transistor on a silicon substrate.
    Type: Application
    Filed: August 2, 2006
    Publication date: February 7, 2008
    Inventors: Mantu K. Hudait, Mohamad A. Shaheen, Dmitri Loubychev, Amy W.K. Liu, Joel M. Fastenau
  • Patent number: 7307282
    Abstract: The TFT has a channel-forming region formed of a crystalline semiconductor film obtained by heat-treating and crystallizing an amorphous semiconductor film containing silicon as a main component and germanium in an amount of not smaller than 0.1 atomic % but not larger than 10 atomic % while adding a metal element thereto, wherein not smaller than 20% of the lattice plane {101} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, not larger than 3% of the lattice plane {001} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film, and not larger than 5% of the lattice plane {111} has an angle of not larger than 10 degrees with respect to the surface of the semiconductor film as detected by the electron backscatter diffraction pattern method.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: December 11, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara, Taketomi Asami, Tamae Takano, Takeshi Shichi, Chiho Kokubo, Yasuyuki Arai
  • Patent number: 7288821
    Abstract: A method and device for increasing pFET performance without degradation of nFET performance. The method includes forming a first structure on a substrate using a first plane and direction and forming a second structure on the substrate using a second plane and direction. In use, the device includes a nFET stack on a substrate using a first plane and direction, e.g., (100)<110> and a pFET stack on the substrate using a second plane and direction, e.g., (111)/<112>. An isolation region within the substrate is provided between the nFET stack and the pFET stack.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: October 30, 2007
    Assignee: International Business Machines Corporation
    Inventor: Oh-Jung Kwon
  • Patent number: 7285799
    Abstract: A semiconductor light emitting device includes a planar light emitting layer with a wurtzite crystal structure having a <0001> axis roughly parallel to the plane of the layer, referred to as an in-plane light emitting layer. The in-plane light emitting layer may include, for example, a {11 20} or {10 10} InGaN light emitting layer. In some embodiments, the in-plane light emitting layer has a thickness greater than 50 ?.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: October 23, 2007
    Assignee: Philip Lumileds Lighting Company, LLC
    Inventors: James C. Kim, Yu-Chen Shen
  • Patent number: 7282732
    Abstract: Symmetric quantum dots are embedded in quantum wells. The symmetry is achieved by using slightly off-axis substrates and/or overpressure during the quantum dot growth. The quantum dot structure can be used in a variety of applications, including semiconductor lasers.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: October 16, 2007
    Assignees: STC. unm, Innolume Acquisition, Inc.
    Inventors: Allen L Gray, Andreas Stintz, Kevin J Malloy, Luke F Lester, Petros M Varangis
  • Patent number: 7282379
    Abstract: Provided is a nitride semiconductor having a larger low-defective region on a surface thereof, a semiconductor device using the nitride semiconductor, a method of manufacturing a nitride semiconductor capable of easily reducing surface defects in a step of forming a layer through lateral growth, and a method of manufacturing a semiconductor device manufactured by the use of the nitride semiconductor. A seed crystal portion is formed into stripes on a substrate with a buffer layer sandwiched therebetween. Then, a crystal is grown from the seed crystal portion in two steps of growth conditions to form a nitride semiconductor layer. In a first step, a low temperature growth portion having a trapezoidal-shaped cross section in a layer thickness direction is formed at a growth temperature of 1030° C., and in a second step, lateral growth predominantly takes place at a growth temperature of 1070° C. Then, a high temperature growth potion is formed between the low temperature growth portions.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: October 16, 2007
    Assignee: Sony Corporation
    Inventors: Osamu Goto, Takeharu Asano, Motonobu Takeya, Katsunori Yanashima
  • Patent number: 7271467
    Abstract: Structures are provided for multiple oxide thicknesses on a single silicon wafer. In particular, structures are provided for multiple gate oxide thicknesses on a single chip. The chip can include circuitry including but not limited to the memory and logic technologies. These structures for multiple oxide thickness on a single silicon wafer can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity. One structure includes a top layer of SiO2 on a top surface of a silicon wafer and a trench layer of SiO2 on a trench wall of the silicon wafer. The trench wall of the silicon wafer has a different order plane-orientation than the top surface. The thickness of the top layer is different from a thickness of the trench layer.
    Type: Grant
    Filed: August 30, 2004
    Date of Patent: September 18, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Wendell P. Noble, Leonard Forbes
  • Patent number: 7268377
    Abstract: The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane of a planar hybrid substrate. The method of the present invention also improves the performance of creating SOI-like devices with a combination of a buried insulator and counter-doping layers. The present invention also relates to semiconductor structures that are formed utilizing the method of the present invention.
    Type: Grant
    Filed: February 25, 2005
    Date of Patent: September 11, 2007
    Assignee: International Business Machines Corporation
    Inventors: Meikei Ieong, Min Yang
  • Patent number: 7262485
    Abstract: A substrate 1 for growing an electro-optical single crystal thin film in which two or more layers of buffer layers 3, 4, and 5 for buffering lattice mismatch between Si and BTO are formed on an Si (001) substrate 2 is provided as a substrate for growing an electro-optical single crystal thin film which can obtain an electro-optical single crystal thin film of BTO single crystal thin film 6 etc. with a large size and a very high quality.
    Type: Grant
    Filed: July 6, 2005
    Date of Patent: August 28, 2007
    Assignee: Covalent Materials Corporation
    Inventors: Yoshihisa Abe, Shunichi Suzuki, Hideo Nakanishi, Jun Komiyama
  • Patent number: 7253483
    Abstract: A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction <100>) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.
    Type: Grant
    Filed: June 27, 2005
    Date of Patent: August 7, 2007
    Assignee: Chartered Semiconductor Manufacturing, LTD
    Inventors: Yisuo Li, Xiaohong Jiang, Francis Benistant
  • Patent number: 7226805
    Abstract: An epitaxial silicon carbide layer is fabricated by forming first features in a surface of a silicon carbide substrate having an off-axis orientation toward a crystallographic direction. The first features include at least one sidewall that is orientated nonparallel (i.e., oblique or perpendicular) to the crystallographic direction. A first epitaxial silicon carbide layer is then grown on the surface of the silicon carbide substrate that includes first features therein. Second features are then formed in the first epitaxial layer. The second features include at least one sidewall that is oriented nonparallel to the crystallographic direction. A second epitaxial silicon carbide layer is then grown on the surface of the first epitaxial silicon carbide layer that includes the second features therein.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: June 5, 2007
    Assignee: Cree, Inc.
    Inventors: Christer Hallin, Heinz Lendenmann, Joseph John Sumakeris
  • Patent number: 7214984
    Abstract: In a semiconductor device of the present invention, the top surface of an n-type silicon carbide layer formed on a silicon carbide substrate is miscut from the (0001) plane in the <11-20> direction. A gate electrode, a source electrode and other elements are arranged such that in a channel region, the dominating current flows along a miscut direction. In the present invention, a gate insulating film is formed and then heat treatment is performed in an atmosphere containing a group-V element. In this way, the interface state density at the interface between the silicon carbide layer and the gate insulating film is reduced. As a result, the electron mobility becomes higher in a miscut direction A than in the direction perpendicular to the miscut direction A.
    Type: Grant
    Filed: November 24, 2004
    Date of Patent: May 8, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masao Uchida, Makoto Kitabatake, Osamu Kusumoto, Kenya Yamashita, Kunimasa Takahashi, Ryoko Miyanaga
  • Patent number: 7208803
    Abstract: A method of forming a raised source/drain proximate a spacer of a gate of a transistor on a substrate, and a semiconductor device of an integrated circuit employing the same. In one embodiment, the method includes orienting the gate substantially along a <100> direction of the substrate. The method also includes providing a semiconductor material adjacent the spacer of the gate to form a raised source/drain layer of the raised source/drain oriented substantially along a <100> direction of the substrate.
    Type: Grant
    Filed: May 5, 2004
    Date of Patent: April 24, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Steve Ming Ting
  • Patent number: 7205639
    Abstract: Integrated circuits are oriented on a substrate at an angle that is rotated between 0 to 45 degrees from a direction parallel or perpendicular to a preferred crystalline plane direction, such as the cleavage plane, of the substrate. Parameters such as stress and mobility of transistors may be optimized by adjusting the angle of rotation of the substrate. For a rotated substrate CMOS device design, other stress control measures may be used, such as a stress control or tensile liner, over an NMOS transistor, PMOS transistor, or both, to further adjust the stress and improve performance.
    Type: Grant
    Filed: March 9, 2005
    Date of Patent: April 17, 2007
    Assignees: Infineon Technologies AG, International Business Machines Corporation
    Inventors: Matthias Hierlemann, Chun-Yung Sung, Brian J. Greene, Manfred Eller
  • Patent number: 7199451
    Abstract: An assembly and method of making the same wherein the assembly incorporates a rare-earth oxide film to form a [110] crystal lattice orientation semiconductor film. The assembly comprises a substrate, a rare-earth oxide film formed on the substrate, and a [110]-oriented semiconductor film formed on the rare-earth oxide film. The rare-earth oxide film having a [110] crystal lattice orientation. The substrate has a [001] crystal lattice orientation.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: April 3, 2007
    Assignee: Intel Corporation
    Inventor: Maxim B. Kelman