Abstract: A semiconductor device comprising single crystal films consisting of at least one III-V nitride selected from the group consisting of gallium nitride, aluminum nitride, boron nitride, indium nitride, and single-crystalline alloys of these nitrides, the single crystal films being provided on a single crystal substrate of aluminum nitride either directly or through a low-temperature growth buffer layer of at least one III-V nitride. This semiconductor device is useful as a short-wavelength light emitting device capable of conducting continuous oscillation or a diode which is operated at a high temperature. The AlN single crystal substrate is matched in lattice constant and coefficient of thermal expansion with the single crystal film of a III-V nitride and the single crystal films is grown with good crystallinity on the substrate.

Abstract: Prevention of reduction in the production yield due to the increase in the area of a semiconductor chip permits a sophisticated-performance single-chip semiconductor device to be fabricated. This also permits a many-kind small-amount production of semiconductor devices to be implemented. After plural semiconductor chips 2 and 3 are fabricated separately, only defect-free chips of them are selected. The selected defect-free chips are connected in contact between their side walls of their densest faces of atoms of their substrates so that the surfaces 4a and 4b where elements are to be formed are located in the same plane. Thus, even when the chip area is increased, reduction of the production yield can be prevented, thereby permitting a large-area sophisticated-performance single chip semiconductor device to be fabricated.

Abstract: A semiconductor integrated circuit device including: an off-substrate having a semiconductor surface with a plurality of steps each having a height of one monolayer and extending in one direction; a wiring layer formed on the semiconductor surface of the off-substrate and made of semiconductor material, the wiring layer including a plurality of conductive stripe regions and high resistance strip regions disposed in a stripe pattern, each stripe region extending in a direction parallel with the steps, and the conductive stripe regions and the high resistance stripe regions both having lattice structures identical to those of underlying surfaces; and semiconductor elements formed on the wiring layer and electrically connected to the conductive stripe regions, the semiconductor elements including semiconductor regions with lattice structures identical to those of the conductive stripe regions.

Abstract: A silicon layer serving as a contact plug directly connected to a diffusion layer of a MOS transistor is provided. On a surface of an N.sup.- type diffusion layer in self-alignment with a silicon nitride layer spacer and a field oxide layer, an N.sup.+ type monocrystalline silicon layer formed by anisotropic selective epitaxial growth method is directly connected. The surface of the N.sup.+ type monocrystalline silicon layer is directly connected to an N.sup.+ type monocrystalline silicon layer formed by isotropic selective epitaxial growth.

Abstract: A semiconductor device includes a semiconductor substrate; a semiconductor laminated structure including a first barrier layer, a conduction layer including a natural superlattice, and a second barrier layer, disposed on the semiconductor substrate. The first barrier layer, the conduction layer, and the second barrier layer produce heterojunctions that confine charge carriers within the conduction layer. The first barrier layer has steps at the surface contacting the conduction layer, the steps including, alternatingly arranged, a first crystal plane having a first orientation and a second crystal plane having a second orientation. The conduction layer includes first portions where the natural superlattice is ordered and second portions where the natural superlattice is disordered, the first and second portions being disposed on the first and second crystal planes, respectively. The degree of order in the conduction layer is higher in the first portions than in the second portions.

Abstract: An insulated gate FET such as a power MOS FET is made by forming a rectangular parallelepiped-shaped recess in a direction that the side walls of the recess make 45.degree. angle against the <100> direction of the silicon substrate having (100) plane as principal surface, and the vertical side walls of (010) or (001) planes are used as channel region of the insulated gate FET, thereby assuring a large electron mobility in the channel, hence low channel resistance suitable for high power operation.

Abstract: The present invention is intended to provide a semiconductor optoelectric device with high luminescent efficiency and a method of manufacturing the same. The semiconductor optoelectric device 18 according to the present invention is constructed by depositing compound-semiconductor layers 13 and 14 on a monocrystalline substrate 11 of a hexagonal close-packed structure. The shape of the monocrystalline substrate 11 is a parallelogram. Individual sides of the parallelogram are parallel to a <11-20> orientation. As the monocrystalline substrate, sapphire, zinc oxide or silicon carbide may be used. As the compound-semiconductor layers, an n-type GaN layer 13 and p-type GaN layer 14 may be used.

Abstract: A silicon wafer has a polycrystalline silicon film formed on one main surface. The polycrystalline silicon film has a multilayer structure composed of X layers (X is an integer equal to or greater than two) containing <220> oriented components in different proportions. The proportion of the <220> oriented component in the first polycrystalline silicon layer in contact with the silicon wafer is larger than the respective proportions of the <220> oriented components in the second to X-th polycrystalline silicon layers superposed on the first polycrystalline silicon layer. It becomes possible to provide a silicon wafer whose polycrystalline silicon film possesses high gettering capability and in which stress acting on the silicon wafer is decreased.

Abstract: A process for manufacturing a field emission element including a substrate, and an emitter and a gate each arranged on the substrate is provided. The emitter is formed at at least a tip portion thereof with an electron discharge section, which is formed of metal or semiconductor into a monocrystalline structure or a polycrystalline structure preferentially oriented in at least a direction perpendicular to the substrate by deposition.

Abstract: In the vicinity of the (100) plane, planar channeling by (100) type crystal planes, which are (011) plane and (011) plane according to the (100) surface plane, degrades uniformity of ion implantation. Therefore, a major surface of the substrate is established at a plane perpendicular to a crystal orientation forming an angle greater than or equal to 3.5.degree. with two planes perpendicularly intersecting the (100) plane. Namely, in consideration of fluctuation in setting to an ion implantation device and ion implantation angle, the substrate having surface orientation within a range 104 is employed. Also, by limiting the orientation to be less than or equal to 10.degree. from the (100) plane, ion implantation can be performed perpendicularly to the substrate without modifying the process condition.

Abstract: In a heterostructure III-V nitride semiconductor device, an InP substrate has a surface having a sloped angle of 0.degree. to 16.degree. with respect to a (100) surface thereof. At least one GaN layer is formed on the InP substrate.

Abstract: A semiconductor device having high carrier mobility, which comprises a substrate provided thereon a base film and further thereon a crystalline non-single crystal silicon film by crystal growth, wherein, the crystals are grown along the crystallographic ?110! axis, and source/drain regions are provided approximately along the direction of carrier movement which coincides to the direction of crystal growth. Moreover, the electric conductivity along this direction of crystal growth is higher than any in other directions.

Abstract: A gallium nitride type compound semiconductor light emitting element, such as a semiconductor laser, a light emitting diode is constructed by forming an In.sub.0.06 Ga.sub.0.94 N buffer layer, an n-type In.sub.0.06 Ga.sub.0.94 N clad layer, an n-type In.sub.0.06 Al.sub.0.15 Ga.sub.0.79 N clad layer, an undoped GaN active layer having layer thickness of 50 nm, a p-type In.sub.0.06 Al.sub.0.15 Ga.sub.0.79 N clad layer and a p-type In.sub.0.06 Ga.sub.0.94 N cap layer on a (0001) azimuth sapphire substrate. A p-side electrode is formed on the p-type In.sub.0.06 Ga.sub.0.94 N cap layer, and an n-side electrode is formed on the n-type In.sub.0.06 Ga.sub.0.94 N clad layer. In the construction set forth above, a greater thickness for the active layer is provided. Also, tensile strain is applied to the active layer. Light is taken out in parallel direction to the substrate. This threshold current of the semiconductor laser is lowered and light emitting efficiency of the light emitting diode is improved.

Abstract: A method for assembling microstructures onto a substrate through fluid transport. The microstructures being shaped blocks self-align into recessed regions located on a substrate such that the microstructure becomes integral with the substrate 20, 70, 90, 120, 200. The improved method includes a step of transferring the shaped blocks into a fluid to create a slurry. Such slurry is then poured evenly over the top surface of a substrate having recessed regions thereon. The microstructure via the shape and fluid tumbles onto the surface of the substrate, self-aligns, and engages into a recessed region.

Abstract: A compound semiconductor device includes a compound semiconductor layer having an upper major surface formed with a multi-step structure, wherein said multi-step structure includes a plurality of steps each having a step height of at least 5 atomic layers and a step width of 300 nm or more.

Abstract: To provide a field-effect transistor having a large power conversion capacity and its fabrication method by decreasing the leakage current between the source and the drain of a semiconductor device made of hexagonal-system silicon carbide when the gate voltage of the semiconductor device is turned off and also decreasing the electrical resistance of the semiconductor device when the gate voltage of the semiconductor device is turned on. The main current path of the field-effect transistor is formed so that the current flowing between the source and the drain of, for example, a field-effect transistor flows in the direction parallel with the {0001} plane and a channel forming plane is parallel with the {1120} plane. ?Selected Drawing!FIG.

Abstract: A self-aligned heterojunction bipolar transistor is disclosed which includes a semiconductor substrate having the (100) plane as a main surface, and at least a collector region, a base region, and an emitter region having a bandgap greater than the base region. The emitter region has an under-cut mesa structure and its crystal orientation is defined in a direction other than that parallel to the ?011! direction. In neither the ?001! direction nor the ?011! direction has the transistor any outwardly slanted structure that could cause leakage current between the emitter and base and, hence, the transistor has improved electric isolation between the emitter and base although it is self-aligned.

Abstract: A method of fabricating a compositional semiconductor device comprising a antum well wire or quantum dot superlattice structure, in particular a device selected from the group comprising lasers, photodiodes, resonant tunneling transistors, resonant tunneling diodes, far infrared detectors, far infrared emitters, high electron mobility transistors, solar cells, optical modulators, optically bistable devices and bipolar transistors, by epitaxial growth of the superlattice structure on a semiconductor substrate, is characterised in that the epitaxial growth is effected on a {311}, {211}, {111} or {110} substrate, and that the devices preferably have length and width dimensions less than 500 .ANG. and especially less than 300 .ANG..

Abstract: A method for differentially etching an N-sided polygon aperture through a first major surface of a <100> silicon wafer along the <111> planes begins with depositing a mask and defining therein a first intermediate polygon aperture having at least 4N+2 sides, where N is a positive integer. At least one side is generally parallel to the <110> plane, and the intersection of a second side and a third side of the first intermediate polygon is located generally along a major crystal axis perpendicular to the <110> plane. The included angle between the second and third sides expands during anisotropic etching to form one of the N sides of the polygon located along the major axis perpendicular to the <110> plane.

Abstract: A semiconductor device containing a polycrystalline silicon thin film wherein crystal grains of the silicon thin film have mainly a columnar structure and a crystal orientation of individual crystal grains is almost in a uniform direction can be produced by depositing a non-impurity-doped silicon thin film or an impurity layer on an interface of underlying film, followed by deposition of impurity-doped silicon thin film, if necessary, followed by heat treatment for polycrystallization.

Abstract: A semiconductor device comprises a semiconductor substrate formed by a first single crystalline semiconductor material and semiconductor layers formed on the semiconductor substrate by a second single crystalline semiconductor material doped with an element which can easily surface segregate. The surface of the semiconductor substrate is formed of a crystalline plane substantially equivalent to a facet plane which is formed on the surface of the second single crystalline semiconductor material if the second single crystalline semiconductor material is epitaxially grown with being doped with the element on a (100) plane of the first single crystalline semiconductor material.

Abstract: The semiconductor device has a semiconductor structure directly bonded onto another semiconductor structure of a different kind from the former. These two semiconductor structures are arranged in such a way that their crystal structures in a cross section perpendicular to the bonded interface of the two semiconductor structures are different from each other or that their lattice orders are not equivalent. This can be applied to direct bonding of any combination of semiconductor structures in any crystallographic orientation relation. This also allows bonding of three or more kinds of semiconductor structures.

Abstract: A compression-type semiconductor device comprises a silicon substrate in which crystal orientation between main faces opposite to each other is not larger than <1,0,0> .+-.27.5.degree.; cathode and gate electrodes formed on one of the main faces of the silicon substrate; an anode electrode formed on the other of the main faces of the silicon substrate; a cathode thermal compensation plate for the cathode and gate electrodes; and an anode thermal compensation plate for the anode electrode.

Abstract: A light-emitting semiconductor device includes a sapphire substrate whose main surface orientation is tilted by 1 to 4 degrees from its axis "a" <1120>, and layers epitaxially formed thereon. Tilting the surface orientation of the sapphire substrate enables uniform doping of a p-type impurity into the layers epitaxially grown thereon. As a result, the luminous intensity of the light-emitting semiconductor device is improved.

Abstract: The present invention provides an Si base semiconductor monocrystal substrate which includes an Si(11n) substrate where n=1.5-2.5. An intermediate layer is formed on the Si(11n) substrate. The intermediate layer is made of a material selected from the group consisting of ZnTe and Zn-rich CdZnTe, The intermediate layer has a thickness in the range of 50-200 angstroms. The intermediate layer is oriented in a (11n')B plane. An upper layer is formed on the intermediate layer. The upper layer is made of a material selected from the group consisting of CdTe and Cd-rich CdZnTe. The upper layer is oriented in a (11n")B plane. The indexes n' and n" satisfy the following equations. ##EQU1## where y is the lattice mismatch between the Si substrate and the intermediate layer. ##EQU2## where y' is the lattice mismatch between the Si substrate and the upper layer.

Abstract: A semiconductor epitaxial substrate, characterized in that a crystal is formed by epitaxial growth on a gallium arsenide single crystal substrate whose crystallographic plane azimuth is slanted from that of one of {100} planes at an angle of not more than 1.degree., that at least part of the epitaxial crystal is an In.sub.x Ga.sub.(1-x) As crystal (wherein 0<x<1), and that the epitaxial growth is carried out by chemical vapor deposition. Since the In.sub.x Ga.sub.(1-x) As layer has reduced microscopic unevenness and reduced variation in thickness, the epitaxial substrate of the present invention can be used as a channel layer of a field effect transistor or as an active layer of a semiconductor laser to endow these devices with excellent characteristics.

Abstract: A buffer layer having crystal orientation in a (111) face is formed on a semiconductor single-crystal (100) substrate and a ferroelectric thin film having crystal orientation in a (111) or (0001) face is then formed over the buffer layer. The buffer layer is preferably formed of MgO at a temperature ranging from 20 to 600.degree. C. and at a rate ranging from 0.5 to 50 .ANG./sec. The thus formed ferroelectric thin film has its axes of polarization aligned in one direction. Using the oriented ferroelectric thin-film device, highly functional nonvolatile memories, capacitors or optical modulators can be fabricated on semiconductor substrates.

Abstract: A semiconductor member with a monocrystalline semiconductor layer for forming a functional element. The main plane of the monocrystalline semiconductor layer has a center line average surface roughness Ra of not more than 0.4 nm when the main plane is washed with an aqueous ammonia-hydrogen peroxide solution in a ratio of NH.sub.4 OH:H.sub.2 O.sub.2 :H.sub.2 O of 1:1:5 by volume at a washing temperature of 85.degree. C. for a washing time of 10 minutes.

Abstract: A semiconductor device includes a substrate crystal of a type for epitaxial growth thereon. The substrate crystal has a (111)A face and a (111)B face. Also provided are at least two semiconductor regions of different conductivity types deposited by way of epitaxial growth on the (111)A face of the substrate crystal according to metal organic chemical vapor deposition, thereby providing a structure having a source and a drain. A gate side includes the (111)B face of the substrate crystal. A gate insulating layer is deposited by way of epitaxial growth on the gate side according to molecular layer epitaxy. Alternatively, the at least two semiconductor regions may be deposited on the (111)B face of the substrate crystal according to molecular layer epitaxy, and the gate insulating layer may be deposited on the (111)A face of the substrate crystal according to metal organic chemical vapor deposition.

Abstract: A semiconductor device includes a monocrystalline silicon substrate, an insulating film consisting of a monocrystalline silicon oxide formed on the surface of the monocrystalline silicon substrate, and a conductive film formed on the insulating film. The monocrystalline silicon substrate has a (100) plane orientation, the insulating film essentially consists of .beta.-cristobalite having a unit structure in a P4.sub.1 2.sub.1 2 structural expression in such a manner that every other silicon atoms of four silicon atoms aligned about a C-axis are arranged on two adjacent silicon atoms aligned in a 110! direction on an Si (100) plane, and that a plane including the C-axis of the .beta.-cristobalite and the 110! direction is set perpendicular to the (100) plane.

Abstract: A method for fabricating a semiconductor thin film is disclosed. The method includes the step of epitaxially growing a semiconductor layer made of a group II-VI compound semiconductor to have a thickness of at least one atomic layer or more, on a main plane of a single-crystal semiconductor substrate, the semiconductor substrate having one of a diamond structure and a zinc blende structure, the main plane being inclined by an angle in the range of 2 to 16 degrees with respect to a (100) plane.

Abstract: The invention is a field-emission element that is fabricated by forming an elevated surface and a base surface on a conductive substrate or a semiconductor substrate by applying a photolithographic process and an etching process, and making these surfaces cross at a step with an acute angle between the two surfaces. The intersection of the elevated surface with the step form a cathode having a radius of curvature of less than 20 nm. A gate electrode formed on the base electrode but insulated therefrom is disposed at a distance less than 1 .mu.m from said cathode by controlling the distance by the thickness of an etching protection mask. The field-emission element enables electrons to be emitted from the cathode when a voltage less than 150V is applied between the cathode and the gate electrode.

Abstract: By etching, a first groove and a second groove are formed in a silicon substrate. Surfaces of the side walls of these grooves have a surface orientation of (111). The first and second grooves sandwich a silicon thin plate therebetween, which is formed as a part of the silicon substrate. The silicon thin plate is sufficiently thin so as to act as a quantum well. Further, a pair of silicon oxide films acting as tunneling barriers are formed on the surfaces of the side walls of the silicon thin plate, thus forming a double barrier structure. In addition, a pair of polysilicon electrodes are formed and sandwich the double barrier structure. As a result, the structure of a resonance tunneling diode, which utilizes the resonance tunneling effect, is provided. Adding a third electrode to the above structure provides a hot electron transistor.

Abstract: The main surface of a semiconductor substrate, on which a field effect transistor is formed, coincides with the (nm0) lattice plane of the substrate and drain electrode thereof is oriented to flow drain current in a direction parallel to the [mn0] or [mn0] axis, wherein n and m independently represent an arbitrary integer, provided that n and m are not 0 at the same time, and that the quotient n/m (m is not zero) is not an integer. Accordingly, the plane orientation of the substrate and the direction of the drain current have a relationship such that no piezoelectric charges are induced in the channel region of the field effect transistor. Therefore, substantially no piezoelectric charges are generated even when a stress is produced in the dielectric layer formed on the substrate. Moreover, deterioration and variation in the electric characteristics due to the variation in the thickness of the dielectric layer are minimized.

Abstract: On a substrate having a surface slightly tilted by an angle .alpha. within the range of from 0.5 to 10 degrees from the (110) plane in the <00-1> direction, a superlattice structure having a periodicity in both <110> and <001> directions is formed. Various band structures are possible by selecting an appropriate constituent material and periodicity for the superlattice structure. When current flows in a direction without periodicity, a very high mobility is obtained as a result of suppressed alloy scattering. If current is caused to flow in a direction with periodicity, and the periodicity is properly selected, optical phonon scattering can also be suppressed.

Abstract: A ridge or groove is formed on a major surface of a semiconductor substrate which is formed on a first electrode and whose major surface having a ridge or groove is slanted to a <110> crystal axis direction from a {001} crystal plane. A first semiconductor layer is formed on the semiconductor substrate, then a semiconductor function layer deviating from a {111} B crystal plane is formed on the first semiconductor layer, then a second semiconductor layer is formed on the semiconductor function layer and then a second electrode is formed on the second semiconductor layer. The ridge or groove extends to the <110> crystal axis direction, and at least one of the first semiconductor layer, the semiconductor function layer and the second semiconductor layer includes phosphorus.

Abstract: A light emitting diode array has light emitting dots arranged in a line and is characterized in that a semiconductor substrate of a chip constituting the light emitting diode array has a Dovetail grooved mesa shape on a chip end face opposed to an adjacent chip and arranged in a direction perpendicular to an arranging direction of light emitting diodes. A light emitting portion can be protected from chipping even when a length from the light emitting portion of the light emitting diode array to a chip end portion is shorter than the size of a chipping portion.

Abstract: A light emitting diode including a carrier injection layer of semiconductor material, such as diamond, and a light emitting layer of electroluminescent organic material, such as PPV, positioned to form a diode junction therebetween. The semiconductor material being selected to have a wider bandgap than the organic material and the materials being further selected to minimize the discontinuities at the junction which would cause energy spikes.