Abstract: A transistor having a source/drain metal silicide in close proximity to the channel region may be formed according to the following process. A masking structure is formed upon a semiconductor substrate, and a metal is deposited self-aligned to sidewall surfaces of the masking structure. The metal is then annealed to form a metal silicide. Following formation of lightly doped drain impurity areas self-aligned to the sidewall surfaces of the masking structure, spacers may be formed adjacent the sidewall surfaces and source and drain impurity areas may be formed self-aligned to sidewall surfaces of the spacers. Fill structures are then formed adjacent the spacers and the masking structure is removed to form an opening between the spacers. A gate dielectric is formed upon the exposed upper surface of the semiconductor substrate within the opening, and a gate conductor is formed within the opening.

Abstract: Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigation performance by removing the inter-layer dielectrics and supporting the interconnection system with a rigid lining. Embodiments include depositing a dielectric sealing layer, e.g., silicon oxide, silicon nitride or composite of silicon oxide/silicon nitride, before forming the first metallization level, removing the inter-layer dielectrics after forming the last metallization level, lining the interconnection system with undoped polycrystalline silicon and forming a dielectric protective layer, e.g. a silane derived oxide, on the uppermost metallization level.

Abstract: In the manufacture of a field effect transistor which can improve the breakdown voltage between a gate and a drain and can also prevent a gate lag, an oxide film is formed or wet cleaning is carried out over the semiconductor surface of an inter-source-gate region while a nitride film is formed or dry cleaning is carried out over the semiconductor surface of an inter-gate-drain region, in order that surface traps in the semiconductor surface of the inter-gate-drain region, which is not covered with electrode metal, is greater in number than those in the semiconductor surface of the inter-source-gate region.

Abstract: An integrated circuit (IC) is provided. The IC includes a silicon substrate and a dielectric layer formed upon the silicon substrate. The IC further includes a terminal metal layer (TML) formed upon the dielectric layer. The dielectric layer and the TML form a die active area. The TML has formed therein a plurality of spaced locking structures. The plurality of space locking structures are electrically isolated therebetween. Each locking structure is formed outside the die active area. The IC further includes a passivation layer adhering to the locking structures.

Abstract: A semiconductor processing method is provided for making contact openings. It includes depositing several insulative layers and performing an anisotropic etch. One layer is a conformal oxide covering the contact area and adjacent structures. A second layer is a breadloafed oxide deposited over the contact area and adjacent structures. A third layer is a doped oxide deposited over the two lower layers. The anisotropic etch is performed through the oxide layers to the contact area located on a lower substrate. The etch is selectively more rapid in the third oxide than in the two other oxides. The breadloafed oxide provides additional protection and reduces the risk of etch-through to conductive structures adjacent the contact area. An alternate embodiment replaces the two lowest oxide layers by a breadloafed nitride layer. In this embodiment, the anisotropic etch is selectively more rapid in oxides than in nitrides.

Abstract: A modified LOCOS isolation process for semiconductor devices is disclosed. First, a shielding layer is formed overlying a semiconductor substrate. The shielding layer is then patterned to form an opening that exposes a portion of the semiconductor substrate for forming a device isolation region. Next, oxygen ions are implanted with a tilt angle into the semiconductor substrate to form a doped region extending to the area under the margin of the shielding layer. A thermal oxidation process is then performed to form a field oxide layer on the semiconductor substrate. Since the oxidation rate of the area under the margin of the shielding layer is increased by the implanted oxygen ions, the bird's beak effect shown in conventional LOCOS process can be eliminated. After that, the shielding layer is removed to complete the fabricating process of this invention.

Abstract: In a thin film transistor, a first insulating film on a silicon layer formed in an island on a substrate is smaller in thickness than the silicon layer so that the stepped island edges is gentle in slope to facilitate covering the island with a second insulating film. This reduces occurrence of gate leak considerably. Since the peripheral region of the stepped island is smaller in thickness than the central region above the channel, it is possible to minimize occurrence of gate electrode breakage. The silicon layer contains two or more inert gas atoms, and the atoms smaller in mass number (e.g., He) are contained in and near an interface with a silicon active layer while the atoms larger in mass number (e.g., Ar) than those smaller in mass number are contained in and near a second interface with a gate electrode.

Abstract: A semiconductor integrated circuit device is provided in which an interlayer insulation film deposited on a semiconductor chip includes a boron-containing silicon oxide film and a second film deposited on the boron-containing silicon oxide film. A guard ring is disposed adjacent to the periphery of the semiconductor chip, and a slit is disposed between the guard ring and the periphery of the chip. The depth of the slit is selected such that cracks formed on the boundary between the BPSG film and the second film are inhibited by the slit from intruding further along the boundary to the inside of the chip, thereby preventing moisture or obstacles from reaching the inside of the chip through the cracks.

Abstract: A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4) as the silicon (Si) source for silicon dioxide (SiO.sub.2), so as to create, in the gap, a large void whose dielectric constant is slightly greater than 1. After the formation of the void in the 0.5 microns or less gaps, the deposited nonconformal material is etched either simultaneously or sequentially along with deposition to fill the remaining gaps with void free insulation. The surface of the deposited insulating material is planarized at the desired thickness. Alternatively, a thin conformal insulating layer is first deposited as a liner on the conductive lines.

Abstract: This invention is to provide a photovoltaic element capable of improving the production yield in the manufacturing process and the reliability such as the weather resistance and the durability, while also improving the photoelectric conversion efficiency by the light enclosing effect. For attaining such object, the photovoltaic element is featured by a fact that the transparent conductive layer, positioned between the substrate and the semiconductor layers, is provided, at a face in contact with the semiconductor layers, with a fractal structure of a fractal dimension D within a range of 1.01.ltoreq.D.ltoreq.1.20 at least within a dimensional range from 40 to 400 nm.

Abstract: A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material includes formation above an intermediate process structure of a dielectric multilayer comprising a layer of amorphous planarizing material. The process also includes the partial removal of the dielectric multilayer so as to create at least one peripheral termination of the multilayer in the device edge morphological structure. Removal of the dielectric multilayer requires that the peripheral termination thereof be located in a zone of the intermediate process structure relatively higher than the level of the major surface, if compared with adjacent zones of the intermediate structure itself at least internally toward the circuit and in so far as to the device edge morphological structure.

Abstract: An insulating film having a low dielectric constant lower than that of silicon oxide is arranged between a silicon support layer and a silicon active layer. A channel region, source/drain regions, and a device isolation region are formed in the active layer. A gate electrode is arranged on the channel region through a gate insulating film. The active layer is covered with a TEOS film in which contact holes are formed. The contact holes are filled with wiring layers connected to the source/drain regions and the gate electrode.

Abstract: A method for forming an integrated circuit comprising providing a substrate comprising a node to which electrical connection is to be made; providing a layer of material outwardly of the node; and providing an electrically conductive plug through the layer of material and in electrical connection with the underlying node, the layer of material and conductive plug forming an interlocking discontinuity which effectively prevents displacement of the electrical conductive plug from the node. The present invention also contemplates an integrated circuit wherein an interlocking discontinuity comprises a projection which extends laterally outwardly relative to an electrically conductive plug, or a projection which extends laterally outwardly from a layer of material into an electrically conductive plug.

Abstract: A circuit including an active area, at least one bond pad and a corral formed on the circuit between the active area and the bond pad. A method including providing a circuit with an active area and at least one bond pad and forming a corral on the circuit between the active area and the bond pad. Embodiments of the present invention contain materials placed over the active area of a circuit preventing them from engaging areas outside the corral.

Abstract: A fuse window structure and method for forming the same for a semiconductor device with a fuse and a cutting site on the fuse, the structure having (1) a first oxide region substantially in register with the cutting site, the first oxide region having a first thickness, (2) a second oxide region substantially in register with a first land generally surrounding the cutting site, the first land generally in register with the fuse, the second region having a second thickness, and (3) a third oxide region substantially in register with a second land generally surrounding the fuse, the third region having a third thickness different than the first thickness. Different fuse window structures are formed by using etch stops with different configurations, each configuration differing with regard to coverage of the three oxide regions.

Abstract: A semiconductor device in accordance with the present invention has a passivation film. The passivation film is provided on the entire surface of a substrate provided with a bonding pad and a scribe line. After applying a photoresist on the entire surface of the passivation film, a photoresist pattern is contoured. The photoresist pattern thus contoured is exposed and developed so as to be patterned. The photoresist is patterned so as to (1) provide an opening which is a connected region of a region to be the bonding pad and a region to be the scribe line, and (2) make angles of the patterning obtuse angles. Then, the passivation film is etched, and the photoresist is removed. With this arrangement, a removing solution and a resist residue do not remain in the opening section provided on a portion of the passivation film corresponding to the bonding pad, thereby preventing a quality deterioration such as corrosion of the bonding pad and breakage of wire bonding.

Abstract: A semiconductor device has a memory cell area which contains a component having a height and a peripheral circuit area free of a component having a height. The first area includes a interlayer insulating film comprising a first interlayer film as an uppermost insulating film. The second area includes an interlayer insulating film comprising the first interlayer film and a second interlayer film disposed directly on the first interlayer film and having a chemical mechanical polishing rate greater than the first interlayer film. The interlayer insulating film in the memory cell area has a surface higher than the interlayer insulating film in the peripheral circuit area.

Abstract: A void is defined between adjacent wiring lines to minimize RC coupling. The void has a low dielectric value approaching 1.0. For one approach, hollow silicon spheres define the void. The spheres are fabricated to a known inner diameter, wall thickness and outer diameter. The spheres are rigid enough to withstand the mechanical processes occurring during semiconductor fabrication. The spheres withstand elevated temperatures up to a prescribed temperature range. At or above a desired temperature, the sphere walls disintegrate leaving the void in place. For an alternative approach, adjacent wiring lines are "T-topped" (i.e., viewed cross-sectionally). Dielectric fill is deposited in the spacing between lines. As the dielectric material accumulates on the line and substrate walls, the T-tops grow toward each other. Eventually, the T-tops meet sealing off an internal void.

Abstract: On a surface of a silicon substrate having conductivity type of p-type, a field oxide layer and a gate oxide layer to be an isolation region are formed. A gate electrode is formed via the gate oxide layer. A surface silicon oxide layer is formed on a surface of the gate electrode. An etch stop layer is formed at a region outside of the surface silicon oxide layer, which etch stop layer is formed of a material different from a material of the gate oxide layer. Also, on the upper surface of the etch stop layer, an interlayer insulation layer is formed. Then, on the surface of the silicon substrate in the vicinity of the end of the gate electrode, an n.sup.- -diffusion layer is formed. In a region outside of the n.sup.- -diffusion layer, an n.sup.+ -diffusion layer is formed. On the other hand, between the upper surface of the n.sup.- -diffusion layer and the n.sup.

Abstract: The invention relates to a semiconductor device with a substrate, with at least one isolation layer with at least one window, with a passivation layer scheme lying on the isolation layer and a metallization lying on the passivation layer scheme, the latter comprising at least two dielectric layers of which the first dielectric layer covers the isolation layer with its edges as well as the substrate in an outer edge zone of the window, and of which the second dielectric layer covers the first dielectric layer also over the edge of the isolation layer and in a portion of the outer region of the window.

Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayer.Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the is surface of the insulating layer, in order to use a portion of the multilayer wing substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.

Abstract: A semiconductor device and method having a low-permittivity material between closely-spaced leads in order to decrease unwanted capacitance, while having a more structurally strong dielectric between widely-spaced leads where capacitance is not as critical. A metal layer 14 is deposited on a substrate 12 of a semiconductor wafer 10, where the metal layer 14 has a first region 15 and a second region 17. An insulating layer 39 is deposited on the metal layer, and the insulating layer 39 is patterned with a conductor pattern of widely-spaced leads and closely-spaced leads. Widely-spaced leads 16 are formed in the first region 15 of the metal layer 14. At least adjacent portions of closely-spaced leads 18 are formed in the second region 17 of the metal layer 14. A low-permittivity material 34 is deposited between adjacent portions of the closely-spaced leads 18. A structural dielectric layer 26 is deposited between at least the widely-spaced leads.

Abstract: A method and structure for improving the thermal conductivity and therefore the heat dissipation of densely interconnected semiconductor circuits, particularly those utilizing low dielectric constant materials by placing a layer of highly thermally conductive material such as diamond film 26 between layers of interconnect metal 22. An embodiment of the present invention allows increased thermal conductivity from the upper levels of metalization to the substrate 10 where structure of the present invention is repeated to form multiple levels of interconnects stacked one upon the other. Further, the diamond layer of the present invention may be used as an effective etch stop or planarization stop. The present invention can be used with known low dielectric constant materials, interlevel dielectrics 30 and planarization techniques with the added benefit of highly thermally conductive diamond film.

Abstract: Power semiconductor devices having overlapping floating field plates include a primary field plate and a plurality of floating field plates which are formed on an electrically insulating region and capacitively coupled together in series between an active region of a power semiconductor device and a floating field ring. Preferably, the capacitive coupling is achieved by overlapping at least portions of the floating field plates. According to one embodiment, a power semiconductor device comprises a semiconductor substrate having a first region of first conductivity type therein extending to a face thereof and a second region of second conductivity type in the first region of first conductivity type and forming a P-N junction therewith.

Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wiring bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayered substrate. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, in order to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.

Abstract: A method for fabricating a semiconductor memory device includes the steps of forming, in a semiconductor substrate of a first conductivity type, a well of a second opposite conductivity type by protecting the substrate surface except for a part where the well of the second conductivity type is to be formed, oxidizing the exposed surface of the semiconductor substrate while using the same mask pattern to form a thick oxide film on the surface of the well, and removing the thick oxide film by an etching process to form a recessed surface on the well.

Abstract: Pin-holes or thin sections in the implanted dielectric layer of a SIMOX device are patched by forming a reverse biasable PN junction within the depth range of or proximate to the dielectric layer. A charge depletion zone forms about the PN junction when the Latter is reverse-biased and reinforces or patches weak spots in the implanted dielectric layer such as pin-holes and thin-sections.

Abstract: A multi-state memory cell for a mask ROM device. Source/drain regions are arranged on a substrate as strips extending along a first direction on the plane of the substrate and bit lines. Gate oxide layers are arranged on the substrate as strips extending along a second direction. Gate electrodes are each formed on top of each of the gate oxide layers as strips extending along the second direction. The gate oxide layers have a number of selected thickness' arranged in a differential series. Each of the transistor channel regions, together with their corresponding one of the neighboring source/drain pair, the gate oxide layer on top, and the gate electrodes further on top thereof constitute one of the memory cells that can have its threshold voltage varied among the differential series of thicknesses allowing for the storage of a multi-bit equivalent of memory content for the memory cell.

Abstract: A method of forming a native oxide from an aluminum-bearing Group III-V semiconductor material is provided. The method entails exposing the aluminum-bearing Group III-V semiconductor material to a water-containing environment and a temperature of at least about 375.degree. C. to convert at least a portion of said aluminum-bearing material to a native oxide characterized in that the thickness of said native oxide is substantially the same as or less than the thickness of that portion of said aluminum-bearing Group III-V semiconductor material thus converted. The native oxide thus formed has particular utility in electrical and optoelectrical devices, such as lasers.

Abstract: This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying and gelling one or more solutions between and over conductors 24 and drying the wet gel to create at least porous dielectric sublayers 28 and 29. By varying the composition of the solutions, gelling conditions, drying temperature, composition of the solvents in the wet gel, or a combination of these approaches, the porosity of the sublayers may be tailored individually. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract: A semiconductor device has a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type contacted by respective first and second electrodes. A semi-insulating layer extends between the first and second electrodes and there is a first insulating layer between the semi-insulating layer and the first semiconductor region. The sheet resistivity of the semi-insulating layer varies, and this improves the high breakdown voltage of the p-n junction of the semiconductor device between the first and second semiconductor layers, by acting as a shield for charges included on a passivation insulation layer covering the semi-insulating layer and the first and second electrodes. Third semiconductor regions, with corresponding third electrodes, extend around, and are spaced from, the second semiconductor region.

Abstract: This invention provides an improved porous structure for semiconductor devices and a process for making the same. This process may be applied to an existing porous structure 28, which may be deposited, for sample, between patterned conductors 24. The process may include baking the structure in a reducing atmosphere, preferably a forming gas, to dehydroxylate the pore surfaces. The process may include baking the structure in a halogen-containing atmosphere to bond halogens to the pore surfaces. It has been found that a porous structure treated in such a manner generally exhibits improved dielectric properties relative to an untreated sample.

Abstract: A semiconductor device with an improved contact capable of improving junction breakdown voltage and junction leakage current by forming a contact at an active region without damaging bird' beak portions of its element-isolation oxide films and a method of making this semiconductor device. The semiconductor device comprises element-isolation oxide films formed on a semiconductor substrate, an etch barrier material film formed on bird's beak portions of element-isolation oxide films, an insulating film formed over the element-isolation oxide films and the etch barrier material layer, and a conductive material layer formed over the insulating film and in contact with the active region. In order to prevent the bird's beak portions of element-isolation oxide films from being damaged upon the formation of contact hole, the etch barrier material film has an etch selectivity different from that of a silicon oxide film formed on the active region.

Abstract: Disclosed herein is a semiconductor device having a multilayer interconnection structure, which is provided with a plurality of via holes having constant diameters. Patterns of a first interconnection layer are provided on a semiconductor substrate. An interlayer insulating film is provided over the semiconductor substrate, to cover the patterns of the first interconnection layer. A silicon ladder resin film is applied onto the surface of the interlayer insulating film, to flatten the same. First and second via holes are provided through the silicon ladder resin film and the interlayer insulating film, to expose first and second coupling portions provided on the surfaces of the patterns of the first interconnection layer. A second interconnection layer is provided over the semiconductor substrate, to be connected with the first and second coupling portions through the first and second via holes respectively.

Abstract: A tunnel insulating film is formed on a main surface of a silicon substrate. A floating gate electrode is formed on the tunnel insulating film. A nitride layer formed of a material of the floating gate electrode is formed in the vicinity of an interface between the floating gate electrode and the tunnel insulating film located in a tunnel region A. Therefore, the write/erase characteristics of a non-volatile semiconductor memory device can be improved without decreasing the driving capability of a memory transistor at lower voltages.

Abstract: An improved EEPROM cell structure is disclosed which provides protection against external detection of data stored within the cell. One or more cavities filled with a high etching film and extending in a substantially vertical direction are provided in a region adjacent to an end of the floating gate such that during an attempted deprocessing of the cell using an etching process, the etchant will rapidly diffuse through these cavities and expose the floating gate via these cavities before exposing and removing the control gate via the insulating layers overlapping the control gate. Any charge once present on the floating gate will dissipate before the control gate can be removed, thereby making it impossible to read data stored within the cell.

Abstract: An electronic circuit package having a wiring substrate, at least two semiconductor chips and a bus line. All the semiconductor chips to be connected by means of the bus line are bare chip packaged on a wiring substrate, and the semiconductor chips and the wiring substrate are connected by wire bonding between wire bonding pads formed on the semiconductor chips and the wiring substrate. The wiring substrate may be a multilayer element. Preferably, there is an insulating layer partially formed on the surface of the multilayer wiring substrate and a die bonding ground formed on the surface of the insulating layer, thereby making it possible to use a portion of the multilayer wiring substrate under the die bonding ground as a wiring or a via hole region, and at least one of the semiconductor chips is formed on the die bonding ground.

Abstract: A new planarized device isolation structure within a semiconductor substrate is described. The device isolation structure comprises narrow device isolation regions each consisting of a deep trench having a thin oxide covering its sidewalls and bottom and filled with silicon oxide, wide device isolation regions each consisting of two deep trenches flanking a shallow trench wherein each deep trench has a thin oxide covering its sidewalls and bottom and is filled with silicon oxide and wherein the shallow trench is filled with a field oxide. The top surface of the narrow and wide device isolation regions and the semiconductor substrate is planarized.

Abstract: Apparatus for improving ON/OFF switching in high speed digital circuitry is disclosed. The present invention includes apparatus for altering the impedance or capacitive loading of the interconnect. Some embodiments reduce back reflections by raising the impedance of the interconnect to be closer to that of the contact, or raising the capacitive loading, and others improve the culprit-victim problem by filtering out the highest frequency components of the pulse on the culprit interconnect. For the back reflection problem, the apparatus for altering can be formed of elements for altering the capacitance or, alternatively the resistance, of the interconnect. For the culprit-victim problem, the apparatus for altering includes elements which alter the effective capacitance or resistance of the culprit interconnect.

Abstract: An integrated circuit wafer composed of a substrate having a surface carrying a plurality of circuit chips spaced from one another by scribe lines constituted by regions of the substrate surface along which the substrate will be cut in order to separate the chips from one another, each chip having at least one semiconductor element composed of a plurality of patterned layers of electrically conductive material and the wafer further including at least one interlayer insulation film having portions which extend across each chip and interposed between two of the layers of electrically conductive material to form a component part of each element, the interlayer insulation film further having portions which extend across the scribe lines at the time the substrate is cut along the scribe lines and which are contiguous with portions of the interlayer insulation film that extend across each chip, wherein the wafer is provided with one or more defined patterns located at at least one scribe line region and a passivati

Abstract: The electrical operating characteristics of a microwave circuit are modified by providing a dielectric layer on the circuit in a pattern which modifies the electrical characteristics of an overlay responsive portion of the circuit in a manner which results in the overall circuit having a desired electrical operating characteristic within a tolerance. Adjustment of the operating characteristics may be done in an iterative manner of measuring the characteristics, modifying the distribution of dielectric material and remeasuring the operating characteristics until satisfactory operating characteristics are obtained.

Abstract: A method for forming contact vias in a integrated circuit which do not have planarizing material nearby. After a first insulating layer is deposited over the integrated circuit, a planarizing layer is deposited over the first insulating layer. The planarizing layer is etched back and portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the integrated circuit. A first masking layer is then formed over the surface of the integrated circuit. The openings created in the first masking layer have a size which is greater than the size of the contact vias to be formed. The first insulating layer is partially etched into so that portions of the planarizing layer near the locations of the contact vias are removed. The first masking layer is then removed, and a second insulating layer is deposited over the integrated circuit.

Abstract: A tamper resistant structure has a pattern which covers portions of an IC but exposes other portions of the IC so that etching away the tamper resistant structure destroys the exposed portions. The IC can not be easily disassembled and reverse engineered because the tamper resistant structure hides active circuitry and removing the tamper resistant structure destroys active circuitry. One embodiment of the tamper resistant structure includes a metal layer and a cap layer. The cap layer typically includes material that is difficult to remove, such as silicon carbide, silicon nitride, or aluminum nitride. The metal layer typically includes a chemically resistant material such as gold or platinum. A bonding layer of nickel-vanadium alloy, titanium-tungsten alloy, chromium, or molybdenum, may be used to provide stronger bonds between layers. Some embodiments provide an anti-corrosion seals for bonding pads in addition to the tamper residant structure.

Abstract: A semiconductor device having a superior step coverage of a layer formed inside or near a contact-hole is provided. An intermediate conductive layer is formed through an insulating layer on a lower conductive layer on a semiconductor substrate, and first, second and third inter-layer insulating layers are formed on the intermediate conductive layer. The third inter-layer insulating layer is selectively removed by an isotropic wet etching method thereby to form a through-hole extended to the second inter-layer insulating layer and having a large opening area. In performing this, the second inter-layer insulating layer acts to restrict the removal of the third inter-layer insulating layer in the thickness direction. Next, the first and second inter-layer insulating layers are selectively removed by an anisotropic dry etching method thereby to form a through-hole having a small opening area. The through-hole having a large opening area and the through-hole having a small opening area form a contact-hole.

Abstract: A non-volatile semiconductor memory providing a semiconductor substrate including source and drain diffusion regions and a gate electrode, and an insulating film which is at least provided on the semiconductor substrate just below the gate electrode and has a smaller dielectric breakdown strength on the source side than on the drain side, wherein the insulating film is comprised of a laminated film having a multilayer structure on the drain side and a single-layer film or multilayer film which is broken down at a smaller voltage on the source side than on the drain side, and a predetermined voltage is applied to break down the single-layer film or multilayer film on the source side, so that data can electrically be written only once.

Abstract: A contact structure is formed atop a semiconductor wafer at a level whereat it is desired to terminate polishing of a layer overlying the contact structure. When the contact structure becomes exposed to a polishing slurry, an electrical characteristic, such as resistance or impedance, is registered by measuring apparatus. In one embodiment, two or more contact structures are formed atop the wafer, vias are formed through the wafer, and the vias are filled, thereby providing a conductive path from the contact structures to the back side of the wafer. The measuring apparatus probes the filled vias on the back side of the wafer. A change in resistance/impedance indicates that the contact structures have become exposed during polishing, and polishing is terminated. In another embodiment of the invention, one or more contact structures are formed atop the wafer. The measuring apparatus is connected to a probe in the polishing slurry, and to the wafer itself, such as to the back side of the wafer.

Abstract: An integrated circuit comprises a semiconductor substrate, a plurality of islands formed at a principal surface of the substrate and isolated from one another by a PN junction, an interlayer insulating film formed to substantially cover the principal surface of the substrate, and a capacitor formed in a selected one of the islands and having a dielectric layer which is formed within an opening formed in the interlayer insulating film above the selected island. The dielectric layer is constituted of a multilayer film including a silicon oxide film and a silicon nitride film extending to cover the interlayer insulating film. A power supply line conductor is formed on the interlayer insulating film, and the silicon nitride film is completely removed from a portion of the interlayer insulating film directly under the power supply line conductor.

Abstract: A gate insulating layer, which is formed on a channel region of a semiconductor substrate and interposed between the semiconductor substrate and a gate electrode, consists of a first part and a second part adjoining each other. The first part includes an oxide lower layer and a nitride upper layer, and a second part includes a nitride lower layer and an oxide upper layer.

Abstract: A method for forming a planar insulating layer over the surface of a semiconductor workpiece 8 which includes at least one low region 13 is discussed herein. The first step is to form a layer of blocking material 14 on the surface of the workpiece 8. A first material region 20 is then formed in the low region 13 and an insulating layer 21 is formed over the surface of the workpiece 8 including the first material region 20. The workpiece 8 is then heated in the presence of an active ambient such that the insulation layer 21 reflows and also so that the first material 20 region reacts with the active ambient to create an internal stress in said insulation layer 21. Other systems and methods are also disclosed.

Abstract: A dynamic random access memory comprises a memory cell region and a sense amplifier region defined on a substrate, a plurality of memory cell capacitors provided on the memory cell region in correspondence to memory cell transistors, a first insulation layer provided on the semiconductor substrate to cover both the memory cell region and the sense amplifier region, a first conductor pattern provided on the first insulation layer, an intermediate connection pattern provided on the first insulation layer in correspondence to the sense amplifier region, a spin-on-glass layer provided on the first insulation layer to extend over both the memory cell region and the sense amplifier region, and a projection part provided on the substrate of the sense amplifier region in correspondence to the intermediate connection pattern under the first insulation layer for lifting the level of the surface of the first insulation layer such that the intermediate interconnection pattern is exposed above the upper major surface of t