Abstract: Novel semiconductor devices containing a discontinuous cap layer and possessing a relatively low dielectric constant are provide herein. The novel semiconductor devices includes at least a substrate, a first dielectric layer applied on at least a portion of the substrate, a first set of openings formed through the dielectric layer to expose the surface of the substrate so that a conductive material deposited within and filling the openings provides a first set of electrical contact conductive elements and a discontinuous layer of cap material covering at least the top of the conductive elements to provide a first set of discontinuous cap elements. Methods for forming the semiconductor devices are also provided.

Abstract: Disclosed is a MOS semiconductor device, which comprises a semiconductor substrate; a gate insulating film formed on the semiconductor substrate, the gate insulating film containing nitrogen; a gate electrode selectively formed on the gate insulating film; and an oxide film formed on a surface of the gate electrode and the semiconductor substrate, wherein a thickness of a first portion of the gate insulating film which overlaps vertically the gate electrode is one third or less that of a second portion of the gate insulating film disposed at a corner portion of the gate electrode. According to such constitution of the MOS transistor device of the present invention, by allowing the gate insulating film to contain nitrogen, an increase in a thickness of the gate insulating film toward the semiconductor substrate than required can be suppressed, and hence lowering of a gate voltage can be prevented, resulting in preventing a controllability deterioration of the MOS transistor device.

Abstract: The present invention has provided on a back channel side of the TFT a blocking layer that is formed by laminating a 50 nm to 100 nm thick silicon oxynitride film (A) and a 30 nm to 70 nm thick silicon oxynitride film (B). By forming a lamination structure of such silicon oxynitride films, not only can be the contaminations caused by impurities such as alkali metallic elements from the substrate prevented, but the fluctuations in the electrical characteristics of the TFT can be reduced.

Abstract: A method for manufacturing integrated circuits (“IC”) on wafers to manage crack damage in the ICs such that crack propagation into the IC active array is reduced or eliminated. The method provides for a defined separation or divide of the IC gate conductor from the IC crack stop or IC edge. The method is especially useful in managing crack damage induced through the delamination of one or more of the gate conductor surface interfaces as a result of the IC wafer dicing process. Circuits or chips manufactured according to the methods disclosed are also taught.

Abstract: A process for fabricating a device including the step of forming a structure for facilitating the passivation of surface states is disclosed. The structure comprises an oxynitride layer formed as part of the device structure. The oxynitride facilitates the passivation of surface states when heated.

Abstract: In a semiconductor device including a laminate of a first insulating layer, a crystalline semiconductor layer, and a second insulating layer, characteristics of the device are improved by determining its structure in view of stress balance. In the semiconductor device including an active layer of the crystalline semiconductor layer having tensile stress on a substrate, tensile stress is given to the first insulating layer formed to be in close contact with a surface of the semiconductor layer at a substrate side, and compressive stress is given to the second insulating layer formed to be in close contact with a surface of the semiconductor layer at a side opposite to the substrate side.

Abstract: Cu diffusion between Cu and Cu alloy interconnect members, e.g., lines, in a silicon oxide inter-layer dielectric is avoided or substantially reduced by converting an upper portion of the silicon oxide inter-layer dielectric between neighboring lines to silicon oxynitride and then depositing a capping layer. Embodiments include filling damascene trenches in a silicon oxide inter-layer dielectric with Cu or a Cu alloy, CMP to effect planarization such that the upper surfaces of the lines are substantially coplanar with the upper surface of the inter-layer dielectric and treating the exposed surfaces with a high strength ammonia plasma to ion bombard the exposed inter line silicon oxide with nitrogen atoms, thereby converting the upper portion to silicon oxynitride, while simultaneously removing or substantially reducing surface oxides on the lines. A silicon nitride capping layer is then deposited.

Abstract: A semiconductor device comprising a thin film transistor, and a process for fabricating the same, the process comprising: a first step of forming an island-like semiconductor layer, a gate insulating film covering the semiconductor layer, and a gate electrode comprising a material containing aluminum as the principal component formed on the gate insulating film; a second step of introducing impurities into the semiconductor layer in a self-aligned manner by using the gate electrode as the mask; a third step of forming an interlayer dielectric to cover the gate electrode, and forming a contact hole in at least one of source and drain; a fourth step of forming over the entire surface, a film containing aluminum as the principal component, and then forming an anodic oxide film by anodically oxidizing the film containing aluminum as the principal component; a fifth step of etching the film containing aluminum as the principal component and the anodic oxide film, thereby forming a second layer interconnection cont

Abstract: A method of fabricating an integrated circuit having reduced threshold voltage shift is provided. A nonconducting region is formed on the semiconductor substrate and active regions are formed on the semiconductor substrate. The active regions are separated by the nonconducting region. A barrier layer and a dielectric layer are deposited over the nonconducting region and over the active regions. Heat is applied to the integrated circuit causing the barrier layer to anneal.

Abstract: A barrier film of a SiON film is formed below an interlayer insulating film which is a single layer film or laminated film of an TEOS film or SOG film covering a floating gate 4 and control gate 6. The SiON film which is good in moisture blocking but poor in coverage is covered with another TEOS film which is better in coverage than the SiON film, thereby improving the barrier property of the barrier film. Such a configuration prevents moisture or H atoms contained in the TEOS film or SOG film from being diffused and trapped by the tunneling oxide film 3, thereby improving the trap-up rate and hence endurance characteristic and extending the operation life of a memory cell.

Abstract: Lateral bipolar transistor, in which a thin diffusion barrier (4) is applied to a base region (10) between an emitter region (9) and a collector region (11), and there is present, on said barrier, a base electrode (8) which is provided for low-resistance supply, is connected to a heavily doped base terminal region and consists of polysilicon, for example, into which dopant is diffused out from said base terminal region.

Abstract: A structure and method for forming a high dielectric constant device structure includes a monocrystalline semiconductor substrate and an insulating layer formed of a metal oxide-nitride such as MnOm−xNx, wherein M is a metallic or semi-metallic element or combination of metallic and/or semi-metallic elements and m and n are integers. Semiconductor devices formed in accordance with the present invention exhibit low leakage current density and improved chemical, thermal, and electrical stability over conventional metal oxides.

Abstract: In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer.

Abstract: The invention provides a semiconductor device with a passivation film provided on a surface thereof, said passivation film comprising a SiON layer in contact with the surface of said semiconductor device, and a Si3N4 layer provided at the outer side of said SiON layer, chraracterized in that said passivation film has an outermost layer of Si3N4 and said outermost layer has a portion in contact with said semiconductor device or the exposed area of said SiON layer is nitrided. The semiconductor device has a high bonding strength between the passivation film and the semiconductor device and high moisture resistance.

Abstract: An improved photolithography technique is provided whereby the beneficial effects of using an anti-reflective coating may be realized while maintaining critical dimensions in each subsequent step. This improvement is realized by the treatment of the anti-reflective coating with a gaseous plasma or a solution of sulfuric acid and hydrogen peroxide. By treating the anti-reflective coating with gaseous plasma or solution of sulfuric acid and hydrogen peroxide, no “footing” results and the critical dimensions as set by the photoresist mask are preserved to provide an accurately patterned mask for subsequent steps.

Abstract: A method of fabricating a CVD low-k SiOCN material. The first embodiment comprising the following steps. MeSiH3, N2O, and N2 are reacted at a molar ratio of from about 1:5:10 to 1:10:15, at a plasma power from about 0 to 400 W to deposit a final deposited film. The final deposited film is treated to stabilize the final deposited film to form a CVD low-k SiOCN material. The second embodiment comprising the following steps. A starting mixture of MeSiH3, SiH4, N2O, and N2 is reacted at a molar ratio of from about 1:1:5:10 to 1:5:10:15, in a plasma in a helium carrier gas at a plasma power from about 0 to 400 W to deposit a CVD low-k SiOCN material.

Abstract: A GaN substrate formed with a substrate, a first GaN layer, a first preventing film, a second GaN layer, and a second preventing film. The first GaN layer is formed on the substrate, and includes a plurality of stripe portions which form at least one first groove between adjacent ones of the plurality of stripe portions. The second GaN layer is formed over the substrate and the first GaN layer. The first preventing film is arranged on upper surfaces of the plurality of stripe portions, and prevents crystal growth of a GaN layer in a vertical up direction from the upper surfaces of the plurality of stripe portions. The second preventing film is arranged on at least one bottom surface of the at least one first groove, and prevents crystal growth of a GaN layer in a vertical up direction from the at least one bottom surface.

Abstract: An integrated circuit structure (8) includes a plurality of solid state electronic devices and a plurality of conductive elements (12, 14) that electrically couple the electronic devices. The integrated circuit structure (8) also includes a dielectric layer (16) positioned between two or more of the conductive elements (12, 14). A liner (18) is positioned between at least a portion of the dielectric layer (16) and a conductive element (12, 14). The liner (18) is formed from a compound that includes silicon and either carbon and nitrogen.

Abstract: An SiN film is formed by applying a thermal nitridation process to a surface of a Si substrate to form a first SiN film and then forming a second SiN film on the first SIN film by conducting a CVD process that uses SiCl4 and an ammoniac gas, wherein the CVD process is conducted at a temperature in the range of 550-660° C.

Abstract: In a semiconductor chip with a planar structure, the width of each corner portion of a peripheral electrode in a diagonal direction of the chip is made almost the same as the width of each straight portion of the peripheral electrode, the peripheral electrode having the same potential as a drain electrode in the periphery of the chip. The corner portion of the peripheral electrode is in the form of a partial annular ring. Degradation of the withstand voltage in the semiconductor device is prevented in the high-temperature and high-humidity conditions.

Abstract: An electrode pad for a Group III nitride compound semiconductor having p-type conduction includes a triple layer structure having first, second, and third metal layers, formed on an electrode layer. A protection film with a window exposing a central portion of the third metal layer is formed by etching on the third metal layer and covers the sides of the first, second, and third metal layers. The second metal layer is made of gold (Au). The first metal layer is made of an element which has ionization potential lower than gold (Au). The third metal is made of an element which has adhesiveness to the protection film stronger than that of gold (Au). Consequently, this structure of the electrode pad improves the adhesive strength between the protection layer and the third meal layer and prevents the etching of the sides of the protection film. Furthermore, the contact resistance between the semiconductor and the electrode pad is lowered and, thus, ohmic characteristic of the electrode pad is improved.

Abstract: A method of forming a composite silicon oxide layer over a semiconductor device. The composite silicon oxide layer is formed between the semiconductor device and a doped silicate glass layer. The composite silicon oxide layer comprises two silicon oxide layers, each having a different silicon/oxide composition. The oxygen-rich oxide layer or silicon dioxide layer is formed directly above the semiconductor device, and the silicon-rich oxide layer is formed above the silicon dioxide layer next to the doped silicate glass layer. Both the silicon dioxide layer and the silicon-rich oxide layer are formed in the same plasma deposition chamber.

Abstract: A flash memory structure and fabrication process whereby stacks of a first poly-crystalline or of an amorphous silicon material (polysilicon), having a bottom layer member of an interpoly dielectric stack, are processed for formation of a post-treatment layer over the bottom interpoly dielectric layer member. The post-treatment layer is essentially a solid material formed by a chemical reaction for purposes of improving the reliability of an interpoly dielectric stack and results in changes to the capacitor coupling ratio of the flash memory element and allows the use of new power supply and programming voltages. The post-treatment layer is formed by exposing the polysilicon stacks with the bottom interpoly dielectric layer member to a selected one of at least three ambient reagent gases. The selected ambient reagent gases and exposure of the semiconductor structure being performed in either a batch furnace, a single wafer rapid thermal anneal tool, or a plasma chamber.

Abstract: In one aspect, the current invention provides a method for reducing the source leakage of a semiconductor device. The method comprises the steps of stacked gate etch, thin oxide formation, SAS etch, spacer formation and source implant on the semiconductor substrate. In a second aspect, the current invention provides another method for reducing the source leakage of a semiconductor device. The method comprises the steps of stacked gate etch, first oxide layer formation, first source implant, annealing, SAS etch, second oxide layer formation, spacer formation, and second source implant. In yet another aspect, the current invention provides a novel semiconductor device. The semiconductor device is comprised of a stacked gate provided on a portion of a semiconductor substrate, a first oxide layer appended to the stacked gate, a second oxide layer formed on the first oxide layer and a spacer formed on the second oxide layer.

Abstract: In one aspect, the invention includes a semiconductor processing method, comprising: a) providing a silicon nitride material having a surface; b) forming a barrier layer over the surface of the material, the barrier layer comprising silicon and nitrogen; and c) forming a photoresist over and against the barrier layer.

Abstract: A semiconductor device and method of forming a patterned conductive layer on a semiconductor substrate are provided so as to prevent fluorine substance outflow from a fluorinated silicate glass (FSG) layer thereon and simultaneously so as to suppress back reflection of light waves into a photoresist layer during photolithographic processing. The substrate is coated in turn with a conductive layer, a dielectric (e.g., silicon dioxide) liner, a FSG layer, a silicon oxynitride layer preventing fluorine substance outflow therethrough from the FSG layer and also forming an antireflective coating (ARC), and a photoresist layer. The photoresist layer is exposed and developed to uncover pattern portions of the underlying silicon oxynitride layer. The uncovered pattern portions of the silicon oxynitride ARC layer and corresponding underlying portions of the FSG layer and dielectric liner are then removed, e.g., by a single dry etching step, to expose pattern portions of the conductive layer for metallization.

Abstract: A semiconductor component with passivation includes at least two double passivating layers, of which an uppermost is applied to a planar surface of a layer located therebelow. The double passivating layers include two layers of different dielectric materials, for example silicon oxide and silicon nitride. The respective thicknesses of the individual passivating layers can be adapted to dimensions of the structuring of the layer to which the passivation is applied. This produces a reliable passivation which is particularly suitable for capacitively measuring fingerprint sensors.

Abstract: The present invention provides a MOS structure and fabrication process for fabricating the substrate structure whereby a thin layer of silicon oxynitride, acting as a reaction barrier layer, and a tantalum pentoxide layer are formed in the gate region for controlling induction of electric charge in the gate region and thereby control the flow of current through the device. The high dielectric characteristic of the tantalum pentoxide facilitates blocking the flow of current in accordance with the applied voltage, and which in an off-state of the device, minimizes the gate leakage current. The silicon oxynitride barrier is formed by using a pre-deposition process of annealing the silicon substrate surface in a nitric oxide (NO) environment. The anneal may be a rapid thermal anneal (RTA) process for 10 seconds to 5 minutes at 400° C. to 1000° C. in the nitric oxide NO ambient. The annealing process produces the thin silicon oxynitride layer needed for depositing the tantalum pentoxide layer.

Abstract: An ultra-large-scale integrated (ULSI) circuit includes MOSFETs which have different threshold voltages and yet have the same channel characteristics. The MOSFETs include gate structures with a polysilicon material. The polysilicon material is implanted with lower concentrations of germanium where lower threshold voltage MOSFETs are required. Over a range of 0-60% concentration of germanium, the threshold voltage can be varied by roughly 240 mV.

Abstract: A semiconductor device is formed with a silicon oxynitride gate insulating film to exhibit high TDDB characteristics. The silicon oxynitride film is formed on a silicon substrate and does not include an SiNO2 chemical bond unit at any portion in the film thickness direction.

Abstract: The adhesion of a silicon carbide containing film to a surface is enhanced by employing a transition film of silicon nitride, silicon dioxide and/or silicon oxynitride.

Abstract: This invention includes a novel synthesis of a three-step process of growing, depositing and growing Si02 under low pressure, e.g., 0.2-10 Torr, to generate high quality, robust and reliable gate oxides for sub 0.5 micron technologies. The first layer, 1.0-3.0 nm is thermally grown for passivation of the Si-semiconductor surface. The second deposited layer 1.0-5.0 nm forms an interface with the first grown layer. During the third step of the synthesis densification of the deposited oxide layers occurs with a simultaneous removal of the interface traps at the interface and growth of a stress-modulated Si02 occurs at the Si/first grown layer interface in the presence of a stress-accommodating interface layer resulting in a planar and stress-reduced Si/SiO2 interface. The entire synthesis is done under low-pressure (e.g., 0.2-10 Torr) for slowing down the oxidation kinetics to achieve ultrathin sublayers and may be done in a single low-pressure furnace by clustering all three steps.

Abstract: A resin material having a small relative dielectric constant is used as a layer insulation film 114. The resin material has a flat surface. A black matrix or masking film for thin film transistors is formed thereon using a metal material. Such a configuration prevents the problem of a capacity generated between the masking film and a thin film transistor.

Abstract: A fabrication method for a semiconductor memory device having an isolation structure which includes the steps of forming a pad oxide film on a semiconductor substrate, forming a first nitride film on the pad oxide film, patterning the first nitride film and the pad oxide film, forming an oxynitride film on a portion of the substrate externally exposed by the patterning step, forming side walls of a second nitride film on sides of the first nitride film, removing a portion of the oxynitride film using the side walls as a mask, forming a field oxide film on an exposed portion of the substrate, and removing the remaining pad oxide film, first nitride film, second nitride film, and oxynitride film. The first nitrate film and the pad oxide film may be patterned such that the pad oxide film is undercut to expose more of the substrate and to allow formation of the oxynitride film under the first nitride film. As such, the first nitride film can be used as a mask, rendering unnecessary the formation of side walls.

Abstract: A method and system for providing a semiconductor device is disclosed. The method and system include depositing an antireflective coating (ARC) layer having antireflective properties. The method and system also include depositing a capping layer on the ARC layer. The capping layer reduces a susceptibility of the ARC layer to removal while allowing the ARC layer to substantially retain the antireflective properties.

Abstract: A 1200 dpi LED may be manufactured without highly accurate mask alignment and provide good light radiation efficiency. A first interlayer dielectric is formed on a semiconductor substrate and has a plurality of first windows formed therein and aligned in a row. A diffusion region is formed in the semiconductor substrate through each of the first windows. An electrode is formed to have an area in contact with the corresponding diffusion region. Another electrode is formed on the other side of the substrate. A second interlayer dielectric is formed on the first interlayer dielectric such that the second interlayer dielectric does not overlap the area of the electrode and does not extend to a first perimeter of the area.

Abstract: A microelectronic structure including adjacent material layers susceptible of adverse interaction in contact with one another, and a barrier layer interposed between said adjacent material layers, wherein said barrier layer comprises a binary, ternary or higher order metal nitride-carbide material, whose metal constituents are different from one another and include at least one metal selected from the group consisting of transition metals Ti, V, Cr, Zr, Nb, Mo, Hf, Ta, W, Sc and Y, and optionally further including Al and/or Si. The barrier layer is stoichiometrically constituted to be amorphous or nanocrystalline in character, and may be readily formed by techniques such as chemical vapor deposition, sputtering, and plasma-assisted deposition, to provide a diffusional barrier of appropriate resistivity character for structures such as DRAMs or non-volatile ferroelectric memory cells.

Abstract: A method of forming interconnections is provided. A defined metal layer is formed as a metal line on a provided substrate. An oxide layer is formed on the metal layer and on the substrate. A silicon nitride layer is formed on the oxide layer. The oxide layer and the silicon nitride layer constitute a seed layer. A via hole is formed in the silicon nitride layer to expose the oxide layer positioned over the metal layer. A dielectric layer is formed on the seed layer. Since the silicon nitride layer and the oxide layer are different, a part of the dielectric layer positioned on the silicon nitride layer is a silicon oxide layer having holes therein. The other dielectric layer positioned on the oxide layer within the via hole is a dense silicon oxide layer.

Abstract: In a laser beam make-link programmable semiconductor device, a pair of conductor strips are formed in the same level plane on a lower level insulator film formed on a semiconductor substrate, and are separated from each other in such a manner that opposing ends of the pair of conductor strips are separated by a predetermined distance smaller than a film thickness of the upper level insulator film. An upper level insulator film substantially transparent to a laser beam, is formed on the conductor strips. With this arrangement, even if a trimming laser beam has a small energy, the laser beam permeates through the upper level insulator film to reach and melt the opposing ends of the pair of conductor strips, with the result that the opposing ends of the pair of conductor strips are short-circuited.

Abstract: A self-aligned structure and method of etching contact holes in the self-aligned structure are described. The dielectric materials, etching methods, and etchants are chosen to provide high selectivity etching. The structure comprises an electrode with a silicon oxy-nitride cap and silicon oxy-nitride spacers on the sidewalls of the electrode and the cap. An etch stop layer of silicon nitride is deposited over the substrate covering the spacers and cap. A layer of silicon oxide is deposited over the etch stop layer. Etching methods and etchants are used which provide a ratio of the etching rate of silicon oxide to the etching rate of silicon nitride or silicon oxy-nitride of at least eight and a ratio of the etching rate of silicon nitride to the etching rate of silicon oxy-nitride of at least two.

Abstract: A resin material having a small relative dielectric constant is used as a layer insulation film 114. The resin material has a flat surface. A black matrix or masking film for thin film transistors is formed thereon using a metal material. Such a configuration prevents the problem of a capacity generated between the masking film and a thin film transistor.

Abstract: The present invention is described in several embodiments depicting structures and methods to form these structures. A first embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal nitride film bonded to the metal film; and the silicon dioxide film bonded to the metal nitride film. A second embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal oxide film bonded to the metal film; and the silicon dioxide film bonded to the metal oxide film. A third embodiment is a structure having a silicon dioxide film bonded to a metal film comprising: a metal/oxide/nitride film bonded to the metal film; and the silicon dioxide film bonded to the metal/oxide/nitride film.

Abstract: A semiconductor device comprising a thin film transistor, and a process for fabricating the same, the process comprising: a first step of forming an island-like semiconductor layer, a gate insulating film covering the semiconductor layer, and a gate electrode comprising a material containing aluminum as the principal component formed on the gate insulating film; a second step of introducing impurities into the semiconductor layer in a self-aligned manner by using the gate electrode as the mask; a third step of forming an interlayer dielectric to cover the gate electrode, and forming a contact hole in at least one of source and drain; a fourth step of forming over the entire surface, a film containing aluminum as the principal component, and then forming an anodic oxide film by anodically oxidizing the film containing aluminum as the principal component; a fifth step of etching the film containing aluminum as the principal component and the anodic oxide film, thereby forming a second layer interconnection cont

Abstract: The present invention provides an anti-reflection film for lithographic application on tungsten-silicide containing substrate. In one embodiment of the present invention, a structure for improving lithography patterning in integrated circuit comprises a tungsten-silicide layer, a diaphanous layer located above the tungsten-silicide layer, an anti-reflection layer located above the diaphanous layer, and a photoresist layer located above the anti-reflection layer for patterning the integrated circuit pattern.

Abstract: A transistor having a source/drain metal silicide in close proximity to the channel region may be formed according to the following process. A masking structure is formed upon a semiconductor substrate, and a metal is deposited self-aligned to sidewall surfaces of the masking structure. The metal is then annealed to form a metal silicide. Following formation of lightly doped drain impurity areas self-aligned to the sidewall surfaces of the masking structure, spacers may be formed adjacent the sidewall surfaces and source and drain impurity areas may be formed self-aligned to sidewall surfaces of the spacers. Fill structures are then formed adjacent the spacers and the masking structure is removed to form an opening between the spacers. A gate dielectric is formed upon the exposed upper surface of the semiconductor substrate within the opening, and a gate conductor is formed within the opening.

Abstract: The present invention includes a SOI structure formed in a substrate. A gate is formed over the substrate in a recessed portion of a substrate. A first isolation structure is formed on the side walls of the gate. A second isolation structure is formed adjacent to the first isolation structure. Source and drain regions are formed on the SOI structure. Lightly doped drain (LDD) structures are formed adjacent to the source and drain regions, on the SOI structure and under the second isolation structure. A first metal silicide layer is formed on the source and drain regions and a second metal silicide layer is formed on the gate.

Abstract: A semiconductor device with first and second types of devices formed in a semiconductor substrate with a barrier layer formed over the surface of the semiconductor device including over the first and second types of devices with the barrier layer removed from over the first type of device. The first type of device is a positive charge sensitive device such as a nonvolatile memory device. The semiconductor device has a hydrogen getter layer formed under the barrier layer.

Abstract: The formation of a graded passivation layer is disclosed. In one embodiment, a method includes four steps. In the first step, at least one transistor on a semiconductor substrate is provided. In the second step, at least one metallization layer is formed over the at least one transistor. In the third step, an oxide layer is deposited over the at least one metallization layer. Finally, in the fourth step, an ion implantation of a predetermined dopant is applied to create a graded passivation film over the at least one metallization layer.

Abstract: A transistor and a method for making a transistor are described. Barrier species such as nitrogen may be introduced into a semiconductor substrate to form a barrier layer. A dielectric having a high dielectric constant, preferably a metal- and oxygen-bearing dielectric, may then be deposited upon the semiconductor substrate. The barrier layer preferably mitigates short channel effects and prevents dopant and/or metal atom migration into or out of the gate structure. The dielectric may be annealed in an oxygen-bearing atmosphere to passivate the dielectric material and to incorporate barrier species into the dielectric. Alternatively, the anneal may be performed in an inert atmosphere. Following deposition of a conductive gate material upon the dielectric, a gate conductor and gate dielectric may be patterned. Lightly doped drain impurity areas and/or source and drain impurity areas may then be formed in the semiconductor substrate.

Abstract: Disclosed is an improved process and liner for trench isolation which includes either a single oxynitride layer or a dual oxynitride (or oxide)/nitride layer. Such a process and liner has an improved process window as well as being an effective O.sub.2 diffusion barrier and resistant to hot phosphoric and hydrofluoric acids.