Abstract: One aspect of this disclosure relates to a method for creating proximity gettering sites in a semiconductor wafer. In various embodiments of this method, a relaxed silicon germanium region is formed to be proximate to a device region on the semiconductor wafer. The relaxed silicon germanium region generates defects to getter impurities from the device region. In various embodiments, an ultra high vacuum chemical vapor deposition (UHV CVD) process is performed to epitaxially form the relaxed silicon germanium gettering region. In various embodiments, forming the relaxed silicon germanium gettering region includes implanting germanium ions into a silicon substrate with a desired dose and energy to form a silicon region containing germanium ions and heat treating the substrate to regrow a crystalline silicon layer over a resulting silicon germanium layer using a solid phase epitaxial (SPE) process. Other aspects are provided herein.

Abstract: A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.

Abstract: A thin-film transistor is formed by a polycrystalline silicon film having a thin-film part and a thick-film part, the thin-film part minimally being used as a channel part. The polycrystalline silicon film is formed by laser annealing with an energy density that completely melts the thin-film part but does not completely melt the thick-film part. Because large coarse crystal grains growing from the boundary between the thin-film part and the thick-film part form the channel part, it is possible to use a conventional laser annealing apparatus to easily achieve high carrier mobility and low leakage current and the like.

Abstract: The present invention provide an LDD type TFT having excellent properties, particularly for a liquid crystal display unit. For this purpose, a top gate type LDDTFT gate electrode is converted into a two-stage structure by use of a chemical reaction or plating, and furthermore, into a shape in which an upper portion or a lower portion slightly protrudes on the source electrode side, or the drain electrode side relative to the other portions. Impurities are injected by using this electrode having this structure and shape as a mask. Prior to injection of impurities, the gate insulating film is removed, and a Ti film is formed for preventing hydrogen for dilution from coming in. This is also the case with the LDD-TFT on the bottom gate side.

Abstract: A CMOS process for double vertical channel thin film transistor (DVC TFT). This process fabricates a CMOS with a double vertical channel (DVC) structure and defines the channel without an additional mask. The DVC structure of the CMOS side steps the photolithography limitation because the deep-submicrometer channel length is determined by the thickness of gate, thereby decreasing the channel length of the CMOS substantially.

Abstract: A semiconductor device comprising a metal-oxide-semiconductor field-effect transistor well controllably brings the work function of a gate electrode close to the intrinsic mid gap energy of silicon, thereby lowering the concentration of impurities in a channel. By this, the deterioration of carrier mobility is prevented and a metal-oxide-semiconductor field-effect transistor is obtained. A gate electrode has a multi-layer structure of a p-type polycrystalline or a single-crystalline germanium film 3 and a low resistance conductive film 4.

Abstract: A semiconductor device includes a SiC substrate and an ohmic electrode, a semiconductor member including a SiC member and a SiGe member being formed between the SiC substrate and the ohmic electrode, wherein the semiconductor member is composed of a SiGe member formed on a SiC member, and the ohmic electrode is formed on the SiGe member, whereby the ohmic electrode with a low resistance can be formed on the SiC substrate without conducting a heat treatment at a high temperature.

Abstract: There is provided a semiconductor device using a semiconductor thin film having high crystallinity, which is formed by a manufacturing method with high productivity. When active layers of an amorphous silicon film are crystallized, germanium is used as a catalytic element for facilitating crystallization. When a heat treatment is carried out in a state where the active layers are in contact with a germanium film through an opening portion provided in a mask insulating film, the active layers made of a polysilicon film are obtained by crystal growth in a lateral direction.

Abstract: At least one of a semiconductor thin-film for forming a picture display portion and a semiconductor thin-film for forming a peripheral circuit portion, which are accumulated on one common insulative substrate, is constructed with a semiconductor thin-film having a plural number of semiconductor crystalline portions formed to be divided and disposed in a matrix-like, and TFTs are provided in the semiconductor thin-film by bringing those semiconductor single crystal portions into active portions thereof. For that purpose, a crystallization accelerating material is adhered at the position of lattice points of a matrix and is treated with heating process, for forming the single crystal portions disposed in the matrix-like manner, so as to form the TFTs on the surface thereof, thereby completing the thin-film semiconductor integrated circuit device.

Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 &mgr;m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.

Abstract: A silicon germanium layer is deposited over a semiconductor substrate with a gate insulating film interposed between the substrate and the silicon germanium layer. Then, an upper silicon layer in an amorphous state is deposited on the silicon germanium layer. Thereafter, a gate electrode is formed by patterning the silicon germanium layer and the upper silicon layer.

Abstract: A strained silicon p-type MOSFET utilizes a strained silicon channel region formed on a silicon germanium substrate. Silicon germanium regions are formed to the silicon germanium layer adjacent to ends of the strained silicon channel region, and shallow source and drain extensions are implanted in the silicon germanium material. The shallow source and drain extensions do not extend into the strained silicon channel region. By forming the source and drain extensions in silicon germanium material rather than in silicon, source and drain extension distortions caused by the enhanced diffusion rate of boron in silicon are avoided.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. A monocrystalline layer is then formed over the accommodating buffer layer, such that a lattice constant of the monocrystalline layer substantially matches the lattice constant of a subsequently grown monocrystalline film.

Abstract: An apparatus comprising control circuitry formed on a substrate, and a plurality of active media coupled to the control circuitry and formed in a plurality of planes over the substrate. A method comprising forming a pair of junction regions on a substrate separated by a channel length; and forming a channel material overlying and coupled to the pair of junction regions having a dimension at least equal to the channel length. An apparatus comprising a contact formed in a first plane over a device structure; and a device coupled to the contact and formed in a second plane a greater distance from the substrate than the first plane.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from a silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy and epitaxial growth of single crystal silicon onto single crystal oxide materials. Monocrystalline substrates having a hydrogen ion implant are cleaved along the hydrogen ion implant, and an insulating substrate is bonded to the monocrystalline oxide.

Abstract: A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon germanium layer and a silicon layer. The SOI layer is patterned to form an active layer pattern to a certain direction. An insulation layer is formed to cover the active layer pattern. An etch stop layer is stacked on the active layer pattern covered with the insulation layer. The etch stop layer is patterned and removed at a gate region crossing the active layer pattern at the channel region. The insulation layer is removed at the gate region. The silicon germanium layer is isotropically etched and selectively removed to form a cavity at the channel region of the active layer pattern.

Abstract: Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.

Abstract: The present invention discloses a polycrystalline silicon thin film transistor connected to a gate line and a data line that includes a source electrode contacting the data line; a gate electrode contacting the gate line; a drain electrode spaced apart from the source electrode; a polysilicon layer positioned between and contacting the source and the drain electrodes, and acting as a channel area in which electrons flow; at least one metal layer positioned near the polysilicon layer and parallel to a flow direction of the electrons; and a buffer layer interposed between the metal layer and the polysilicon layer.

Abstract: A comparator includes an adjustable offset and particularly dimensioned and configured components. The particular configuration and dimensioning of the comparator ensure that the offset voltage can be set precisely and permanently to a value, which can vary within a large range. The setting of an offset voltage does not lead to the degradation of other properties of the comparator, in particular to a slower reaction to changes in the input voltages.

Abstract: There is disclosed a method of fabricating a thin-film transistor having excellent characteristics. Nickel element is held in contact with selected regions of an amorphous silicon film. Then, thermal processing is performed to crystallize the amorphous film. Subsequently, thermal processing is carried out in an oxidizing ambient containing a halogen element to form a thermal oxide film. At this time, the crystallinity is improved. Also, gettering of the nickel element proceeds. This crystalline silicon film consists of crystals grown radially from a number of points. Consequently, the thin-film transistor having excellent characteristics can be obtained.

Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 &mgr;m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.

Abstract: High quality epitaxial layers of monocrystalline materials can be grown overlying monocrystalline substrates such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. An accommodating buffer layer comprises a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. A monocrystalline layer is then formed over the accommodating buffer layer, such that a lattice constant of the monocrystalline layer substantially matches the lattice constant of a subsequently grown monocrystalline film.

Abstract: The electronic device (1) has a layer (11) of a material comprising a first and a second element. This material has an amorphous and a crystalline state. A transition from the amorphous to the crystalline state can be effected by heating of the material to above a crystallization temperature, for example with a laser. As a result, the layer (11) has a first electrically conducting areas (21), comprising the material in the crystalline state, which are insulated from each other by the first electrically insulating area (23), comprising the material in the amorphous state. The layer (11) may be present as an interconnect layer, but also as a covering layer. Preferably, the material is aluminum-germanium. In the method of patterning a layer (11), electrically conductive areas of the layer can be strengthened by electroplating.

Abstract: A semiconductor device comprises: a channel region 14 of silicon, a source region 26 and a drain region 26 respectively forming junction with the channel region 14, and a gate electrode 30 formed on the channel region 14 interposing an insulation film 16 therebetween, either of the source region 26 and the drain region 26 being formed of SiGeC, which lattice-matches with silicon. Whereby parasitic resistance between the source region and the drain region can be much decreased.

Abstract: An indium-implanted transistor is provided. The transistor has a silicon channel region that includes a buried layer of an Si1−xGex alloy into which indium is implanted, with 10−5≦x≦4×10−1. A first method for fabricating an indium-implanted transistor is also provided. A multilayer composite film is produced on at least one region of a surface of a silicon substrate where a channel region of the transistor is to be formed. The multilayer composite film includes at least one Si1−xGex alloy layer, in which 10−5≦x≦4×10−1, and an external silicon layer. Indium is implanted into the Si1−xGex alloy layer, and fabrication of the transistor is completed so as to produce the transistor with a channel region that includes a buried Si1−xGex alloy layer. Additionally, a second method for fabricating an indium-implanted transistor is provided.

Abstract: A novel and very useful method for forming a crystal silicon film by introducing a metal element which promotes crystallization of silicon to an amorphous silicon film and for eliminating or reducing the metal element existing within the crystal silicon film thus obtained is provided. The method for fabricating a semiconductor device comprises steps of intentionally introducing the metal element which promotes crystallization of silicon to the amorphous silicon film and crystallizing the amorphous silicon film by a first heat treatment to obtain the crystal silicon film; eliminating or reducing the metal element existing within the crystal silicon film by implementing a second heat treatment within an oxidizing atmosphere; eliminating a thermal oxide film formed in the previous step; and forming another thermal oxide film on the surface of the region from which the thermal oxide film has been eliminated by implementing another thermal oxidation.

Abstract: A method of forming a MOSFET device is provided including the steps of forming N− lightly doped source and drain extension regions in the top silicon layer, forming spacers above the N− lightly doped source and drain extension regions and forming N+ source and N+ drain regions in the top silicon layer. A silicide film is then provided over the drain and source regions and the spacers are removed. An ion implantation step is then performed to form damaged sidewall regions in the source body and drain body junction.

Abstract: A method is provided for fabricating a semiconductor device having a gate-all-around architecture. A substrate is produced so as to include an active central region with an active main surface surrounded by an insulating peripheral region with an insulating main surface. The active main surface and the insulating main surface are coextensive and constitute a main surface of the substrate. A fist layer of Ge or an SiGe alloy is formed on the active main surface, and a silicon layer is formed on the first layer and on the insulating main surface. The silicon layer and the first layer are masked and etched in order to form a stack on the active main surface, and the first layer is removed so that the silicon layer of the stack forms a bridge structure over the active main surface. The bridge structure defines a tunnel with a corresponding part of the active main surface.

Abstract: There is provided a semiconductor device having a new structure which allows a high reliability and a high field effect mobility to be realized in the same time. In an insulated gate transistor having an SOI structure utilizing a mono-crystal semiconductor thin film on an insulating layer, pinning regions are formed at edge portions of a channel forming region. The pinning regions suppress a depletion layer from spreading from the drain side and prevent a short-channel effect. In the same time, they also function as a path for drawing out minority carriers generated by impact ionization to the outside and prevent a substrate floating effect from occurring.

Abstract: A high quality semiconductor device comprising at least a semiconductor film having a microcrystal structure is disclosed, wherein said semiconductor film has a lattice distortion therein and comprises crystal grains at an average diameter of 30 Å to 4 &mgr;m as viewed from the upper surface of said semiconductor film and contains oxygen impurity and concentration of said oxygen impurity is not higher than 7×1019 atoms.cm−3 at an inside position of said semiconductor film. Also is disclosed a method for fabricating semiconductor devices mentioned hereinbefore, which comprises depositing an amorphous semiconductor film containing oxygen impurity at a concentration not higher than 7×1019 atoms.cm−3 by sputtering from a semiconductor target containing oxygen impurity at a concentration not higher than 5×1018 atoms.

Abstract: Methods and apparatus for a memory system using a branching point-to-point memory bus architecture are disclosed. In one embodiment, a primary memory controller maintains a point-to-point bus connection with one memory module and that memory module maintains a separate point-to-point bus connection with a second module. Data passing between the memory controller and the second memory module passes through a buffer circuit on the first memory module. For data received from the memory controller, the buffer circuit also passes that data up a module bus segment to a first bank of memory devices. That bank of memory devices maintains a second module bus segment with a second bank of memory devices. Data passing between the buffer circuit and the second bank of memory devices passes through a pass-through circuit on the first bank of memory devices. In this manner, a point-to-point memory bus architecture can be maintained even when a memory module contains more than one bank of memory devices.

Abstract: A method of manufacturing an integrated circuit with a channel region containing germanium. The method includes providing an amorphous semiconductor material including germanium, crystallizing the amorphous semiconductor material, and doping to form a source location and a drain location. The semiconductor material containing germanium can increase the charge mobility associated with the transistor. A double gate structure can also be formed.

Abstract: A monolithically integrated, multi-layer device is fabricated with single crystal films of desired orientation grown from arrayed nucleation sites on amorphous and/or non-single crystal surfaces. Examples of devices which can be produced are CMOS and bipolar devices in single crystal (100) and (111) Si films on amorphous surfaces such as SiO2 or Si3N4 in processed ULSIC wafers. These devices can be integrated along the 3rd dimension. Thus, 3-dimensional IC's can be fabricated. Similarly, high performance CMOS devices in SiGe films, MESFET, HEMT and optical devices in compound semiconductor films, can be fabricated within processed ULSIC wafers. Further, Si—, GaAs—, and other compound semiconductor-based devices in the respective single crystal films with different orientations deposited selectively in a given level, and in multilevel IC's, can be manufactured.

Abstract: The present invention relates to a method of crystallizing an amorphous silicon thin film by thermal annealing the amorphous silicon thin film vapor deposited on a substrate in order to form a polycrystalline silicon thin film, and a semiconductor device fabricated by the method. According to the present invention, it is constructed such that a light-absorbing layer having absorbance of light much higher than that of the substrate or the amorphous silicon thin film is formed around the amorphous silicon thin film and is heated by a lamp when crystallizing the amorphous silicon thin film vapor deposited on the substrate by rapid annealing. Therefore, the temperature of the amorphous silicon thin film can be raised while restraining the increase in temperature of the substrate to the utmost. Accordingly, the amorphous silicon thin film can be crystallized without deformation of the substrate.

Abstract: A read data line pair is arranged for every four memory cell columns. Column selection in data reading is carried out by four sub read source lines. A write data line pair is arranged for every eight memory cell columns. Column selection in a data write operation is carried out by eight sub write activation lines. By differentiating the number between the read data line pairs and the write data line pairs and the corresponding memory cell columns, the wiring pitch of the data lines can be alleviated to suppress parasitic capacitance while avoiding significant increase of the signal lines to execute column selection.

Abstract: The device (10) comprises a deposition chamber (12) containing two electrodes (13, 14), one of which comprises a support (16) for a substrate (17) and is earthed, the other being connected to an electric radio frequency generator (15). The device includes a mechanism (23) for extracting gas from the chamber (12) and a mechanism (18) for supplying gas. The device also comprises a mechanism for purification (31) of the gases introduced into the chamber, these a mechanism being arranged so as to reduce the number of oxygen atoms contained in the deposition gas, such gas being made up of silane, hydrogen and/or argon. The procedure consists of creating a vacuum in the deposition chamber (12), purifying the gases using purification a mechanism (31), introducing these purified gases into the chamber (12), then creating a plasma between the electrodes (13, 14). A film of intrinsic microcrystalline silicon in then deposited on the substrate.

Abstract: A technique for forming a film of material (12) from a donor substrate (10). The technique has a step of introducing energetic particles (22) through a surface of a donor substrate (10) to a selected depth (20) underneath the surface, where the particles have a relatively high concentration to define a donor substrate material (12) above the selected depth. An energy source is directed to a selected region of the donor substrate to initiate a controlled cleaving action of the substrate (10) at the selected depth (20), whereupon the cleaving action provides an expanding cleave front to free the donor material from a remaining portion of the donor substrate.

Abstract: A method of manufacturing a polycrystalline silicon film having a particular field effect mobility is disclosed. A first polycrystalline silicon film is formed on a transparent insulation substrate. The surface of the silicon film is oxidized, and an amorphous silicon film is formed on the first polycrystalline silicon film and oxide layer. The amorphous silicon film is subjected to a solid phase growth process to be converted to a second polycrystalline silicon film. The field effect mobility of the second polycrystalline silicon film can be adjusted to a desired value by controlling the relative thicknesses of the first and second polycrystalline silicon films.

Abstract: A transistor having source and drain regions which include lower-bandgap portions and a method for making the same are provided. A gate conductor is formed over a gate dielectric on a semiconductor substrate. The gate conductor is covered on all sides with oxide or another dielectric for protection during subsequent processing. Anisotropic etching is used to form shallow trenches in the substrate on either side of the gate conductor. The trenches are bounded by the dielectric-coated gate conductor and by dielectric isolation regions, or by an adjacent gate conductor in the case of non-isolated transistors. A selective epitaxy technique may then be used to grow a layer within each trench of a material having a bandgap lower than that of the semiconductor substrate. The lower-bandgap material is preferably grown only on the exposed semiconductor surfaces in the trenches, and not on the surrounding dielectric regions.

Abstract: A semiconductor memory device using silicon-rich amorphous silicon alloy material memory elements that are electrically programmable by means of current induced conductivity comprises a layer (10) of the alloy material on opposing sides of which sets of input and output contacts (16, 18) are provided, and discrete conductive elements (20) within the layer which serve as nodes and define programmable conductive paths between input and output contacts to create a three dimensional memory network. The conductive elements can be arranged at one or more levels within the thickness of the alloy layer and preferably are of defined shape forming a predetermined 2D array at each level.

Abstract: A method for forming buried oxide regions below a single crystal semiconductor layer incorporating the steps of forming epitaxial layers having different rates of oxidation with the lower layer having a faster rate of oxidation and oxidizing the layers through an opening in a mask. A plurality of oxide isolated FET's may be formed. The invention reduces the problem of source/drain parasitic capacitance and short channel effects while isolating FET's and eliminating floating body effects of an FET by selectively oxidizing semiconductor layers.

Abstract: A silicon on insulator (SOI) device includes an electrically-conducting interface region along a portion of the interface between the insulator and a semiconductor layer atop the insulator. The electrically-conducting interface region provides a “leaky” electrical coupling between the body and source regions of a transistor device such as a “MOSFET”, thereby reducing floating body effects of the device. A method of forming such a semiconductor device includes forming the electrically-conducting interface region by damaging or implanting materials in the insulator and/or the semiconductor in the vicinity of the interface therebetween. The method may include producing a stepped interface region, such as by etching, in order to aid properly locating the transistor device relative to the electrically-conducting interface region.

Abstract: A microcrystal silicon film is formed on a substrate by using a silicide gas, a hydrogen gas, and a source gas that enables introduction of a metal element for accelerating crystallization of silicon in a capacitance-coupling plasma CVD apparatus. The action of the metal element provides a high film forming rate. Therefore, a technique for forming a microcrystal silicon film with high quality and high film forming rate can be provided.

Abstract: The semiconductor device includes and the method for fabricating the same forms a damaged region under a gate electrode to improve device performance and simplify the process. The semiconductor device includes a substrate in which a buried insulating layer is formed; device isolating layers buried in first predetermined areas of the substrate to contact with the buried insulating layer; a gate electrode formed over a second predetermined area of the substrate; sidewall spacers formed on both sides of the gate electrode; source and drain regions at both sides of the gate electrode; and the damaged region at boundary of the buried insulating layer under the gate electrode.

Abstract: On the polycrystal semiconductor film 3 formed on the insulating substrate 1, the source 6 and drain 7 in LDD structure having a low concentration region 4 and a high concentration region 5 are formed. The region 4 has a low impurity concentration, and the region 5 has a high impurity concentration. The length of the low concentration region 4 measured from the edge of gate insulating film 9 is not smaller than the average grain size of the polycrystal semiconductor film 3. The LCD device employing the TFT thus constructed is free from white spots (micro brighter spots) in a high temperature atmosphere.

Abstract: In thin film transistor, an amorphous diamond is used as an ohmic layer formed between an active layer and a source and drain electrodes. Specifically, in a inverse staggered type thin film transistor, a gate electrode and a gate insulating layer are formed on an insulating substrate. On the gate insulating layer is formed an active layer. An etch stopper is formed on the active layer, overlapping with the gate electrode. Thereafter, an amorphous diamond is overlappingly formed on the gate electrode on a resultant structure and then a metal layer is formed on the resultant in which the ohmic layer is formed. The metal layer and the amorphous diamond layer is patterned until the etch stopper is exposed, forming the ohmic layer and a source electrode and a drain electrode.

Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 .mu.m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.

Abstract: A first heat treatment for crystallization is implemented after introducing nickel to an amorphous silicon film 103 disposed on a quartz substrate 101. A crystal silicon film 105 is obtained by this heat treatment. Then, a oxide film 106 is formed by wet oxidation. At this time, the nickel element is gettered to the oxide film 106 by an action of fluorite. Then, the oxide film 106 is removed. Thereby, a crystal silicon film 107 having low concentration of the metal element and a high crystallinity can be obtained.

Abstract: A transistor includes an MILC (metal-induced lateral crystallization) region formed on a substrate with a semiconductor material and including a channel region, and a plurality of MIC (metal-induced crystallization) regions formed on the sides of the MILC region with a semiconductor material, wherein at least one boundary between the MILC region and one of the MIC regions is located outside the channel region. A method of fabricating a transistor includes the steps of forming an MILC (metal-induced lateral crystallization) region on a substrate using a semiconductor material, the MILC region including a channel region, and forming a plurality of MIC (metal-induced crystallization) regions formed on sides of the MILC region using a semiconductor material, wherein at least one boundary between the MILC region and one of the MIC regions is located outside the channel region.

Abstract: A semiconductor device includes a substrate having an insulating film on its surface, and an active layer made of a semiconductive thin film on the substrate surface. The thin film contains a mono-domain region formed of multiple columnar and/or needle-like crystals parallel to the substrate surface without including crystal boundaries therein, allowing the active layer to consist of the mono-domain region only. The insulating film underlying the active layer has a specific surface configuration of an intended pattern in profile, including projections or recesses. To fabricate the active layer, form a silicon oxide film by sputtering on the substrate. Pattern the silicon oxide film providing the surface configuration. Form an amorphous silicon film by low pressure CVD on the silicon oxide film. Retain in the silicon oxide film and/or the amorphous silicon film certain metallic element for acceleration of crystallization.