Abstract: A channel forming region of a thin-film transistor is covered with an electrode and wiring line that extends from a source line. As a result, the channel forming region is prevented from being illuminated with light coming from above the thin-film transistor, whereby the characteristics of the thin-film transistor can be made stable.

Abstract: An object of the present invention is to increase adhesiveness between thin films, particularly a high molecular film formed on an insulating surface, and the present invention provides a semiconductor device with high reliability and a method for manufacturing the semiconductor device with high yield. A semiconductor device of the present invention comprises a laminate structure formed in close contact with an organic insulating film on a hydrophobic surface of an inorganic insulating film including silicon and nitrogen. A film having the hydrophobic surface is an insulating film having a contact angle of water of equal to or more than 30°, preferably of equal to or more than 40°.

Abstract: According to the invention, the thin film having the thickness controlled desirably can be easily formed using common semiconductor processes. Provided is a coating liquid for forming the porous film having an excellent dielectric property and mechanical property. Specifically, the coating liquid for forming a porous film comprises the condensation product obtained by condensation of one or more silicate compounds represented by the formula (X2O) i(SiO2)j(H2O)k and one more organosilate compounds represented by the formula (X2O)a(RSiO1.5)b(H2O)c. Thus, the porous insulating film having sufficient mechanical strength and dielectric properties for use in the semiconductor manufacturing process can be manufactured.

Abstract: A film structure includes low-k dielectric films and N—H base source films such as barrier layer films, etch-stop films and hardmask films. Interposed between the low-k dielectric film and adjacent N—H base film is a TEOS oxide film which suppresses the diffusion of amines or other N—H bases from the N—H base source film to the low-k dielectric film. The film structure may be patterned using DUV lithography and a chemically amplified photoresist since there are no base groups present in the low-k dielectric films to neutralize the acid catalysts in the chemically amplified photoresist.

Abstract: A thin InGaAs contact layer is provided for the collector of a heterojunction bipolar transistor (HBT) above an InP sub-collector. The contact layer provides a low resistance contact mechanism and a high thermal conductivity path for removing device heat though the sub-collector, and also serves as an etch stop to protect the sub-collector during device fabrication. A portion of the sub-collector lateral to the remainder of the HBT is rendered electrically insulative, preferably by an ion implant, to provide electrical isolation for the device and improve its planarity by avoiding etching through the sub-collector.

Abstract: A semiconductor device includes an insulating layer, a conducting portion, and a modified layer. The insulating layer is formed on a semiconductor substrate. The conducting portion is formed in the insulating layer. The modified layer is formed between the insulating layer and the conducting portion. The insulating layer includes hydrogenated polysiloxane. The modified layer is a layer to which the hydrogenated polysiloxane is modified. A portion of the modified layer far from the semiconductor substrate may be thicker than a portion of the modified layer near the semiconductor substrate.

Abstract: An organic light emitting device display may include transverse row and column lines. In a passively driven OLED display, a fuse may be positioned between the OLED material and the row electrode. When a short occurs, the single pixel may be separated from the circuit by the fuse, avoiding the possibility that an entire row of pixels may be adversely affected by the short associated with one single pixel along a row.

Abstract: A resin material having low dielectric constant is used as an inter-layer insulating film and its bottom surface is contacted with a silicon oxide film across the whole surface thereof. Thereby, the surface may be flattened and capacity produced between a thin film transistor and an pixel electrode may be reduced. Further, it allows to avoid a problem that impurity ions and moisture infiltrate into the lower surface of the resin material, thus degrading the reliability of whole semiconductor device.

Abstract: In one aspect, the invention encompasses a semiconductor processing method wherein a conductive copper-containing material is formed over a semiconductive substrate and a second material is formed proximate the conductive material. A barrier layer is formed between the conductive material and the second material. The barrier layer comprises a compound having silicon chemically bonded to both nitrogen and an organic material. In another aspect, the invention encompasses a composition of matter comprising silicon chemically bonded to both nitrogen and an organic material. The nitrogen is not bonded to carbon. In yet another aspect, the invention encompasses a semiconductor processing method. A semiconductive substrate is provided and a layer is formed over the semiconductive substrate. The layer comprises a compound having silicon chemically bonded to both nitrogen and an organic material.

Abstract: Conductive lines, such as co-axial lines, integrated circuitry incorporating such conductive lines, and methods of forming the same are described. In one aspect, a substrate having an outer surface is provided. A masking material is formed over the outer surface and subsequently patterned to form a conductive line pattern. An inner conductive layer is formed within the conductive line pattern, followed by formation of a dielectric layer thereover and an outer conductive layer over the dielectric layer. Preferred implementations include forming the inner conductive layer through electroplating, or alternatively, electroless plating techniques. Other preferred implementations include forming the dielectric layer from suitable polymer materials having desired dielectric properties. A vapor-deposited dielectric layer of Parylene is one such preferred dielectric material.

Abstract: The invention provides processes for the formation of structures in microelectronic devices such as integrated circuit devices. More particularly, the invention relates to the formation of vias, interconnect metallization and wiring lines using multiple low dielectric-constant inter-metal dielectrics. The processes use two or more dissimilar low-k dielectrics for the inter-metal dielectrics of Cu-based dual damascene backends of integrated circuits. The use of both organic and inorganic low-k dielectrics offers advantages due to the significantly different plasma etch characteristics of the two kinds of dielectrics. One dielectric serves as the etchstop in etching the other dielectric so that no additional etchstop layer is required. Exceptional performance is achieved due to the lower parasitic capacitance resulting from the use of low-k dielectrics.

Abstract: A semiconductor device is provided with a plurality of protrusions which are made of a resin and which protrude higher than electrodes, and conductive layers which are electrically connected to the electrodes and which cover the top surfaces of the protrusions. A method for manufacturing the semiconductor device includes a step of applying a layer of the resin to the semiconductor device except for the electrodes, a step of patterning the conductive layers on the electrodes and the layer of the resin in accordance with the protrusions, and a step of removing the layer of the resin located between the conductive layers by the use of the patterned conductive layers as masks so as to form the protrusions.

Abstract: A semiconductor structure may be covered with a thermally decomposing film. That film may then be covered by a sealing cover. Subsequently, the thermally decomposing material may be decomposed, forming a cavity.

Abstract: A polymer or organic light emitting display may be formed on a substrate by patterning the light emitting material using a screen printing technique. In this way, displays may be formed economically, overcoming the difficulties associated with photoprocessing light emitting materials. A binary optic material may be selectively incorporated into sol gel coatings coated over light emitting elements formed from the light emitting material. A tricolor display may be produced using a light emitting material that produces a single color.

Abstract: A power module includes a substrate with a power semiconductor device mounted thereon, a case having an interior in which the substrate is disposed, a cooling fin having a surface on which the substrate and the case are placed, and a smoothing capacitor disposed on an opposite surface of the cooling fin from the surface on which the substrate is placed, the smoothing capacitor being electrically connected to the power semiconductor device for smoothing a voltage to be externally supplied to the power semiconductor device.

Abstract: A method for forming semiconductor device packages including one or more semiconductor dice, leads in communication with bond pads of the dice, and a protective layer, or package, over at least the active surfaces of the semiconductor dice. The protective layer covers at least the bond pads, the proximate regions of the corresponding leads, and the conductive elements between the bond pads and their corresponding leads. The leads are at least electrically exposed through the protective layer. A portion of each lead may be physically exposed through the protective layer so as to facilitate connection of each lead to external circuitry. The packages may also include protective layers over the back sides or the edges of the semiconductor dice. A stereolithographic process is used for precisely forming the protective layers of the package. A machine vision system is used in connection with stereolithographic equipment to locate individual dice, features thereof, or leads.

Abstract: A method for producing a semiconductor component with the following steps. A semiconductor chip is provided having electrical contacts in a contact making region. A housing including a rear plate and a side area is provided and surrounds the semiconductor chip. A first compliant buffer layer is applied on a rear plate. The semiconductor chip is applied to the first compliant buffer layer, and a second compliant buffer layer is applied to and around the semiconductor chip except in the contact making region. A contact passage plate is provided with an opening over the contact areas and the contact passage plate is fixed to the second compliant buffer layer.

Abstract: A material layer which contains nitrogen atoms is formed on a first wiring or at a side surface of a first wiring. When etching for forming a via hole is carried out, nitrogen atoms contained in the material layer bind with CF molecules, CF2 molecules, CF3 molecules and the like contained in an etching gas, and compounds thus formed adhere to a surface of a silicon dioxide layer at side walls and a bottom portion of a via hole. As a result, once the material layer is exposed during etching for forming a via hole, thereafter, the etching rate decreases. Accordingly, even if there is misalignment of a via hole pattern with respect to a first wiring pattern when the via hole pattern is formed by lithography, etching of the silicon dioxide layer does not proceed to an underlying silicon substrate. Thus, short circuits are not formed between the first wiring and the silicon substrate via a second wiring layer which is deposited later.

Abstract: A thin film transistor wherein the semiconductor layer is prepared by a process including:

Abstract: A method for forming a film having a low dielectric constant and high mechanical hardness on a semiconductor substrate by plasma reaction includes the steps of: (i) introducing a silicon-containing hydrocarbon gas as a source gas into a reaction space for plasma CVD processing wherein a semiconductor substrate is placed; and (ii) applying radio-frequency (RF) power of 1,000 W or higher to the reaction space while maintaining a pressure of the reaction space at 100 Pa or higher to activate plasma polymerization reaction in the reaction space, thereby forming a thin film on the semiconductor substrate.

Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.

Abstract: A ferroelectric memory circuit includes a ferroelectric memory cell in the form of a ferroelectric polymer thin film and first and second electrodes respectively, contacting the ferroelectric memory cell at opposite surfaces thereof, whereby a polarization state of the cell can be set, switched or detected by applying appropriate voltages to the electrodes. At least one of the electrodes includes at least one contact layer. The at least one contact layer including a conducting polymer contacting the memory cell, and optionally a second layer of a metal film contacting the conducting polymer, whereby the at least one of the electrodes either includes a conducting polymer contact layer only, or a combination of a conducting polymer contact layer and a metal film layer.

Abstract: The invention is a semiconductor device and method of fabricating the device. The device includes a semiconductor substrate with an active region, and a low dielectric constant insulating layer formed over the substrate. An additional insulating layer is formed over the low dielectric constant layer by a low temperature deposition, such as ion beam assistance deposition. A metal layer can then be formed over the additional layer using lift-off techniques. The metal layer can be patterned to form a bond pad which may be displaced from the area over the active region. Wire bonds can be made on the bond pad using ultrasonic energy.

Abstract: The ferroelectric film of the invention is made from a ferroelectric material represented by a general formula, Bi4−x+yAxTi3O12 or (Bi4−x+yAxTi3O12)z+(DBi2E2O9)1−z, wherein A is an element selected from the group consisting of La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and V; D is an element selected from the group consisting of Sr, Ba, Ca, Bi, Cd, Pb and La; E is an element selected from the group consisting of Ti, Ta, Hf, W, Nb, Zr and Cr; and 0≦x≦2, 0<y≦(4−x)×0.1 and 0.5<z<1.

Abstract: Porous insulation films 28, 40, 50 are formed of an insulation forming material including a silicon compound having a skeleton containing C—C bonds, a pore forming compound which is decomposed or evaporated by a heat treatment, and a solvent which dissolves the silicon compound with the pore forming compound, whereby the porous insulation film can have good mechanical strength and low dielectric constant.

Abstract: A method and structure for protecting a flowable oxide insulator in a semiconductor by oxidizing sidewalls of the FOX insulator, optionally nitridizing the oxidized FOX sidewalls, and then covering all surfaces of a trough or plurality of troughs in the FOX insulator, including the sidewalls, with a conductive secondary protective layer. In a multiple layer damascene structure, the surface of the FOX insulator is also oxidized, an additional oxide layer is deposited thereon, and a nitride layer deposited on the oxide layer. Then steps are repeated to obtain a comparable damascene structure. The materials can vary and each damascene layer may be either a single damascene or a dual damascene layer.

Abstract: A low dielectric constant, thermally stable hydrogenated oxidized silicon carbon film which can be used as an interconnect dielectric in IC chips is disclosed. Also disclosed is a method for fabricating a thermally stable hydrogenated oxidized silicon carbon low dielectric constant film utilizing a plasma enhanced chemical vapor deposition technique. Electronic devices containing insulating layers of thermally stable hydrogenated oxidized silicon carbon low dielectric constant materials that are prepared by the method are further disclosed. To enable the fabrication of thermally stable hydrogenated oxidized silicon carbon low dielectric constant film, specific precursor materials having a ring structure are preferred.

Abstract: A spin-on cap useful as a post-CMP cap for Cu interconnect structures is provided. The inventive spin-on cap includes a low-k dielectric (on the order of 3.5 or less) and at least one additive. The at least one additive employed in the present invention is capable of binding Cu ions, and is soluble in the spun-on low-k dielectric. The spin-on cap of the present invention may further include a spun-on low-k (on the order of 3.5 or less) reactive-ion etch (RIE) stop layer. Spin-on caps containing a bilayer of low-dielectric plus at least additive and low-k RIE stop layer are preferred. It is noted that the inventive spin-on cap of the present invention does not significantly increase the effective dielectric constant of the interconnect structure and does not add additional cost to the fabrication of the interconnect structure since a single deposition tool, i.e., spin coating tool, is employed. Moreover, because of the presence of the additive in the spin-on cap, Cu migration is substantially minimized.

Abstract: In a semiconductor device fabrication method, a first low dielectric constant film having a specific dielectric constant of k less than 3 (k<3) is formed over a wafer so that an edge position of the first low dielectric constant film aligns with a first position along the circumference of the wafer. Then, a first protection layer having a gas permeability lower than that of the first low dielectric constant film is formed over the first low dielectric constant film and the wafer so that an edge of the first protection layer aligns with a second position that is located outside the first position. Then, a second low dielectric constant film having a specific dielectric constant of k less than 3 (k<3) is formed over the first protection layer so that an edge of the second low dielectric constant film is located at the first position.

Abstract: The present invention describes a structure having a multilayer stack of thin films, the thin films being a low-dielectric constant material, the thin films having pores, and a method of forming such a structure.

Abstract: A fabrication process for making a semiconductor device, which contains a dry etch plasma process that utilizes CO2 to etch a film. Furthermore, the dry etch plasma process may utilize CO2 in combination with NH3, H2, Ar, N2, He, or other inert gases during the etching process. The CO2 dry etch plasma process etches an anti-reflectant coating layer while enabling greater selectivity and control with regard to the underlying films.

Abstract: A novel dielectric composition is provided that is useful in the manufacture of electronic devices such as integrated circuit devices and integrated circuit packaging devices. The dielectric composition is prepared by crosslinking a thermally decomposable porogen to a host polymer via a coupling agent, followed by heating to a temperature suitable to decompose the porogen. The porous materials that result have dielectric constants of less than 2.4.

Abstract: This invention discloses a process for forming durable anti-stiction surfaces on micromachined structures while they are still in wafer form (i.e., before they are separated into discrete devices for assembly into packages). This process involves the vapor deposition of a material to create a low stiction surface. It also discloses chemicals which are effective in imparting an anti-stiction property to the chip. These include polyphenylsiloxanes, silanol terminated phenylsiloxanes and similar materials.

Abstract: The present invention provides for low cost discrete inductor devices in an all organic platform. The inductor devices can utilize virtually any organic material that provides the desired properties, such as liquid crystalline polymer (LCP) or polyphenyl ether (PPE), in a multilayer structure, wherein the organic materials have low moisture uptake and good temperature stability. Each layer may be metalized and selectively interconnected by vias formed in respective layers so as to form winding or coiled inductors. The inductor devices may advantageously include external shielding formed by metalizing the side walls and top surface of the inductor devices on in-built shielding achieved by the utilization of the hybrid co-planar waveguide topologies. The inductor devices can be configured for either ball grid array (BGA)/chip scale package (CSP) or surface mount device (SMD) mounting to circuit boards.

Abstract: Disclosed is a conductive fuse for a semiconductor device, comprising: a pair of contact portions integrally connected to a fusible portion by connecting portions; the contact portions thicker than the connecting portions and the connecting portions thicker than the fusible portion; a first dielectric under the connecting portions and the fusible portion and extending between the pair of contact portions; and a second dielectric between the first dielectric and the fusible portion, the second dielectric extending between the connecting portions and defining the length of the fusible portion.

Abstract: A semiconductor component with passivation includes at least two double passivating layers, of which an uppermost is applied to a planar surface of a layer located therebelow. The double passivating layers include two layers of different dielectric materials, for example silicon oxide and silicon nitride. The respective thicknesses of the individual passivating layers can be adapted to dimensions of the structuring of the layer to which the passivation is applied. This produces a reliable passivation which is particularly suitable for capacitively measuring fingerprint sensors.

Abstract: A device for the detection of electromagnetic radiation, wherein the device has (i) a photoactive layer of a semiconductor having a band gap of greater than 2.5 eV, (ii) a dye applied to the semiconductor, and (iii) a charge transport layer comprising a hole conductor material, where the hole conductor material is preferably solid and amorphous.

Abstract: A siloxan polymer insulation film has a dielectric constant of 3.3 or lower and has —SiR2O— repeating structural units. The siloxan polymer has dielectric constant, high thermal stability and high humidity-resistance on a semiconductor substrate. The siloxan polymer is formed by directly vaporizing a silicon-containing hydrocarbon compound expressed by the general formula Si&agr;O&bgr;CxHy (&agr;, &bgr;, x, and y are integers) and then introducing the vaporized compound to the reaction chamber of the plasma CVD apparatus. The residence time of the source gas is lengthened by reducing the total flow of the reaction gas, in such a way as to form a siloxan polymer film having a micropore porous structure with low dielectric constant.

Abstract: Two aspects, an impurity factor and a structural factor are assumed as the deterioration causes of an organic light emitting device and means for solving the respective factors are provided. In order to prevent deterioration of the light emitting device, concentrations of moisture and oxygen, which are left in a space in which an organic light emitting element is sealed, are minimized. At the same time, an impurity including oxygen, such as moisture or oxygen which is included in an organic compound composing the organic light emitting element, is reduced. An element structure for preventing the deterioration of the organic light emitting element due to stress is used to suppress the deterioration.

Abstract: Low resistance metal/semiconductor and metal/insulator contacts incorporate metal nanocrystals embedded in another metal having a different work function. The contacts are fabricated by placing a wetting layer of a first metal on a substrate, which may be a semiconductor or an insulator and then heating to form nanocrystals on the semiconductor or insulator surface. A second metal having a different work function than the first is then deposited on the surface so that the nanocrystals are embedded in the second material.

Abstract: A semiconductor device comprising organic semiconductor material (14) has one or more barrier layers (16) disposed at least partially thereabout to protect the organic semiconductor material (14) from environment-driven changes that typically lead to inoperability of a corresponding device. If desired, the barrier layer can be comprised of partially permeable material that allows some substances therethrough to thereby effect disabling of the encapsulated organic semiconductor device after a substantially predetermined period of time. Getterers (141) may also be used to protect, at least for a period of time, such organic semiconductor material.

Abstract: A magnetic tunnel junction (MTJ) sensor system and a method for fabricating the same are provided. First provided are a first lead layer, and a pinned layer. Positioned adjacent to pinned layer is a free layer. The magnetization direction of the pinned layer is substantially perpendicular to the magnetization direction of the free layer at zero applied magnetic field. Also included is a tunnel barrier layer positioned between the pinned layer and the free layer. Further provided is a second lead layer, where the pinned layer, the free layer, and the tunnel barrier layer are positioned between the first lead layer and the second lead layer. A pair of hard bias layers are positioned adjacent to the pinned layer, the free layer, and the tunnel barrier layer. To prevent shunt currents from flowing, insulating layers are positioned between the hard bias layers and the first lead layer and the second lead layer. Such insulating layers are constructed from a non-conductive, magnetic material.

Abstract: In the present invention, provided are a semiconductor device having a semiconductor-element-mounting substrate on which a semiconductor element has been mounted via an adhesive having an exothermic-reaction curing start temperature of 130° C. or below as measured with a differential scanning calorimeter at a heating rate of 10° C./minute, and a process for its fabrication.

Abstract: A method for forming a thin film includes the steps of: supplying a deposition material in the form of a liquid onto a heated surface; heating and vaporizing the deposition material on the heated surface while the deposition material is undergoing movement; and depositing the deposition material onto a deposition surface. The deposition material is supplied onto a position of the heated surface where the vaporized deposition material does not reach the deposition surface.

Abstract: A novel encoding system, compositions for use therein and methods for determining the source, location and/or identity of a particular item or component of interest is provided. In particular, the present invention utilizes a collection of one or more sizes of populations of semiconductor nanocrystals having characteristic spectral emissions, to “track” the source or location of an item of interest or to identify a particular item of interest. The semiconductor nanocrystals used in the inventive compositions can be selected to emit a desired wavelength to produce a characteristic spectral emission in narrow spectral widths, and with a symmetric, nearly Gaussian line shape, by changing the composition and size of the semiconductor nanocrystal. Additionally, the intensity of the emission at a particular characteristic wavelength can also be varied, thus enabling the use of binary or higher order encoding schemes.

Abstract: This invention relates generally to a new method of forming semiconductor substrates with defect-free surface metallurgical features. In particular, the invention related to a method for providing surface protected ceramic green sheet laminates using at least one thermally depolymerizable surface layer. More particularly, the invention encompasses a method for fabricating semiconductor substrates wherein a thermally depolymerizable/decomposable surface film is placed over a ceramic green sheet stack or assembly prior to lamination and caused to conform to the surface topography of the green sheet during lamination. The invention also encompasses a method for fabricating surface protected green sheet laminates which can be sized or diced without causing process related defects on the ceramic surface.

Abstract: A silicon oxide layer is produced by plasma enhanced oxidation of an organosilicon compound to deposit films having a carbon content of at least 1% by atomic weight. Films having low moisture content and resistance to cracking are deposited by introducing oxygen into the processing chamber at a flow rate of less than or equal to the flow rate of the organosilicon compounds, and generating a plasma at a power density ranging between 0.9 W/cm2 and about 3.2 W/cm2. An optional carrier gas may be introduced to facilitate the deposition process at a flow rate less than or equal to the flow rate of the organosilicon compounds. The organosilicon compound preferably has 2 or 3 carbon atoms bonded to each silicon atom, such as trimethylsilane, (CH3)3SiH. An oxygen rich surface may be formed adjacent the silicon oxide layer by temporarily increasing oxidation of the organosilicon compound.

Abstract: An ohmic resistance is present between two parts of a conductor layer so that the size of the ohmic resistance can be ascertained and/or a semiconductor region is present in or on a layer forming the dielectric. The conductor layer is structured into a gate contact, a source contact, and a drain contact so that a transistor function or switching function is possible in the semiconductor region. Such a configuration allows an attempt to analyze the circuit integrated in the chip to be detected.

Abstract: A semiconductor device and a process for production thereof, said semiconductor device having a new electrode structure which has a low resistivity and withstands heat treatment at 400° C. and above. Heat treatment at a high temperature (400-700° C.) is possible because the wiring is made of Ta film or Ta-based film having high heat resistance. This heat treatment permits the gettering of metal element in crystalline silicon film. Since this heat treatment is lower than the temperature which the gate wiring (0.1-5 &mgr;m wide) withstands and the gate wiring is protected with a protective film, the gate wiring retains its low resistance.

Abstract: Integrated circuit packages that may be easily stacked one on top of the other are disclosed. The package includes a molded plastic body having metal-coated interconnection posts on both its upper and lower surfaces. An integrated circuit is mounted on the upper surface. Metal traces on the upper surface electrically connect each bonding pad on the integrated circuit to a one of a plurality of groups of four interconnection posts on the upper surface. Vias through the substrate electrically connect each group of four posts on the upper surface to an interconnection post on the lower surface of the package. Two or more packages can be stacked and electrically connected by wedging the lower posts of a top package between each group of four posts on the upper surface of a lower package. The lower posts of the lower package may be soldered to a conventional printed circuit board, or may be mounted on a mounting substrate that also has corresponding groups of four interconnection posts.