Abstract: An electrically dynamic window structure may include first and second panes of transparent material and an electrically controllable optically active material positioned between the two panes. A driver can be electrically connected to electrode layers carried by the two panes. The driver may be configured to alternate between a drive phase in which a drive signal is applied to the electrode layers and an idle phase in which the drive signal is not applied to the electrode layers. The electrically controllable optically active material can maintain its transition state during the idle phase. As a result, the power consumption of the structure may be reduced as compared to if the driver continuously delivers the drive signal.

Abstract: A capacitive level sensor device, for detecting the level of a medium contained in a container, comprises a circuit support, which extends longitudinally substantially according to level-detection axis. The circuit support has, in a detection region thereof, at least one first plurality of first capacitive elements, which comprise at least one first array of first electrodes (J), preferably spaced from one another along the level-detection axis, which are arranged in a position corresponding to at least one first side of the circuit support. The sensor device has a casing body which comprises an electrically insulating and fluid-tight detection portion, which covers the detection region of the circuit support. The detection portion of the casing body comprises an overmoulded outer coating, made of a first electrically insulating polymeric material, which defines an outer surface of the casing body designed to be in contact with the medium the level of which has to be detected.

Abstract: A method for manufacturing a 3D integrated circuit is provided. A manufacturing system provides a first integrated circuit having a first surface and a first via extending to the first surface. The manufacturing system applies a first controlled collapse chip connection (C4) solder bump to the first via. The manufacturing system provides a second integrated circuit having a second surface and a second via extending to the second surface. The manufacturing system applies a second C4 solder bump to the second via. The manufacturing system overturns the second integrated circuit onto the first integrated circuit and aligns the first C4 solder bump with the second C4 bump. The manufacturing system heats the first C4 solder bump and the second C4 solder bump until the first via contact is soldered to the second via.

Abstract: A method for manufacturing a circuit board includes forming a patterned first dielectric layer on a substrate; forming a first adhesive layer on the patterned first dielectric layer; forming a second dielectric layer on the first adhesive layer; patterning the second dielectric layer to expose a portion of a top surface of the first adhesive layer opposite to the substrate; and filling at least the patterned second dielectric layer with a conductive material, such that the conductive material is in contact with the top surface of the first adhesive layer.

Abstract: The present invention provides a manufacturing method for an electronic element of an electronic apparatus. The electronic element includes a substrate, a bump and at least one under bump metal (UBM) layer. The manufacturing method includes sequentially disposing the UBM layer and the bump onto the substrate; and processing an etching operation at the UBM layer to form a breach structure.

Abstract: A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film.

Abstract: An apparatus for supporting a substrate in a process chamber and regulating surface temperature of the substrate and method of making the same is provided. The apparatus includes a base support having a surface adapted to support the substrate and a heater for heating the substrate with the heater being disposed proximate the base support. The base support is made of a composite material comprising a plurality of thermally conductive arcuate members embedded within a matrix, each of the plurality thermally conductive arcuate members being arranged concentrically and defining predetermined intervals in a radial direction such that the composite material provides an anisotropic thermal conductivity in radial (?), azimuthal (?) and axial (z) directions in a cylindrical coordinate system of the base support.

Abstract: A pharmaceutical package may include a glass body enclosing an inner volume and having an exterior surface. The glass body may be formed from a borosilicate glass that meets the Type 1 criteria according to USP <660>or an alkali aluminosilicate glass having a Class HGA 1 hydrolytic resistance when tested according to the ISO 720-1985 testing standard. A coupling agent layer having a first thickness less than or equal to 100 nm may be disposed on the exterior surface of the glass body. A polymer layer having a second thickness of less than 50 nm may be positioned over the coupling agent layer. The exterior surface of the glass body with the coupling agent layer and the polymer layer may have a coefficient of friction less than or equal to 0.7.

Abstract: A semiconductor device includes a passivation layer overlying a semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer overlies the interconnect structure and includes a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.

Abstract: Systems and methods for bonding include selectively heating an initial location of a sample to melt a bonding layer at an interface between a first layer and a second layer of the sample. The heating is propagated in a direction away from the initial location such that a melt front of the bonding layer is translated across the interface to provide a void free bond between the first layer and the second layer.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.

Abstract: An organic light-emitting display apparatus includes a thin film transistor including an active layer, a gate electrode, source and drain electrodes, a first insulating layer between the active layer and the gate electrode, and a second insulating layer between the gate electrode and the source and drain electrodes, a third insulating layer covering the source and drain electrodes, the third insulating layer being an organic insulating layer, a pixel electrode including a semi-transparent metal layer and having an end located in a trench formed around the first insulating layer, a fourth insulating layer including an opening exposing a top surface of the pixel electrode, the fourth insulating layer being an organic insulating layer, an organic light-emitting layer on the pixel electrode, and a counter electrode on the organic light-emitting layer.

Abstract: A method of making an electronic device comprising a double bank well-defining structure, which method comprises: providing an electronic substrate; depositing a first insulating material on the substrate to form a first insulating layer; depositing a second insulating material on the first insulating layer to form a second insulating layer; removing a portion of the second insulating layer to expose a portion of the first insulating layer and form a second well-defining bank; depositing a resist on the second insulating layer and on a portion of the exposed first insulating layer; removing the portion of the first insulating layer not covered by the resist, to expose a portion of the electronic substrate and form a first well-defining bank within the second well-defining bank; and removing the resist. The method can provide devices with reduced leakage currents.

Abstract: There is provided a composite porous membrane comprising a porous membrane comprised of an organic polymeric compound, and a supporting porous membrane adjacent to the porous membrane, characterized in that the organic polymeric compound constituting the porous membrane penetrates in at least part of a surface adjacent to porous membrane of the supporting porous membrane, the porous membrane having specified opening ratio, average pore diameter, standard deviation of pore diameter, ratio of through pore, average membrane thickness, standard deviation of membrane thickness and internal structure, and that the supporting porous membrane has communicating pores of 0.5 D ?m or greater average pore diameter. Further, there are provided a blood filtration membrane comprising the composite porous membrane; a leukocyte removing filter unit comprising the composite porous membrane as a second filter; and, utilizing the composite porous membrane, a cell culturing diaphragm and method of cell culturing.

Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a first surface, a second surface, and a through hole that extends through the semiconductor substrate from the first surface to the second surface. An insulating layer covers the first surface and includes an opening at a location facing the through hole. An insulating film covers an inner wall of the through hole and an inner wall of the opening. A through electrode is formed in the through hole and the opening that are covered by the insulating film. A first connecting terminal is formed integrally with the through electrode to cover one end of the through electrode exposed from the insulating layer. The first connecting terminal has a larger size than the through electrode as viewed from above.

Abstract: Systems and methods for preparing films comprising metal using sequential ion implantation, and films formed using same, are provided herein. A structure prepared using ion implantation may include a substrate; an embedded structure having pre-selected characteristics; and a film within or adjacent to the embedded structure. The film comprises a metal having a perturbed arrangement arising from the presence of the embedded structure. The perturbed arrangement may include metal ions that coalesce into a substantially continuous, electrically conductive metal layer, or that undergo covalent bonding, whereas in the absence of the embedded structure the metal ions instead may be free to diffuse through the substrate. The embedded structure may control the diffusion of the metal through the substrate and/or the reaction of the metal within the substrate.

Abstract: The invention relates to a top-emissive organic light-emitting diode (OLED) (10) arranged to emit light having different emission colors, comprising a multi-layered structure provided with a first electrode, a second electrode and a functional layer enabling light emission disposed between the first electrode and the second electrode, wherein thickness (H1, H2) of the functional layer is modulated by allowing at least a portion of the functional layer to interact with a thickness modulator (5a, 5b, 5c), wherein the functional layer comprises a hole injection layer or the electron injection layer.

Abstract: The invention generally related to a method for preparing a layer of graphene directly on the surface of a semiconductor substrate. The method includes forming a carbon-containing layer on a front surface of a semiconductor substrate and depositing a metal film on the carbon layer. A thermal cycle degrades the carbon-containing layer, which forms graphene directly upon the semiconductor substrate upon cooling. In some embodiments, the carbon source is a carbon-containing gas, and the thermal cycle causes diffusion of carbon atoms into the metal film, which, upon cooling, segregate and precipitate into a layer of graphene directly on the semiconductor substrate.

Abstract: A semiconductor device includes a substrate configured with a plurality of conductive traces. The traces are configured to electrically couple to an integrated circuit (IC) die and at least one of the plurality of conductive traces includes first electrically conductive portions in a first electrically conductive layer of the substrate, second electrically conductive portions in a second electrically conductive layer of the substrate, and first electrically conductive connections between the first electrically conductive portions and the second electrically conductive portions. The first and second electrically conductive portions and the first electrically conductive connections form a continuous path along at least a portion of the at least one of the conductive traces. Time delay of conducting a signal along the at least one of the conductive traces is within a specified amount of time of time delay of conducting a signal along another one of the plurality of conductive traces.

Abstract: An organic electroluminescent member comprising: a positive electrode and a negative electrode on a substrate: multiple organic layers which include at least a positive hole transport layer, a light-emitting layer and an electron transport layer, and which are arranged between the positive electrode and the negative electrode; and an electron injection layer arranged between the electron transport layer and the negative electrode. The electron injection layer is formed from at least one selected from the group consisting of alkali metals and compounds containing alkali metals having a melting point of less than 90° C., and at least one selected from the group consisting of alkali metals, alkaline earth metals, compounds containing alkali metals, and compounds containing.

Abstract: Provided are a hole-injecting material for an organic electroluminescent device (organic EL device) exhibiting high luminous efficiency at a low voltage and having greatly improved driving stability, and an organic EL device using the material. The hole-injecting material for an organic EL device is selected from benzenehexacarboxylic acid anhydrides, benzenehexacarboxylic acid imides, or N-substituted benzenehexacarboxylic acid imides. Further, the organic EL device has at least one light-emitting layer and at least one hole-injecting layer between an anode and a cathode arranged opposite to each other, and includes the above-mentioned hole-injecting material for an organic EL device in the hole-injecting layer. The organic EL device may contain a hole-transporting material having an ionization potential (IP) of 6.0 eV or less in the hole-injecting layer or a layer adjacent to the hole-injecting layer.

Abstract: An integrated circuit device has a dual damascene structure including a lower via portion and an upper line portion. The lower via portion is formed in a polyimide layer, and the upper line portion is formed in an inter-metal dielectric (IMD) layer formed of USG or polyimide. A passivation layer is formed on the IMD layer, and a bond pad is formed overlying the passivation layer to electrically connect the upper line portion.

Abstract: A layer arrangement in accordance with various embodiments may include: a wafer; a passivation disposed over the wafer; a protection layer disposed over at least a surface of the passivation facing away from the wafer; and a mask layer disposed over at least a surface of the protection layer facing away from the wafer, wherein the protection layer includes a material that is selectively etchable to a material of the passivation, and wherein the mask layer includes a material that is selectively etchable to the material of the protection layer.

Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).

Abstract: A method comprises dispensing a first solvent on a semiconductor substrate; dispensing a first layer of a high-viscosity polymer on the first solvent; dispensing a second solvent on the first layer of high-viscosity polymer; and spinning the semiconductor substrate after dispensing the second solvent, so as to spread the high-viscosity polymer to a periphery of the semiconductor substrate.

Abstract: Disclosed herein is a Light Emitting Diode (LED) backlight unit without a Printed Circuit board (PCB). The LED backlight unit includes a chassis, insulating resin layer, and one or more light source modules. The insulating resin layer is formed on the chassis. The circuit patterns are formed on the insulating resin layer. The light source modules are mounted on the insulating resin layer and are electrically connected to the circuit patterns. The insulating resin layer has a thickness of 200 ?m or less, and is formed by laminating solid film insulating resin on the chassis or by applying liquid insulating resin to the chassis using a molding method employing spin coating or blade coating. Furthermore, the circuit patterns are formed by filling the engraved circuit patterns of the insulating resin layer with metal material.

Abstract: The light-emitting unit has at least a first light-emitting element, a second light-emitting element, and a separation layer. The separation layer has a leg portion and a stage portion which protrudes outside of a bottom surface of the leg portion over the leg portion. An upper electrode of the first light-emitting element is electrically connected to a lower electrode of the second light-emitting element in a region where the upper electrode and the lower electrode overlap with the stage portion of the separation layer. By providing the separation layer, the light-emitting unit can be formed without using a metal mask. The upper electrode can be a composite material including an organic compound and a metal oxide or a stacked layer of the composite material and a metal material or a light-transmitting conductive material.

Abstract: A large size organic light emitting diode (OLED) display and manufacturing method thereof are disclosed. In one embodiment, the method includes i) forming a display unit including a plurality of pixels on a substrate, ii) forming a getter layer, a bonding layer and a conductive contact layer around the display unit and iii) manufacturing a sealing member including a flexible polymer film and a metal layer formed on at least one side of the polymer film. The method may further include laminating the sealing member on the substrate using a roll lamination process such that the metal layer contacts the conductive contact layer and curing the contact layer and the conductive contact layer.

Abstract: An integrated circuit includes a substrate. A surface region of the substrate includes a contact pad region. A passivation layer stack includes at least one passivation layer. The passivation layer stack is formed over the surface region and adjacent to the contact pad region. An upper portion of the passivation layer stack is removed in, in a portion of the passivation layer stack proximate the contact pad region.

Abstract: A semiconductor device includes: a wiring board which includes a first face and a second face and in which a conductor pattern and a through part are provided; an electronic component which includes an electrode pad forming face where an electrode pad is formed and which is housed in the through part so that the electrode pad forming face is provided on the first face side; a seal resin which is provided in the through part and the electrode pad forming face, seals the electronic component and includes a first plane exposing a connection face of the electrode pad; and a wiring pattern which is provided in the first face of the wiring board and the first plane of the seal resin and electrically connects the connection face of the electrode pad with a first connected face of the conductor pattern, and which includes a pad part.

Abstract: There is disclosed a resist underlayer film composition, wherein the composition contains a polymer obtained by condensation of, at least, one or more compounds represented by the following general formula (1-1) and/or general formula (1-2), and one or more kinds of compounds and/or equivalent bodies thereof represented by the following general formula (2). There can be provided an underlayer film composition, especially for a trilayer resist process, that can form an underlayer film having reduced reflectance, (namely, an underlayer film having optimum n-value and k-value), excellent filling-up properties, high pattern-antibending properties, and not causing line fall or wiggling after etching especially in a high aspect line that is thinner than 60 nm, and a patterning process using the same.

Abstract: A multilayer structure comprises: a substrate; and, a plurality of polymerizable layers successively deposited on the substrate, with each successive layer having a greater dielectric polarizability than the preceding layer(s), so that each successive layer will absorb microwave energy preferentially to the preceding layer(s). In this way, successive layers can be cured without over-curing the preceding layers. The individual layers are preferably materials from a single chemical family (e.g., epoxies, polyimides, PBO, etc.) and have similar properties after curing. The dielectric polarizabilities may be adjusted by modifying such factors as chain endcap dipole strength, cross-linker dipole strength, promoter, solvent, and backbone type. The invention is particularly suitable for producing various polymer layers on silicon for electronic applications. An associated method is also disclosed.

Abstract: An organic light emitting display device constructed with an active layer of a thin film transistor formed on a substrate; a gate electrode including a first transparent conductive layer and a first metal layer formed on the active layer and a first insulating layer, source and drain electrodes including a second metal layer connected to the active layer through a contact hole formed in the second insulating layer, a third metal layer formed on the second metal layer, and a second transparent conductive layer formed on the third metal layer, formed on the gate electrode and a second insulating layer, a pixel electrode including the first transparent conductive layer, the third metal layer, and the second transparent conductive layer formed on the first insulating layer; and an intermediate layer disposed on the pixel electrode.

Abstract: Provided is a technique capable of improving the reliability of a semiconductor device having a slit made over a main surface of a semiconductor substrate, so as to surround each element formation region. In the technique, a second passivation film covers the side surface of an opening made to make the upper surface of a sixth-layer interconnection M6 used for bonding pads naked, and the inner walls (the side surfaces and the bottom surface) of a slit made to surround the circumference of a guard ring and made in a first passivation film, an insulating film for bonding, and an interlayer dielectric, so as to cause the bottom thereof not to penetrate through a barrier insulating film.

Abstract: A semiconductor composite film includes a semiconductor thin film layer containing an organic semiconductor material, an insulating thin film layer formed from a polymer material phase-separated from the organic semiconductor material in the film thickness direction, and a fine particle material dispersed in at least one of the semiconductor thin film layer and the insulating thin film layer.

Abstract: A method of manufacturing a thin film electronic device comprises applying a first plastic coating (PI-1) directly to a rigid carrier substrate (40) and forming thin film electronic elements (44) over the first plastic coating. A second plastic coating (46) is applied over the thin film electronic elements with electrodes (47) on top, with a portion lying directly over the associated electronic element, spaced by the second plastic coating. The rigid carrier substrate (40) is released from the first plastic coating, by a laser release process. This method enables traditional materials to be used as the base for the electronic element manufacture, for example thin film transistors. The second plastic coating can form part of the known field shielded pixel (FSP) technology.

Abstract: To reduce defects of a semiconductor device, such as defects in shape and characteristic due to external stress and electrostatic discharge. To provide a highly reliable semiconductor device. In addition, to increase manufacturing yield of a semiconductor device by reducing the above defects in the manufacturing process. The semiconductor device includes a semiconductor integrated circuit sandwiched by impact resistance layers against external stress and an impact diffusion layer diffusing the impact and a conductive layer covering the semiconductor integrated circuit. With the use of the conductive layer covering the semiconductor integrated circuit, electrostatic breakdown (malfunctions of the circuit or damages of a semiconductor element) due to electrostatic discharge of the semiconductor integrated circuit can be prevented.

Abstract: An organic light emitting diode display is disclosed. The organic light emitting diode display includes a plurality of subpixels that emit light of at least three colors, the plurality of subpixels each including a first electrode, an organic light emitting layer, and a second electrode. Each of the organic light emitting layers of at least two of the plurality of subpixels includes at least two electron transport layers. The organic light emitting layer of at least one of the plurality of subpixels includes at least one electron transport layer.

Abstract: Compounds comprising a ligand having a quinoline or isoquinoline moiety and a phenyl moiety, e.g., (iso)pq ligands. In particular, the ligand is further substituted with electron donating groups. The compounds may be used in organic light emitting devices, particularly devices with emission in the deep red part of the visible spectrum, to provide devices having improved properties.

Abstract: In order to improve the reliability of a semiconductor device having a fuse formed by a Damascene technique, a barrier insulating film and an inter-layer insulating film are deposited over a fourth-layer wiring and a fuse. The barrier insulating film is an insulating film for preventing the diffusion of Cu and composed of a SiCN film deposited by plasma CVD like the underlying barrier insulating film. The thickness of the barrier insulating film covering the fuse is larger than the thickness of the underlying barrier insulating film so as to improve the moisture resistance of the fuse.

Abstract: An organic light emitting device is disclosed. The organic light emitting device includes a substrate, a display positioned on the substrate, and a dummy pattern positioned at an edge of the display. The display includes a plurality of subpixels each including a first electrode, an emissive unit including at least an organic emissive layer, and a second electrode. The dummy pattern includes a dummy layer including the same formation material as that of at least one of a plurality of layers for forming the emissive unit.

Abstract: To prevent a point defect and a line defect in forming a light-emitting device, thereby improving the yield. A light-emitting element and a driver circuit of the light-emitting element, which are provided over different substrates, are electrically connected. That is, a light-emitting element and a driver circuit of the light-emitting element are formed over different substrates first, and then electrically connected. By providing a light-emitting element and a driver circuit of the light-emitting element over different substrates, the step of forming the light-emitting element and the step of forming the driver circuit of the light-emitting element can be performed separately. Therefore, degrees of freedom of each step can be increased, and the process can be flexibly changed. Further, steps (irregularities) on the surface for forming the light-emitting element can be reduced than in the conventional technique.

Abstract: The present invention has an object of providing a light emitting device including an OLED formed on a plastic substrate, which can prevent the degradation due to penetration of moisture or oxygen. On a plastic substrate, a plurality of films for preventing oxygen or moisture from penetrating into an organic light emitting layer in the OLED (hereinafter, referred to as barrier films) and a film having a smaller stress than that of the barrier films (hereinafter, referred to as a stress relaxing film), the film being interposed between the barrier films, are provided. Owing to a laminate structure of a plurality of barrier films, even if a crack occurs in one of the barrier films, the other barrier film(s) can effectively prevent moisture or oxygen from penetrating into the organic light emitting layer. Moreover, the stress relaxing film, which has a smaller stress than that of the barrier films, is interposed between the barrier films, thereby making it possible to reduce a stress of the entire sealing film.

Abstract: An alpha particle blocking structure and method of making the structure. The structure includes: a semiconductor substrate; a set of interlevel dielectric layers stacked from a lowermost interlevel dielectric layer closest to the substrate to a uppermost interlevel dielectric layer furthest from the substrate, each interlevel dielectric layer of the set of interlevel dielectric layers including electrically conductive wires, top surfaces of the wires substantially coplanar with top surfaces of corresponding interlevel dielectric layers; an electrically conductive tot final pad contacting a wire pad of the uppermost interlevel dielectric layer; an electrically conductive plating base layer contacting a top surface of the terminal pad; and a copper block on the plating base layer.

Abstract: A strengthened semiconductor die substrate and package are disclosed. The substrate may include contact fingers formed with nonlinear edges. Providing a nonlinear contour to the contact finger edges reduces the mechanical stress exerted on the semiconductor die which would otherwise occur with straight edges to the contact fingers. The substrate may additionally or alternatively include plating traces extending at an angle from the contact fingers. Extending at an angle, at least the ends of the plating traces at the edge of the substrate are covered beneath a lid in which the semiconductor package is encased. Thus, when in use with a host device, contact between the ends of the plating traces beneath the lid and contact pins of the host device is avoided.

Abstract: Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass transition temperature; and the later applied dielectric layers are laminated at temperatures lower than the glass transition temperatures of the earlier applied dielectric layers. In one embodiment, the glass transition temperatures of earlier applied dielectric films in a build-up interconnect are increased through a thermosetting process to exceed the temperature for laminating the later applied dielectric films. In one embodiment, a polyimide material is formed with embedded catalysts to promote cross-linking after a film of the polyimide material is laminated (e.g., through photo-chemical or thermal degradation of the encapsulant of the catalysts).

Abstract: A high-efficiency, white organic electroluminescent device has such a structure that its emission layer is obtained by laminating sub-emission layers of red, green, and blue, respectively. The green sub-emission layer contacting a hole transport layer has a delayed fluorescent material, and the red sub-emission layer has a phosphorescent light emitting material.

Abstract: There is provided an organic electroluminescence display includes a lower electrode formed on a substrate, a device separation film formed on the lower electrode, an organic compound layer formed on the device separation film and including a light emission layer, and an upper electrode formed on the organic compound layer, wherein the device separation film is a polyimide film having an imidation ratio in a range of 65% or more to less than 90%. The display is expected to have longer operating life.

Abstract: Provided are methods and apparatuses for depositing barrier layers for blocking diffusion of conductive materials from conductive lines into dielectric materials in integrated circuits. The barrier layer may contain copper. In some embodiments, the layers have conductivity sufficient for direct electroplating of conductive materials without needing intermediate seed layers. Such barrier layers may be used with circuits lines that are less than 65 nm wide and, in certain embodiments, less than 40 nm wide. The barrier layer may be passivated to form easily removable layers including sulfides, selenides, and/or tellurides of the materials in the layer.

Abstract: The present invention relates to an organic/inorganic hybrid thin film passivation layer comprising an organic polymer passivation layer prepared by a UV/ozone curing process and an inorganic thin film passivation layer for blocking moisture and oxygen transmission of an organic electronic device fabricated on a substrate and improving gas barrier property of a plastic substrate; and a fabrication method thereof. Since the organic/inorganic hybrid thin film passivation layer of the present invention converts the surface polarity of an organic polymer passivation layer into hydrophilic by using the UV/ozone curing process, it can improve the adhesion strength between the passivation layer interfaces, increase the light transmission rate due to surface planarization of the organic polymer passivation layer, and enhance gas barrier property by effectively blocking moisture and oxygen transmission.