Abstract: Integrated circuit packages that may be easily stacked one on top of the other are disclosed. The package includes a molded plastic body having metal-coated interconnection posts on both its upper and lower surfaces. An integrated circuit is mounted on the upper surface. Metal traces on the upper surface electrically connect each bonding pad on the integrated circuit to a one of a plurality of groups of four interconnection posts on the upper surface. Vias through the substrate electrically connect each group of four posts on the upper surface to an interconnection post on the lower surface of the package. Two or more packages can be stacked and electrically connected by wedging the lower posts of a top package between each group of four posts on the upper surface of a lower package. The lower posts of the lower package may be soldered to a conventional printed circuit board, or may be mounted on a mounting substrate that also has corresponding groups of four interconnection posts.

Abstract: A chip structure comprises a substrate, a first built-up layer, a passivation layer and a second built-up layer. The substrate includes many electric devices placed on a surface of the substrate. The first built-up layer is located on the substrate. The first built-up layer is provided with a first dielectric body and a first interconnection scheme, wherein the first interconnection scheme interlaces inside the first dielectric body and is electrically connected to the electric devices. The first interconnection scheme is constructed from first metal layers and plugs, wherein the neighboring first metal layers are electrically connected through the plugs. The passivation layer is disposed on the first built-up layer and is provided with openings exposing the first interconnection scheme. The second built-up layer is formed on the passivation layer.

Abstract: The semiconductor device comprising a lower conductive layer (11) and an upper conductive layer (12) which are formed via an interlayer insulator (20) on a substrate (1), wherein the interlayer insulator (20) has a stack structure of an organic resin layer (21) formed on the lower conductive layer (11) and one or more high water-resistant insulating film (22) having a specific Si content formed on the organic resin layer (21). Even when the interlayer insulator realized by an organic resin insulating film of a low dielectric constant is used, characteristic and realizability is prevented from being deteriorated.

Abstract: An integrated circuit device with a low stress, thin film, protective overcoat having enhanced adhesion both to polymeric materials used in packaging semiconductor devices, and within the passivating film layers, including the following sequence of materials deposited by PECVD processing: a thin film of silicon dioxide, a layer of silicon nitride, oxy-nitride or silicon carbide, and a very thin topmost layer of silicon oxide.

Abstract: The present invention relates to an insulator as an insulating layer in a laminate which can inhibit dusting at the time of use, more particularly an electronic circuit component to which the insulator has been applied, particularly a wireless suspension. The insulator comprises a laminate of one or more insulation unit layers etchable by a wet process, the insulator having been subjected to plasma treatment after wet etching. The insulator exists mainly as an insulating layer in a laminate having a layer construction of first inorganic material layer—insulating layer—second inorganic material layer or a layer construction of inorganic material layer—insulating layer, and at least a part of the inorganic material layer has been removed to expose the insulating layer.

Abstract: Cavities of submicron dimension are in a cavity layer of a semiconductor device. For that purpose, processing material is deposited on ridges of a working layer that is structured from ridges and trenches. The processing material is polymerized and the polymerizing processing material expands over the trenches. Upon covering the trenches, the submicron cavities are formed.

Abstract: Reducing the manufacturing cost of an EL display device and an electronic device furnished with the EL display device is taken as an objective. A textured structure in which projecting portions are formed on the surface of a cathode is used. External stray light is diffusely (irregularly) reflected by the action of the projecting portions when reflected by the surface of the cathode, and therefore a defect in which the face of an observer or the surrounding scenery is reflected in the surface of the cathode can be prevented. This can be completed without using a conventionally necessary high price circular polarizing film, and therefore it is possible to reduce the cost of manufacturing the EL display device.

Abstract: A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are a less attractive combination than gold, silver, or copper wires combined with polymer-based insulation, which promise both lower electrical resistance and capacitance and thus faster, more efficient circuits. Unfortunately, conventional etch-base techniques are ineffective with gold, silver, or copper, and conventional polymer formation promote reactions with metals that undermine the insulative properties of polymer-based insulations. Accordingly, the inventor devised methods which use a liftoff procedure to avoid etching problems and a non-acid-polymeric precursor and non-oxidizing cure procedure to preserve the insulative properties of the polymeric insulator. The resulting interconnective structures facilitate integrated circuits with better speed and efficiency.

Abstract: An integrated circuit, comprising: a semiconductor substrate, a plurality of last metal conductors disposed above said substrate, a bottom metallic layer disposed on said last metal conductors, a top metallic layer, and an alpha absorber disposed between said bottom and top metallic layers, said alpha absorber consisting essentially of a high-purity metal which is an alpha-particle absorber. The metal is, for example, of Ta, W, Re, Os or Ir.

Abstract: There are included a semiconductor substrate provided with a desirable element region, an electrode pad formed to come in contact with a surface of the semiconductor substrate or a wiring layer provided on the surface of the semiconductor substrate, a bonding pad formed on a surface of the electrode pad through an intermediate layer, and a resin insulating film for covering a peripheral edge of the bonding pad such that an interface of the bonding pad and the intermediate layer is not exposed to a side wall.

Abstract: The invention is a semiconductor device and method of fabricating the device. The device includes a semiconductor substrate with an active region, and a low dielectric constant insulating layer formed over the substrate. An additional insulating layer is formed over the low dielectric constant layer by a low temperature deposition, such as ion beam assistance deposition. A metal layer can then be formed over the additional layer using lift-off techniques. The metal layer can be patterned to form a bond pad which may be displaced from the area over the active region. Wire bonds can be made on the bond pad using ultrasonic energy.

Abstract: Porous dielectric materials having low dielectric constants, ≧30% porosity and a closed cell pore structure are disclosed along with methods of preparing the materials. Such materials are particularly suitable for use in the manufacture of electronic devices.

Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components.

Abstract: A novel technology is provided for encapsulating electronics for use in harsh media applications, such as biomedical implants. The present invention includes electroplating a metal film on top of an insulating layer to hermetically seal an electronic system, microstructure, or micro device.

Abstract: A conductive system and a method of forming an insulator for use in the conductive system is disclosed. The conductive system comprises a foamed polymer layer on a substrate. The foamed polymer layer has a surface that is hydrophobic, and a plurality of conductive structures are embedded in the foamed polymer layer. An insulator is formed by forming a polymer layer having a thickness on a substrate. The polymer layer is foamed to form a foamed polymer layer having a surface and a foamed polymer layer thickness, which is greater than the polymer layer thickness. The surface of the foamed polymer layer is treated to make the surface hydrophobic.

Abstract: Resist developers can attack some advanced dielectric materials such as silsesquioxane materials which can be used as an insulator between a surface of an integrated circuit chip and wiring layers formed on the surface of the dielectric material. By performing a resist stripping or etching process in which a reactant material is supplied externally or liberated from the dielectric material, an extremely thin surface protective covering of an intermediate material may be formed which is impervious to resist developers or any of a plurality of other materials which may damage the flowable oxide material. A dual Damascene process for forming robust connections and vias to the chip can thus be made compatible with advanced dielectrics having particularly low dielectric constants to minimize conductor capacitance and support fast signal propagation and noise immunity even where conductors are closely spaced to each other.

Abstract: A semiconductor device including a semiconductor substrate, an insulating layer formed on the substrate, a dielectric organic layer formed on the insulating layer and having a dielectric constant of not more than 3.0, and an interconnection layer in contact with the insulating layer in the dielectric organic layer, wherein the upper surface of the interconnection layer is formed higher than the upper surface of the dielectric organic layer, and a method of manufacture thereof.

Abstract: A resin material having low dielectric constant is used as an inter-layer insulating film and its bottom surface is contacted with a silicon oxide film across the whole surface thereof. Thereby, the surface may be flattened and capacity produced between a thin film transistor and an pixel electrode may be reduced. Further, it allows to avoid a problem that impurity ions and moisture infiltrate into the lower surface of the resin material, thus degrading the reliability of whole semiconductor device.

Abstract: An interconnect structure including a patterned multilayer of spun-on dielectrics as well as methods for manufacturing the same are provided. The interconnect structure includes a patterned multilayer of spun-on dielectrics formed on a surface of a substrate. The patterned multilayer of spun-on dielectrics is composed of a bottom low-k dielectric, a buried etch stop layer, and a top low-k dielectric, wherein the bottom and top low-k dielectrics have a first composition, the said buried etch stop layer has a second composition which is different from the first composition and the buried etch stop layer is covalently bonded to said top and bottom low-k dielectrics. The interconnect structure further includes a polish stop layer formed on the patterned multilayer of spun-on dielectrics; and metal conductive regions formed within the patterned multilayer of spun-on dielectrics.

Abstract: A resin material having low dielectric constant is used as an inter-layer insulating film and its bottom surface is contacted with a silicon oxide film across the whole surface thereof. Thereby, the surface may be flattened and capacity produced between a thin film transistor and an pixel electrode may be reduced. Further, it allows to avoid a problem that impurity ions and moisture infiltrate into the lower surface of the resin material, thus degrading the reliability of whole semiconductor device.

Abstract: The invention is a semiconductor device and method of fabricating the device. The device includes a semiconductor substrate with an active region, and a low dielectric constant insulating layer formed over the substrate. An additional insulating layer is formed over the low dielectric constant layer by a low temperature deposition, such as ion beam assistance deposition. A metal layer can then be formed over the additional layer using lift-off techniques. The metal layer can be patterned to form a bond pad which may be displaced from the area over the active region. Wire bonds can be made on the bond pad using ultrasonic energy.

Abstract: The present invention is directed toward the formation of implanted thermally and electrically conductive structures in a dielectric. An electrically conductive structure, such as an interconnect is formed through ion implantation into several levels within a dielectric layer to penetrate into an electrically conductive region beneath the dielectric layer, such as a semiconductor substrate. Ion implantation continues in discreet, overlapping implantations of the ions from the electrical conductive region up to the top of the dielectric layer so as to form a continuous interconnect. Structural qualities achieved by the method of the present invention include a low interconnect-conductive region resistivity and a low thermal-cycle stress between the interconnect and the dielectric layer in which the interconnect has been implanted.

Abstract: The present invention provides polymeric materials that can be used as a moisture/ion barrier layer for inhibiting the penetration of moisture and/or ions for coming into contact with the metal wiring found in chip level interconnects. The present invention also provides a means to protect the chip backside from being contaminated by metal atoms or metal ions which are capable of forming mobile silicides, which can migrate to the active sites of the semiconductor and destroy them. The present invention further provides methods of forming such polymeric barrier layers on at least one surface of an interconnect structure.

Abstract: A polyamic ester prepared by partially substituting hydrogen atoms of carboxylic groups of a polyamic acid with acid-dissociable groups, the polyamic ester comprising one or more repeating units represented by Formula 1, and each of at least one terminal of the polyamic ester molecule terminates with the same or different reactive end-capping monomer: 1

Abstract: An interlayer dielectric for preventing Cu ion migration in semiconductor structure containing a Cu region is provided. The interlayer dielectric of the present invention comprises a dielectric material that has a dielectric constant of 3.0 or less and an additive which is highly-capable of binding Cu ions, yet is soluble in the dielectric material. The presence of the additive in the low k dielectric allows for the elimination of conventional inorganic barrier materials such as SiO2 or Si3N4.

Abstract: The invention relates to cured dielectric films and a process for their manufacture which are useful in the production of integrated circuits. Dual layered dielectric films are produced in which a lower layer comprises a non-silicon containing organic polymer and an upper layer comprises an organic, silicon containing polymer. Such films are useful in the manufacture of microelectronic devices such as integrated circuits (IC's). In one aspect the upper layer silicon containing polymer has less than 40 Mole percent carbon containing substituents, and in another aspect it has at least approximately 40 Mole percent carbon containing substituents.

Abstract: A manufacturing method for a semiconductor device, wherein a polyimide-based resin layer is covered with a P-CVD oxide silicon film or the like before it is subjected to degassing process in order to prevent blisters or cracks of a cover film of a semiconductor device which has the polyimide-based resin layer as an interlayer insulating film. This makes it possible to take the semiconductor device out in open air after the degassing process and to prevent the dispersion of reaction products resulting from amidation during the degassing process.

Abstract: An interlayer dielectric for preventing Cu ion migration in semiconductor structure containing a Cu region is provided. The interlayer dielectric of the present invention comprises a dielectric material that has a dielectric constant of 3.0 or less and an additive which is highly-capable of binding Cu ions, yet is soluble in the dielectric material. The presence of the additive in the low k dielectric allows for the elimination of conventional inorganic barrier materials such as SiO2 or Si3N4.

Abstract: “”-shaped slits and linking portions are previously provided so as to surround a semiconductor chip-mounting region in a TAB tape. A semiconductor chip is applied onto the semiconductor chip-mounting region. The semiconductor chip in its electrode pad is connected by bonding to the TAB tape in its inner lead. The bonded connection is subjected to plastic molding. Solder balls are provided on the backside of the TAB tape in its portion corresponding to the semiconductor chip-mounting portion. Thereafter, the package portion is cut off at the cutting position in the linking portion of the slits. By virtue of the above constitution, highly reliable BGA type semiconductor devices can be produced while reducing the thickness and reducing the size.

Abstract: A composite containing nano magnetic particles is provided. The composite includes nano magnetic particles in a dielectric matrix. The matrix is made of an inorganic material such as silica, alumina or hydrosilsesquioxane, or an organic material such as polyimide, polymethyl methacrylate (PMMA) or methyl silsesquioxane. The nano magnetic particles consist of (y-Fe2O3), chromium oxide (CrO2), europium oxide (EuO), NiZn-ferrite, MnZn-ferrite, Yittrium-iron garnet or indium (In).

Abstract: An improved dual damascene structure, and process for manufacturing it, are described in which the via hole is first lined with a layer of silicon nitride prior to adding the diffusion barrier and copper. This allows use of a barrier layer that is thinner than normal (since the silicon nitride liner is an effective diffusion barrier) so that more copper may be included in the via hole, resulting in an improved conductance of the via. A key feature of the process that is used to make the structure is the careful control of the etching process. In particular, the relative selectivity of the etch between silicon oxide and silicon nitride must be carefully adjusted.

Abstract: A semiconductor device assembly has a lead frame and a semiconductor device configured to be attached to each other. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor device is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.

Abstract: The invention encompasses methods of forming insulating materials between conductive elements. In one aspect, the invention includes a method of forming a material adjacent a conductive electrical component comprising: a) partially vaporizing a mass to form a matrix adjacent the conductive electrical component, the matrix having at least one void within it. In another aspect, the invention includes a method of forming a material between a pair of conductive electrical components comprising the following steps: a) forming a pair of conductive electrical components within a mass and separated by an expanse of the mass; b) forming at least one support member within the expanse of the mass, the support member not comprising a conductive interconnect; and c) vaporizing the expanse of the mass to a degree effective to form at least one void between the support member and each of the pair of conductive electrical components.

Abstract: A semiconductor device assembly has a lead frame and a semiconductor device configured to be attached to each other. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor device is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.

Abstract: A method of manufacturing a semiconductor package including the steps of adhering inner leads to a semiconductor chip surface via an insulating adhesive, forming an insulating layer on the semiconductor chip and upper surfaces of the inner leads such that bonding pads formed on the semiconductor chip and portions of the inner leads are exposed through an opening, forming a conductive layer in the opening to electrically connect the bonding pads to the inner leads, and forming a semiconductor package by molding the semiconductor chip, the inner leads, the insulating layer, and the conductive layer with a molding material.

Abstract: An optical semiconductor component includes a semiconductor substrate (120) and a packaging material (140) located over the semiconductor substrate. The packaging material includes an optically transparent cycloaliphatic polymer (142, 242, 400, 600). A method of manufacturing the component includes nixing a monomer (300, 500) of the polymer with a catalyst to form the packaging material, filtering the packaging material, applying the packaging material, and curing the packaging material.

Abstract: There is a problem in that, in a liquid crystal display panel in which a color filter is formed on an opposing substrate, it is necessary to assemble an element substrate and the opposing substrate by extremely high precision position alignment, and when this precision is low, the aperture ratio decreases and the display becomes darker. With the present invention, red color filters (R) are formed on driving circuits (402, 403), peripheral circuits, and a color filter (405d) for protecting a pixel TFT portion (407) is formed for each pixel.

Abstract: A first HSQ film composed of a Si—O-based film with a low dielectric constant is formed on a first wiring via a protective insulation film, and the surface of this first HSQ film is reformed to form a first SRO layer. Then, a second HSQ film is formed on this first SRO layer, and the surface of the second HSQ film is reformed to form a second SRO layer. Next, a via-hole is formed within a predetermined region, which reaches the protective insulation film on the first wiring. Then, wiring trenches forming a second wiring are formed within predetermined regions of the second HSQ film and the second SRO film while using the first SRO film as an etching stopper film. Thereafter, the protective insulation film at the bottom of the via-hole is etched and removed, and the wiring trenches and the via-hole are embedded with a conductive film. Then, the conductive film on the second SRO layer is removed while using the second SRO layer as a CMP stopper film.

Abstract: A semiconductor device comprises a semiconductor substrate having an area in which a circuit element is formed; and a passivation film formed on an upper surface of the semiconductor substrate,

Abstract: A novel dielectric composition is provided that is useful in the manufacture of integrated circuit devices and integrated circuit packaging devices. The dielectric composition is prepared by imidizing and curing an oligomeric precursor compound comprised of a central polybenzoxazole, polybenzothiazole, polyamic acid or polyamic acid ester segment end-capped at each terminus with an aryl-substituted acetylene moiety such as an ortho-bis(arylethynyl)aryl group, e.g., 3,4-bis(phenylethynyl)phenyl. Integrated circuit devices, integrated circuit packaging devices, and methods of synthesis and manufacture are provided as well.

Abstract: A method of forming a dual damascene structure in a semiconductor device arrangement forms a first low k dielectric material over an underlying metal interconnect layer, such as a copper interconnect layer. A second low k dielectric layer is formed on the first low k dielectric layer. A via is etched into the first low k dielectric layer, and a trench is then etched into the second low k dielectric layer. The first and second low k dielectric materials are different from one another so that they have different sensitivity to at least one etchant chemistry. Further etching of the first dielectric layer is prevented during the etching of the trench in the second dielectric layer by employing an etch chemistry that etches only the second low k dielectric material and not the first low k dielectric material.

Abstract: An array substrate typically used in a liquid crystal display device includes inter-layer insulating films thick enough to prevent step-off breakage of conductive layers at contact holes while promising a reliability. Thick inter-layer insulating films are made by stacking a film made of an inorganic material, such as silicon nitride or silicon oxide, having a low moisture permeability and thereby promising a reliability of the liquid crystal display device, and a film made of an organic material, such as acrylic resin, that can be readily stacked thick so that the inner wall of the contact hole is gently sloped with respect to the substrate surface to thereby prevent step-off breakage of a conductive layer as thin as 100 nm or less.

Abstract: This invention improves TFT characteristics by making an interface between an active layer, especially a region forming a channel formation region and an insulating film excellent, and provides a semiconductor device provided with a semiconductor circuit made of a semiconductor element having uniform characteristics and a method of fabricating the same. In order to achieve the object, a gate wiring line is formed on a substrate or an under film, a gate insulating film, an initial semiconductor film, and an insulating film are formed into a laminate without exposing them to the atmosphere, and after the initial semiconductor film is crystallized by irradiation of infrared light or ultraviolet light (laser light) through the insulating film, patterning is carried out to obtain an active layer and a protection film each having a desired shape, and then, a resist mask is used to fabricate the semiconductor device provided with an LDD structure.

Abstract: A resin material having a small relative dielectric constant is used as a layer insulation film 114. The resin material has a flat surface. A black matrix or masking film for thin film transistors is formed thereon using a metal material. Such a configuration prevents the problem of a capacity generated between the masking film and a thin film transistor.

Abstract: A method of manufacturing a PIN (positive-intrinsic-negative) diode structure includes depositing an insulation or dielectric layer over the bottom PIN diode electrodes, prior to depositing the PIN semiconductor layers. The insulation layer results in a PIN diode structure with reduced leakage current, reduced RIE (reactive ion etching) chamber contamination, the reduction or elimination of post RIE processing, improved yields, and/or expands the potential materials that may be used for the bottom electrode. A corresponding PIN diode structure is also disclosed. The resulting PIN diode structures may be used in, for example, LCD (liquid crystal display) and solid state imager applications.

Abstract: A typical integrated circuit interconnects millions of microscopic transistors and resistors with aluminum wires buried in silicon-dioxide insulation. Yet, aluminum wires and silicon-dioxide insulation are a less attractive combination than gold, silver, or copper wires combined with polymer-based insulation, which promise both lower electrical resistance and capacitance and thus faster, more efficient circuits. Unfortunately, conventional etch-based techniques are ineffective with gold, silver, or copper, and conventional polymer formation promote reactions with metals that undermine the insulative properties of polymer-based insulations. Accordingly, the inventor devised methods which use a liftoff procedure to avoid etching problems and a non-acid-polymeric precursor and non-oxidizing cure procedure to preserve the insulative properties of the polymeric insulator. The resulting interconnective structures facilitate integrated circuits with better speed and efficiency.

Abstract: The present invention relates to electro optical devices with a reduced filter thinning on the edge pixels and a method for reducing the thinning of filter layers on the pixels closest to the edge of an electro optical device such as a photosensitive chip, as would be used, for example, in a full-color digital copier or scanner. A semiconductor wafer includes a main surface defining a plurality of chip areas and tab regions separated by grooves, wherein the chip areas include inner photosites, outer photosites and bonding pads. A plurality of dams are deposited over the main surface in the tab regions, and a clear layer is deposited over the main surface exclusive of the bonding pads. Alternatively, a clear layer is deposited over the main surface exclusive of the bonding pads, and a plurality of tabs is then deposited in the tab regions on the main surface.

Abstract: A bonded wafer in which silicon wafers and an amorphous heat fusion bonding polyimide are used, a process for producing the same, and a substrate which is prepared by variously processing the bonded wafer.

Abstract: A resin material having a small relative dielectric constant is used as a layer insulation film 114. The resin material has a flat surface. A black matrix or masking film for thin film transistors is formed thereon using a metal material. Such a configuration prevents the problem of a capacity generated between the masking film and a thin film transistor.

Abstract: A trench isolation structure is provided which includes a dielectric material having a relatively low dielectric constant, K, that is approximately less than 3.8. The capacitance between active areas separated by the trench isolation structure, being directly proportional to K, is thus reduced. As a result, the lateral width of the isolation structure may be decreased without significantly increasing the capacitance between those active areas. In an embodiment, a fabrication process for the trench isolation structure may include a trench is etched within a semiconductor substrate upon which a masking layer is formed. An oxide liner is thermally grown upon the sidewalls and base of the trench. A layer of low K dielectric material is deposited across the oxide liner. A fill oxide is then formed upon the layer of dielectric material. The resulting trench isolation structure includes a low K dielectric material interposed between an oxide liner and a fill oxide.