Non-single Crystal, Or Recrystallized, Material With Specified Crystal Structure (e.g., Specified Crystal Size Or Orientation) Patents (Class 257/64)
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Patent number: 7192785Abstract: The present invention provides a water-soluble luminescent quantum dot, a biomolecular conjugate thereof and a composition comprising such a quantum dot or conjugate. Additionally, the present invention provides a method of obtaining a luminescent quantum dot, a method of making a biomolecular conjugate thereof, and methods of using a biomolecular conjugate for ultrasensitive nonisotopic detection in vitro and in vivo.Type: GrantFiled: August 27, 2002Date of Patent: March 20, 2007Assignee: Indiana University Research and Technology CorporationInventors: Shuming Nie, Warren C. W. Chan, Stephen Emory
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Patent number: 7187005Abstract: A flat panel display lowering an on-current of a driving thin film transistor (TFT), maintaining high switching properties of a switching TFT, maintaining uniform brightness using the driving TFT, and maintaining a life span of a light emitting device while the same voltages are applied to the switching TFT and the driving TFT without changing a size of an active layer. The flat panel display has a light emitting device, a switching thin film transistor including a semiconductor active layer having at least a channel area for transferring a data signal to the light emitting device, and a driving thin film transistor including a semiconductor active layer having at least a channel area for driving the light emitting device so that a predetermined current flows through the light emitting device according to the data signal, the channel areas of the switching TFT and the driving TFT having different directions of current flow.Type: GrantFiled: December 4, 2003Date of Patent: March 6, 2007Assignee: Samsung SDI Co., Ltd.Inventors: Jae-Bon Koo, Ji-Yong Park, Hye-Dong Kim, Ul-Ho Lee
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Patent number: 7183585Abstract: To provide a semiconductor device that excels in the manufacturing efficiency and device reliability, and a method for the manufacture thereof. The side of a device is composed of scribed grooves 13 and a cleavage plane 100.Type: GrantFiled: October 28, 2004Date of Patent: February 27, 2007Assignee: NEC CorporationInventor: Masaru Kuramoto
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Patent number: 7183571Abstract: A polycrystalline silicon thin film to be used in display devices, the thin film having adjacent primary grain boundaries that are not parallel to each other, wherein an area surrounded by the primary grain boundaries is larger than 1 ?m2, a fabrication method of the polycrystalline silicon thin film, and a thin film transistor fabricated using the method.Type: GrantFiled: October 28, 2003Date of Patent: February 27, 2007Assignee: Samsung SDI Co., Ltd.Inventors: Ji Yong Park, Hye Hyang Park
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Patent number: 7164152Abstract: A crystalline film includes a first crystalline region having a first film thickness and a first crystalline grain structure; and a second crystalline region having a second film thickness and a second crystalline grain structure. The first film thickness is greater than the second film thickness and the first and second film thicknesses are selected to provide a crystalline region having the degree and orientation of crystallization that is desired for a device component.Type: GrantFiled: January 9, 2004Date of Patent: January 16, 2007Assignee: The Trustees of Columbia University in the City of New YorkInventor: James Im
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Patent number: 7161180Abstract: Disclosed is a flat panel display capable of improving a white balance by making channel regions of transistors of R, G and B unit pixels with different current mobilities. The flat panel display includes a plurality of pixels, each of the pixels including R, G and B unit pixels to embody red (R), green (G) and blue (B) colors, respectively, and each of the unit pixels including at least one transistor. Channel layers of the transistors of at least two unit pixels among the R, G and B unit pixels have different current mobilities from one another. The R, G, B unit pixels includes transistors and the transistor of at least one unit pixel among the R, G and B unit pixels includes the channel layer made of silicon layers of different film qualities.Type: GrantFiled: April 14, 2004Date of Patent: January 9, 2007Assignee: Samsung SDI Co., Ltd.Inventors: Jae-Bon Koo, Ji-Yong Park, Sang-Il Park, Deuk-Jong Kim, Ul-Ho Lee, Jin-Soo Kim, Jin-Woung Jung, Chang-Gyu Lee
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Patent number: 7157737Abstract: Single-crystal devices and a method for forming semiconductor film single-crystal domains are provided. The method comprises: forming a substrate, such as glass or Si; forming an insulator film overlying the substrate; forming a single-crystal seed overlying the substrate and insulator; forming an amorphous film overlying the seed; annealing the amorphous film; and, forming a single-crystal domain in the film responsive to the single-crystal seed. The annealing technique can be (conventional) laser annealing, a laser induced lateral growth (LiLAC) process, or conventional furnace annealing. In some aspects, forming a single-crystal seed includes forming a nanowire or a self assembled monolayer (SAM). For example, a Si nanowire can be formed having a crystallographic orientation of <110> or <100>. When, the seed has a <100> crystallographic orientation, then an n-type TFT can be formed.Type: GrantFiled: April 7, 2005Date of Patent: January 2, 2007Assignee: Sharp Laboratories of America, Inc.Inventors: Apostolos T. Voutsas, John W. Hartzell
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Patent number: 7148507Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.Type: GrantFiled: December 17, 2004Date of Patent: December 12, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo Isobe, Shunpei Yamazaki, Koji Dairiki, Hiroshi Shibata, Chiho Kokubo, Tatsuya Arao, Masahiko Hayakawa, Hidekazu Miyairi, Akihisa Shimomura, Koichiro Tanaka, Mai Akiba
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Patent number: 7145175Abstract: According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which variation between semiconductor devices is small can be provided, and a semiconductor integrated circuit having high conformance can be provided. The invention is characterized in that, in a part or whole of thin film transistors which configure an analog circuit such as a current mirror circuit, a differential amplifier circuit, or an operational amplifier, in which high conformance is required for semiconductor devices included therein, channel forming regions have crystalline semiconductor films on the same line. High conformance can be expected for an analog circuit which has the crystalline semiconductor films on the same line formed using the invention as the channel forming regions of the thin film transistors.Type: GrantFiled: September 7, 2004Date of Patent: December 5, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kiyoshi Kato, Tomoaki Atsumi, Atsuo Isobe
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Patent number: 7129522Abstract: Protrusions called ridges are formed on the surface of a crystalline semiconductor film formed by a laser crystallization method or the like. A heat absorbing layer are formed below a semiconductor film. When the semiconductor film is crystallized by laser, a temperature difference is produced between a semiconductor film 1010 positioned above a heat absorbing layer 1011 and a semiconductor film 1013 of the other region to produce a difference in thermal expansion at the boundary of the outside end 1015 of the heat absorbing layer. This difference produces a strain to form a surface wave. The surface wave starting at the outer periphery of the heat absorbing layer is formed in the vicinity of the heat absorbing layer. When the semiconductor layer is solidified after it is melted, the protrusions of the surface wave remain as protrusions after the semiconductor film is solidified.Type: GrantFiled: December 18, 2003Date of Patent: October 31, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Setsuo Nakajima, Ritsuko Kawasaki
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Patent number: 7119365Abstract: A polycrystalline Si thin film and a single crystal Si thin film are formed on an SiO2 film deposited on an insulating substrate. A polycrystalline Si layer is grown by thermally crystallizing an amorphous Si thin film so as to form the polycrystalline Si thin film. A single crystal Si substrate, having (a) an SiO2 film thereon and (b) a hydrogen ion implantation portion therein, is bonded to an area of the polycrystalline Si thin film that has been subjected to etching removal, and is subjected to a heating process. Then, the single crystal Si substrate is divided at the hydrogen ion implantation portion in an exfoliating manner, so as to form the single crystal Si thin film. As a result, it is possible to provide a large-size semiconductor device, having the single crystal Si thin film, whose property is stable, at a low cost.Type: GrantFiled: March 4, 2003Date of Patent: October 10, 2006Assignee: Sharp Kabushiki KaishaInventors: Yutaka Takafuji, Takashi Itoga
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Patent number: 7115903Abstract: An insulating film having depressions and projections are formed on a substrate. A semiconductor film is formed on the insulating film. Thus, for crystallization by using laser light, a part where stress concentrates is selectively formed in the semiconductor film. More specifically, stripe or rectangular depressions and projections are provided in the semiconductor film. Then, continuous-wave laser light is irradiated along the stripe depressions and projections formed in the semiconductor film or in a direction of a major axis or minor axis of the rectangle.Type: GrantFiled: December 27, 2002Date of Patent: October 3, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo Isobe, Koji Dairiki, Hiroshi Shibata, Chiho Kokubo, Tatsuya Arao, Masahiko Hayakawa, Hidekazu Miyairi, Akihisa Shimomura, Koichiro Tanaka, Shunpei Yamazaki, Mai Akiba
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Patent number: 7105392Abstract: An objective is to provide a method of manufacturing a semiconductor device, and a semiconductor device manufactured by using the manufacturing method, in which a laser crystallization method is used that is capable of preventing the formation of grain boundaries in TFT channel formation regions, and is capable of preventing conspicuous drops in TFT mobility, reduction in the ON current, and increases in the OFF current, all due to grain boundaries. Depressions and projections with stripe shape or rectangular shape are formed. Continuous wave laser light is then irradiated to a semiconductor film formed on an insulating film along the depressions and projections with stripe shape of the insulating film, or along a longitudinal axis direction or a transverse axis direction of the rectangular shape. Note that although it is most preferable to use continuous wave laser light at this point, pulse wave laser light may also be used.Type: GrantFiled: January 28, 2003Date of Patent: September 12, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo Isobe, Shunpei Yamazaki, Chiho Kokubo, Koichiro Tanaka, Akihisa Shimomura, Tatsuya Arao, Hidekazu Miyairi, Mai Akiba
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Patent number: 7102166Abstract: A hybrid orientation semiconductor structure and method of forming the same. The structure includes (a) a semiconductor substrate comprising a first semiconductor material having a first lattice orientation; (b) a back gate region on the semiconductor substrate; (c) a back gate dielectric layer on the back gate region; (d) a semiconductor region on the back gate dielectric layer, wherein the semiconductor region is electrically insulated from the back gate region by the back gate dielectric layer, and wherein the semiconductor region comprises a second semiconductor material having a second lattice orientation different from the first lattice orientation; and (e) a field effect transistor (FET) formed on the semiconductor region, wherein changing a voltage potential applied to the back gate region causes a change in a threshold voltage of the FET.Type: GrantFiled: April 21, 2005Date of Patent: September 5, 2006Assignee: International Business Machines CorporationInventors: Andres Bryant, William F. Clark, Jr., Edward J. Nowak
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Patent number: 7098487Abstract: There is provided a GaN single crystal at least about 2 millimeters in diameter, with a dislocation density less than about 104 cm?1, and having no tilt boundaries. A method of forming a GaN single crystal is also disclosed. The method includes providing a nucleation center, a GaN source material, and a GaN solvent in a chamber. The chamber is pressurized. First and second temperature distributions are generated in the chamber such that the solvent is supersaturated in the nucleation region of the chamber. The first and second temperature distributions have different temperature gradients within the chamber.Type: GrantFiled: December 27, 2002Date of Patent: August 29, 2006Assignee: General Electric CompanyInventors: Mark Philip D'Evelyn, Dong-Sil Park, Steven LeBoeuf, Larry Rowland, Kristi Narang, Huicong Hong, Peter M. Sandvik
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Patent number: 7091519Abstract: A semiconductor device includes a substrate having an insulating film on its surface, and ac active layer made of a semiconductive thin film on the substrate surface. The thin film contains a mono-domain region formed of multiple columnar and/or needle-like crystals parallel to the substrate surface without including crystal boundaries therein, allowing the active layer to consist of the mono-domain region only. The insulating film underlying the active layer has a specific surface configuration of an intended pattern in profile, including projections or recesses. To fabricate the active layer, form a silicon oxide film by sputtering on the substrate. Pattern the silicon oxide film providing the surface configuration. Form an amorphous silicon film by low pressure CVD on the silicon oxide film. Retain in the silicon oxide film and/or the amorphous silicon film certain metallic element for acceleration of silicon film to a crystalline silicon film.Type: GrantFiled: November 27, 2001Date of Patent: August 15, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama, Akiharu Miyanaga, Takeshi Fukunaga
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Patent number: 7045818Abstract: In a fabrication process of a semiconductor device for use in a TFT liquid crystal display system, before the start of crystallizing amorphous silicon (a-Si), dehydrogenation annealing is carried out to not only decrease the density of hydrogen in the p-Si film (13) to 5×1020 atoms/cm3 at most but also to prevent crystallization of the a-Si film (13) being obstructed due to possible excessive hydrogen remaining in the film. With the p-Si film (13) covered with an interlayer insulation film (15) in the form of a plasma nitride film, annealing is then carried out in nitrogen atmosphere at a temperature of 350° C. to 400° C. for one to three hours, more preferably 400° C. for two hours. The result is that hydrogen atoms in the p-Si film (13) efficiently terminate dangling bonds of the film and hence do not become excessive, thus improving the electrical characteristics of the semiconductor device.Type: GrantFiled: April 5, 2004Date of Patent: May 16, 2006Assignee: Sanyo Electric Co., Ltd.Inventors: Yushi Jinno, Shiro Nakanishi, Kyoko Hirai, Tsutomu Yamada, Yoshihiro Morimoto, Kiyoshi Yoneda
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Patent number: 7045819Abstract: A silicon film is crystallized in a predetermined direction by selectively adding a metal element having a catalytic action for crystallizing an amorphous silicon and annealing. In manufacturing TFT using the crystallized silicon film, TFT provided such that the crystallization direction is roughly parallel to a current-flow between a source and a drain, and TFT provided such that the crystallization direction is roughly vertical to a current-flow between a source and a drain are manufactured. Therefore, TFT capable of conducting a high speed operation and TFT having a low leak current are formed on the same substrate.Type: GrantFiled: October 21, 2002Date of Patent: May 16, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Yasuhiro Takemura
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Patent number: 7042009Abstract: A high mobility semiconductor assembly. In one exemplary aspect, the high mobility semiconductor assembly includes a first substrate having a first reference orientation located at a <110> crystal plane location on the first substrate and a second substrate formed on top of the first substrate. The second substrate has a second reference orientation located at a <100> crystal plane location on the second substrate, wherein the first reference orientation is aligned with the second reference orientation. In another exemplary aspect, the second substrate has a second reference orientation located at a <110> crystal plane location on the second substrate, wherein the second substrate is formed over the first substrate with the second reference orientation being offset to the first reference orientation by about 45 degrees.Type: GrantFiled: June 30, 2004Date of Patent: May 9, 2006Assignee: Intel CorporationInventors: Mohamad A. Shaheen, Brian Doyle, Suman Dutta, Robert S. Chau, Peter Tolchinsky
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Patent number: 7034337Abstract: The orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film through heat treatment and irradiation of intense light such as laser light, ultraviolet rays, or infrared rays is enhanced, and a semiconductor device whose active region is formed from the crystalline semiconductor film and a method of manufacturing the semiconductor device are provided. In a semiconductor film containing silicon and germanium as its ingredient and having a crystal structure, the {101} plane reaches 30% or more of all the lattice planes detected by Electron backscatter diffraction.Type: GrantFiled: March 4, 2004Date of Patent: April 25, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi, Takashi Ohtsuki, Toru Mitsuki, Kenji Kasahara, Tamae Takano, Chiho Kokubo, Shunpei Yamazaki, Takeshi Shichi
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Patent number: 7026193Abstract: In a circuit including at least one thin film transistor formed on an insulating substrate, a region 105 to which metal elements that promote crystallinity are added is disposed apart from a semiconductor island region 101 that forms the thin film transistor by a distance y, has a width w, and extends longitudinally over an end portion of the semiconductor island region 101 by a distance x. Also, in a TFT manufactured in a region which is not interposed between the nickel added regions, another nickel added region is disposed (resultantly, which is interposed between two nickel added regions). Further, all the intervals between the respective nickel added regions are preferably identified with each other. Thus, a thin film transistor circuit being capable of a high speed operation (in general, some tens of Mhz and more) is formed. In particular, correcting the difference of crystal growths, using a crystalline silicon film added with nickel, TFTs with uniform characteristics can be provided.Type: GrantFiled: December 6, 1999Date of Patent: April 11, 2006Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hisashi Ohtani, Jun Koyama, Yasushi Ogata, Shunpei Yamazaki
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Patent number: 7023015Abstract: A thin-film semiconductor device is provided including a plurality of thin-film transistors (TFT) having different driving voltages formed on an glass substrate, wherein a gate insulator electric field at each of the driving voltages of the plurality of thin-film transistors is in a range of about 1 MV/cm to 2 MV/cm, and a drain concentration of p-type thin-film transistors (TFT) is in a range of about 3E+19/cm3 to 1E+20/cm3.Type: GrantFiled: August 12, 2003Date of Patent: April 4, 2006Assignee: NEC CorporationInventors: Naoki Matsunaga, Kenji Sera, Mitsuasa Takahashi
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Patent number: 7015507Abstract: Provided is a non-single-crystal germanium thin film transistor having a gate insulating film capable of reducing the interface state density between an active layer and the gate insulating film. This thin film transistor has an active layer made of a non-single-crystal germanium film, and a gate oxide film substantially made of zirconium oxide or hafnium oxide.Type: GrantFiled: May 28, 2004Date of Patent: March 21, 2006Assignee: Canon Kabushiki KaishaInventors: Takao Yonehara, Tetsuya Shimada
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Patent number: 7005676Abstract: There is here disclosed a semiconductor device manufacturing method comprising a step of forming an island region including a monocrystalline Si1-x-yGexCy layer (1>x>0, 1>y?0) and a peripheral region including an amorphous or polycrystalline Si1-x-yGexCy layer which surrounds the island region on a monocrystalline Si layer on an insulating film, a step of subjecting the respective Si1-x-yGexCy layers to heat treatment, and after the heat treatment and the removal of a surface oxide film, a step of forming a monocrystalline Si1-z-wGezCw layer (1>z?0, 1>w?0) which becomes an element formation region on the island region.Type: GrantFiled: July 29, 2003Date of Patent: February 28, 2006Assignee: Kabushiki Kaisha ToshibaInventors: Tsutomu Tezuka, Shinichi Takagi
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Patent number: 7002178Abstract: A thin film transistor device includes a substrate, a buffer layer on the substrate, an active layer on the buffer layer, the active layer is formed of polycrystalline silicon and includes first undoped areas, a second lightly doped area, and third highly doped areas, a gate insulation layer on the buffer layer, a dual-gate electrode on the gate insulation layer including first and second gate electrodes corresponding to the first areas, an interlayer insulator on the gate insulation layer covering the dual-gate electrode, source and drain contact holes exposing the third areas, a gate contact hole penetrating the interlayer insulator to expose a portion of the dual-gate electrode, source and drain electrodes on the interlayer insulator contacting the third areas through the source and drain contact holes, and a third gate electrode on the interlayer insulator contacting the exposed portion of the dual-gate electrode through the gate contact hole.Type: GrantFiled: April 7, 2003Date of Patent: February 21, 2006Assignee: LG.Philips LCD Co., Ltd.Inventor: Hoon-Ju Chung
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Patent number: 6967351Abstract: The present invention provides a device design and method for forming the same that results in Fin Field Effect Transistors having different gains without negatively impacting device density. The present invention forms relatively low gain FinFET transistors in a low carrier mobility plane and relatively high gain FinFET transistors in a high carrier mobility plane. Thus formed, the FinFETs formed in the high mobility plane have a relatively higher gain than the FinFETs formed in the low mobility plane. The embodiments are of particular application to the design and fabrication of a Static Random Access Memory (SRAM) cell. In this application, the bodies of the n-type FinFETs used as transfer devices are formed along the {110} plane. The bodies of the n-type FinFETs and p-type FinFETs used as the storage latch are formed along the {100}. Thus formed, the transfer devices will have a gain approximately half that of the n-type storage latch devices, facilitating proper SRAM operation.Type: GrantFiled: December 4, 2001Date of Patent: November 22, 2005Assignee: International Business Machines CorporationInventors: David M. Fried, Randy W. Mann, K. Paul Muller, Edward J. Nowak
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Patent number: 6933526Abstract: A CMOS thin film transistor having a semiconductor layer formed in a zigzag form on an insulating substrate, and a PMOS transistor region and an NMOS transistor region and a gate electrode having at least one slot crossing the semiconductor layer, wherein the semiconductor layer has an MILC surface existing on the PMOS transistor region and the NMOS transistor region, and the method of manufacturing the same, whereby a manufacturing process of the CMOS TFT is simple and the leakage current is decreased.Type: GrantFiled: September 10, 2002Date of Patent: August 23, 2005Assignee: Samsung SDI Co., Ltd.Inventor: Woo-Young So
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Patent number: 6930326Abstract: According to the invention, a plurality of semiconductor devices which are required to have conformance are formed from crystalline semiconductor films having uniform crystallinity on the same line, and a semiconductor circuit in which variation between semiconductor devices is small can be provided, and a semiconductor integrated circuit having high conformance can be provided. The invention is characterized in that, in a part or whole of thin film transistors which configure an analog circuit such as a current mirror circuit, a differential amplifier circuit, or an operational amplifier, in which high conformance is required for semiconductor devices included therein, channel forming regions have crystalline semiconductor films on the same line. High conformance can be expected for an analog circuit which has the crystalline semiconductor films on the same line formed using the invention as the channel forming regions of the thin film transistors.Type: GrantFiled: March 25, 2003Date of Patent: August 16, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Kiyoshi Kato, Tomoaki Atsumi, Atsuo Isobe
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Patent number: 6927419Abstract: A polycrystal thin film forming method comprising the step of forming a semiconductor thin film on a substrate 14, and the step of flowing a heated gas to the semiconductor thin film while an energy beam 38 is being applied to the semiconductor thin film at a region to which the gas is being applied to thereby melt the semiconductor film, and crystallizing the semiconductor thin film in its solidification. The energy beam is applied while the high-temperature gas is being flowed, whereby the melted semiconductor thin film can have low solidification rate, whereby the polycrystal thin film can have large crystal grain diameters and can have good quality of little defects in crystal grains and little twins.Type: GrantFiled: April 22, 2003Date of Patent: August 9, 2005Assignee: Fujitsu LimitedInventors: Akito Hara, Nobuo Sasaki
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Patent number: 6924506Abstract: A silicon film provided on a blocking film 102 on a substrate 101 is made amorphous by doping Si+, and in a heat-annealing process, crystallization is started in parallel to a substrate from an area 100 where lead serving as a crystallization-promoting catalyst is introduced.Type: GrantFiled: December 1, 2000Date of Patent: August 2, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Hongyong Zhang, Toru Takayama
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Patent number: 6924216Abstract: A method of forming the active regions of field effect transistors is proposed. According to the proposed method, shallow implanting profiles for both the halo structures and the source and drain regions can be obtained by carrying out a two-step damaging and amorphizing implantation process. During a first step, the substrate is damaged during a first light ion implantation step and subsequently substantially fully amorphized during a second heavy ion implantation step.Type: GrantFiled: May 19, 2003Date of Patent: August 2, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Thomas Feudel, Manfred Horstmann, Rolf Stephan
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Patent number: 6909113Abstract: A method of forming a periodic index of refraction pattern in a superlattice of a solid material to achieve photonic bandgap effects at desired optical wavelengths is disclosed. A plurality of space group symmetries, including a plurality of empty-spaced buried patterns, are formed by drilling holes in the solid material and annealing the solid material to form empty-spaced patterns of various geometries. The empty-spaced patterns may have various sizes and may be formed at different periodicities, so that various photonic band structures can be produced for wavelength regions of interest.Type: GrantFiled: November 26, 2002Date of Patent: June 21, 2005Assignee: Micron Technology, Inc.Inventors: Joseph E. Geusic, Kevin G. Donohoe
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Patent number: 6903372Abstract: To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.Type: GrantFiled: October 30, 2000Date of Patent: June 7, 2005Assignee: Hitachi, Ltd.Inventors: Shinya Yamaguchi, Masanobu Miyao, Nobuyuki Sugii, Seang-kee Park, Kiyokazu Nakagawa
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Patent number: 6903371Abstract: An amorphous silicon film is laser irradiated a plural number of times to make the film composed of a plurality of crystal grains while suppressing the formation of protrusions at the boundaries of the adjoining grains to realize a polycrystalline silicon thin film transistor having at least partly therein the clusters of grains, or the aggregates of at least two crystal grains, with preferred orientation in the plane (111), and having high electron mobility of 200 cm2/Vs or above.Type: GrantFiled: February 6, 2004Date of Patent: June 7, 2005Assignee: Hitachi, Ltd.Inventors: Takuo Tamura, Kiyoshi Ogata, Yoichi Takahara, Kazuhiko Horikoshi, Hironaru Yamaguchi, Makoto Ohkura, Hironobu Abe, Masakazu Saitou, Yoshinobu Kimura, Toshihiko Itoga
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Patent number: 6894309Abstract: A surface-transformation method of forming regions of a second material in a first solid material to control the properties of the first solid material is disclosed. The regions of the second material are formed in the first solid material by drilling holes to a predefined depth and at a predefined lattice position. The holes in the first solid material are then filled with a second material and then the first and second materials are heated to a temperature close to the melting point of the first solid material to spontaneously form the regions filled with the second material and embedded in the first solid material at the desired location. A liquid-phase immersion method or a deposition method may be employed to fill the holes in the first solid material.Type: GrantFiled: July 29, 2003Date of Patent: May 17, 2005Assignee: Micron Technology, Inc.Inventor: Joseph E. Geusic
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Patent number: 6888162Abstract: An electronic apparatus employs a polycrystalline semiconductor thin film structure formed of an insulating substrate and a plurality of polycrystalline layers laminated on the insulating substrate. A plurality of transistors are formed at the surface of the polycrystalline semiconductor thin film structure, each transistor being formed in a region of one of a plurality of crystal grains disseminated on the surface of the polycrystalline layers. A number of crystal grains in each of the polycrystalline layers is gradually reduced from a lower layer to an upper layer.Type: GrantFiled: January 30, 2003Date of Patent: May 3, 2005Assignee: Hitachi, Ltd.Inventors: Shinya Yamaguchi, Masanobu Miyao, Kiyokazu Nakagawa, Nobuyuki Sugii
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Patent number: 6885031Abstract: A method of forming a single crystal semiconductor film on a non-crystalline surface is described. In accordance with this method, a template layer incorporating an ordered array of nucleation sites is deposited on the non-crystalline surface, and the single crystal semiconductor film is formed on the non-crystalline surface from the ordered array of nucleation sites. An integrated circuit incorporating one or more single crystal semiconductor layers formed by this method also is described.Type: GrantFiled: August 9, 2003Date of Patent: April 26, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventor: Theodore I. Kamins
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Patent number: 6884668Abstract: To provide devices relating to a manufacturing method for a semiconductor device using a laser crystallization method, which is capable of reducing a cost involved in a design change, preventing a grain boundary from developing in a channel formation region of a TFT, and preventing a remarkable reduction in mobility of the TFT, a decrease in an ON current, and an increase in an OFF current due to the grain boundary and to a semiconductor device formed by using the manufacturing method. In a semiconductor device according to the present invention, among a plurality of TFTs formed on a base film, some TFTs are electrically connected to form logic elements. The plurality of logic elements are used to form a circuit. The base film has a plurality of projective portions having a rectangular or stripe shape.Type: GrantFiled: February 21, 2003Date of Patent: April 26, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Atsuo Isobe, Tamae Takano, Hidekazu Miyairi
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Patent number: 6872977Abstract: A thin film semiconductor device has a semiconductor thin film with a film thickness of 200 nm or less. The semiconductor thin film is formed over a dielectric substrate with a warping point of 600° C. or lower. The semiconductor thin film has a region in which a first semiconductor thin film region with the defect density of 1×1017 cm?3 or less and a second semiconductor thin film region with the defect density of 1×1017 cm?3 or more are disposed alternately in the form of stripes. The width of the first semiconductor thin film region is larger than the width of the semiconductor thin film region. The grain boundaries, grain size and orientation of crystals over the dielectric substrate are controlled, so that a high quality thin film semiconductor device is obtained.Type: GrantFiled: July 5, 2002Date of Patent: March 29, 2005Assignee: Hitachi, Ltd.Inventors: Mutsuko Hatano, Shinya Yamaguchi, Takeo Shiba
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Patent number: 6864127Abstract: There are disclosed techniques for providing a simplified process sequence for fabricating a semiconductor device. The sequence starts with forming an amorphous film containing silicon. Then, an insulating film having openings is formed on the amorphous film. A catalytic element is introduced through the openings to effect crystallization. Thereafter, a window is formed in the insulating film, and P ions are implanted. This process step forms two kinds of regions simultaneously (i.e., gettering regions for gettering the catalytic element and regions that will become the lower electrode of each auxiliary capacitor later).Type: GrantFiled: February 4, 2003Date of Patent: March 8, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Hideto Ohnuma, Tamae Takano, Hisashi Ohtani
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Patent number: 6864520Abstract: A method (and structure) for an electronic chip having at least one layer of material for which a carrier mobility of a first carrier type is higher in a first crystal surface than in a second crystal surface and for which a carrier mobility of a second carrier type is higher in the second crystal surface than the first crystal surface includes a first device having at least one component fabricated on the first crystal surface of the material, wherein an activity of the component of the first device involves primarily the first carrier type, and a second device having at least one component fabricated on the second crystal surface of the material, wherein an activity of the component of the second device involves primarily the second carrier type.Type: GrantFiled: April 4, 2002Date of Patent: March 8, 2005Assignee: International Business Machines CorporationInventors: Massimo V. Fischetti, Steven E. Laux, Paul M. Solomon, Hon-Sum Philip Wong
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Patent number: 6853052Abstract: A semiconductor device and a method for preparing the same that can solve crack of a semiconductor film, capacitance electrodes and the like due to stress when forming a source electrode and a drain electrode in a semiconductor device having a thin film transistor and a holding capacitance with three or more capacitance electrodes is provided. Before forming the source electrode and the drain electrode, a crystalline silicon film for relaxing the stress is formed, then a contact hole connecting to the semiconductor film of the thin film transistor is opened, and a metal film to be the source electrode and the drain electrode is formed.Type: GrantFiled: March 21, 2003Date of Patent: February 8, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Akira Ishikawa
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Patent number: 6847093Abstract: A semiconductor integrated circuit device is formed by a semiconductor substrate having an SiGe layer and a first Si layer epitaxially grown thereover, and on which there are element formation regions each partitioned by element isolation regions; a shallow groove isolation, which has a groove formed in each of the element isolation regions and an insulating film inside of the groove, said groove penetrating through the first Si layer and having a bottom in the SiGe layer; a second Si layer formed between the shallow groove isolation and the SiGe layer; and a semiconductor element formed over the main surface of the semiconductor substrate in the element formation regions. This construction enables a reduction in leakage current via the walls of the shallow groove isolation of the strained substrate, thereby improving the element isolation properties.Type: GrantFiled: June 25, 2003Date of Patent: January 25, 2005Assignee: Renesas Tehnology Corp.Inventors: Katsuhiko Ichinose, Fumio Ootsuka
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Patent number: 6846727Abstract: Methods for forming a patterned SOI region in a Si-containing substrate are provided which has geometries of about 0.25 ?m or less. The methods disclose each utilize a patterned dielectric mask that includes at least one opening having a size of about 0.25 ?m or less which exposes a portion of a Si-containing substrate. Oxygen ions are implanted through the opening using at least a base ion implantation process which is carried out at an oxygen beam energy of about 120 keV or less and an oxygen dosage of about 4E17 cm?2 or less. These conditions minimize erosion of the vertical edges of the patterned dielectric mask and minimize formation of lateral straggles.Type: GrantFiled: May 21, 2001Date of Patent: January 25, 2005Assignee: International Business Machines CorporationInventors: Keith E. Fogel, Mark C. Hakey, Steven J. Holmes, Devendra K. Sadana, Ghavam G. Shahidi
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Patent number: 6844568Abstract: There is disclosed a photoelectric conversion device which is manufactured by depositing numerous crystalline semiconductor particles of one conductivity type on a substrate having an electrode of one side to join the crystalline semiconductor particles to the substrate, interposing an insulator among the crystalline semiconductor particles, forming a semiconductor layer of the opposite conductivity type over the crystalline semiconductor particles, and connecting an electrode to the semiconductor layer of the opposite conductivity type, in which the insulator comprises a mixture or reaction product of polysiloxane and polycarbosilane. The insulator interposed among the crystalline semiconductor particles is free from defects such as cracking and peeling, so that a low cost photoelectric conversion device with high reliability can be provided.Type: GrantFiled: April 25, 2003Date of Patent: January 18, 2005Assignee: Kyocera CorporationInventors: Yoji Seki, Takeshi Kyoda, Yoshio Miura, Hisao Arimune
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Patent number: 6841797Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.Type: GrantFiled: January 8, 2003Date of Patent: January 11, 2005Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Atsuo Isobe, Shunpei Yamazaki, Koji Dairiki, Hiroshi Shibata, Chiho Kokubo, Tatsuya Arao, Masahiko Hayakawa, Hidekazu Miyairi, Akihisa Shimomura, Koichiro Tanaka, Mai Akiba
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Patent number: 6836001Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor layer. The semiconductor substrate has a main surface that is an Si{100} surface. The substrate has a trench in the main surface. The semiconductor layer is located on surfaces defining the trench to have common crystallographic planes with the semiconductor substrate. The trench is defined by a bottom surface, two long sidewall surfaces that face each other, and two short sidewall surfaces that face each other. The bottom surface and the long sidewall surfaces are Si{100} surfaces.Type: GrantFiled: May 21, 2003Date of Patent: December 28, 2004Assignee: Denso CorporationInventors: Shoichi Yamauchi, Hitoshi Yamaguchi, Jun Sakakibara, Nobuhiro Tsuji
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Patent number: 6828614Abstract: The invention includes an array of devices and a charge pump supported by a semiconductive material substrate. A damage region is under the array, and extends less than or equal to 50% of a distance between the array and the charge pump. The invention also includes a method in which a mask is formed over a monocrystalline silicon substrate. A neutral-conductivity-type dopant is implanted through an opening in the mask and into a section of the substrate to produce a damage region. A first boundary extends around the damage region. The masking layer is removed, and epitaxial silicon is formed over the substrate. An array of devices is formed to be supported by the epitaxial silicon. The array is bounded by a second boundary. The first boundary extends less than or equal to 100 microns beyond the second boundary.Type: GrantFiled: March 13, 2003Date of Patent: December 7, 2004Assignee: Micron Technology, Inc.Inventor: Fernando Gonzalez
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Patent number: 6825493Abstract: Sequential lateral solidification (SLS) crystallization of amorphous silicon using a mask having striped light transmitting portions. An amorphous silicon bearing substrate is located in an SLS apparatus. The amorphous silicon film is functionally divided into a driving region (for driving devices) and a display region (for TFT switches). Part of the driving region is crystallized by a laser that passes through the mask. The mask is then moved relative to the substrate by a translation distance that is less than half the width of the light transmitting portions. Thereafter, subsequent crystallizations are performed to crystallize the driving region. Then, part of the display region is crystallized by a laser that passes through the mask. The mask is then moved relative to the substrate by a translation distance that is more than half the width of the light transmitting portions. Thereafter, subsequent crystallizations are performed to crystallize the display region.Type: GrantFiled: June 7, 2002Date of Patent: November 30, 2004Assignee: LG.Philips LCD Co., Ltd.Inventor: Yun-Ho Jung
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Patent number: 6825494Abstract: A polycrystalline silicon thin film of a TFT in which probabilities P1 and P2 for which the maximum number of respective primary crystal grain boundaries for transistors TR1 and TR2 arranged perpendicular to each other are contained in active channel regions are P1=(D1−(Nmax1−1)*Gs1)/Gs1 and P2=(D2−(Nmax2−1)*Gs2)/Gs2: where P1 or P2 is not 0.5, D1=L1 cos &thgr;, W1 sin &thgr;, D2=L2 cos&thgr;+W2 sin &thgr;, L1 and L2 are lengths of active channels, and W1 and W2 are widths of the active channels, of the transistors TR1 and TR2, Nmax1 and Nmax2 are the maximum numbers of the primary crystal grain boundaries contained in the active channel regions for each of TR1 and TR2, Gs1 and Gs2 are crystal grain sizes having a fatal effect on characteristics of each of TR1 and TR2, and &thgr; is an angle in which the primary crystal grain boundaries are inclined perpendicular to an active channel direction of the respective transistors TR1 and TR2.Type: GrantFiled: June 5, 2003Date of Patent: November 30, 2004Assignee: Samsung SDI Co., Ltd.Inventors: Ki Yong Lee, Ji Yong Park, Woo Young So