Abstract: An ultra-thin highly electrically conductive material is prepared by depositing an amorphous material, substantially free of crystal growth-inducing nuclei and sites, onto a substrate. Deposition is preferably with a plasma deposition reactor, with semiconductor dopants introduced during deposition. Deposition time is preferably adjusted to create an amorphous film of a desired thickness, e.g., 200 Å. After deposition, the amorphous film is annealed preferably with a rapid thermal annealing process for four minutes at 700° C. The annealing triggers the creation of nuclei and subsequent large grain growth in the film, releases energy contained within the amorphous material, and helps drive crystallization and dopant activation. After annealing the material is completely crystallized, and contains large grains whose lateral dimensions can exceed the film thickness by a factor of fifty.

Abstract: A method for manufacturing a diode having a relatively improved on-off ratio. The diode is formed in a container in an insulative structure layered on a substrate of an integrated circuit. The container is then partially filled with a polysilicon material, by methods such as conformal deposition, leaving a generally vertical seam in the middle of the polysilicon material. An insulative material is deposited in the seam. The polysilicon material is appropriately doped and electrical contacts and conductors are added as required. The diode can be coupled to a chalcogenide resistive element to create a chalcogenide memory cell.

Abstract: A process for the formation of shaped Group II-VI semiconductor nanocrystals comprises contacting the semiconductor nanocrystal precursors with a liquid media comprising a binary mixture of phosphorus-containing organic surfactants capable of promoting the growth of either spherical semiconductor nanocrystals or rod-like semiconductor nanocrystals, whereby the shape of the semiconductor nanocrystals formed in said binary mixture of surfactants is controlled by adjusting the ratio of the surfactants in the binary mixture.

Abstract: A silicon on insulator (SOI) device includes an electrically-conducting interface region along a portion of the interface between the insulator and a semiconductor layer atop the insulator. The electrically-conducting interface region provides a “leaky” electrical coupling between the body and source regions of a transistor device such as a “MOSFET”, thereby reducing floating body effects of the device. A method of forming such a semiconductor device includes forming the electrically-conducting interface region by damaging or implanting materials in the insulator and/or the semiconductor in the vicinity of the interface therebetween. The method may include producing a stepped interface region, such as by etching, in order to aid properly locating the transistor device relative to the electrically-conducting interface region.

Abstract: In order to obtain a thin-film transistor having high characteristics using a metal element for accelerating the crystallization of silicon, a nickel element is selectively added to the surface of an amorphous silicon film (103) in regions (101) and (102) and regions (108) to (110), and a heat treatment is carried out to grow crystals (horizontal growth) in directions parallel to the substrate as indicated by arrows (104) to (107). At this point, the regions (108) to (110) having a width of 5 &mgr;m or less serve as stopper regions so that horizontal growth starting from the regions (101) and (102) stops there. In this way, the horizontal growth regions can be formed with high controllability. Then a circuit such as a shift register can be constructed with a region having the same crystal growth form.

Abstract: A process for forming Silicon-On-Insulator is described incorporating the steps of ion implantation of oxygen into a silicon substrate at elevated temperature, ion implanting oxygen at a temperature below 200° C. at a lower dose to form an amorphous silicon layer, and annealing steps to form a mixture of defective single crystal silicon and polycrystalline silicon or polycrystalline silicon alone and then silicon oxide from the amorphous silicon layer to form a continuous silicon oxide layer below the surface of the silicon substrate to provide an isolated superficial layer of silicon. The invention overcomes the problem of buried isolated islands of silicon oxide forming a discontinuous buried oxide layer.

Abstract: A microcrystal silicon film is formed on a substrate by using a silicide gas, a hydrogen gas, and a source gas that enables introduction of a metal element for accelerating crystallization of silicon in a capacitance-coupling plasma CVD apparatus. The action of the metal element provides a high film forming rate. Therefore, a technique for forming a microcrystal silicon film with high quality and high film forming rate can be provided.

Abstract: A polycrystalline film of silicon including silicon grains having an aspect ratio, d/t, of more than 1:1, wherein “d” is the grain diameter and “t” is the grain thickness. The polycrystalline film of silicon can be used to form an electronic device, such as a monolithically integrated solar cell having ohmic contacts formed on opposed surfaces or on the same surface of the film. A plurality of solar cells can be monolithically integrated to provide a solar cell module that includes an electrically insulating substrate and at least two solar cells disposed on the substrate in physical isolation from one another. Methods for manufacturing the film, solar cell and solar cell module are also disclosed. The simplified structure and method allow for substantial cost reduction on a mass-production scale, at least in part due to the high aspect ratio silicon grains in the film.

Abstract: A method for manufacturing a thin-film crystalline solar cell includes the steps of (i) forming a porous layer including a large number of fine pores in a surface portion of a crystalline substrate, (ii) transforming a part of the porous layer including the surface thereof into a smooth layer which does not include fine pores by providing the porous layer with excitation energy, and (iii) peeling the smooth layer from the substrate. The excitation energy is provided, for example, by performing heat treatment in a hydrogen atmosphere, irradiating with light having a wavelength equal to or less than 600 nm, or irradiating with an electron beam. It is thereby possible to form a thin-film crystalline semiconductor layer on an inexpensive and flexible substrate by simple processes.

Abstract: A thin film transistor which can be used in an LCD display panel includes an insulator substrate, a gate electrode located on the insulator substrate, an insulator film provided on the insulator substrate and the gate electrode, and a polycrystalline silicon film located on the insulator film. A channel is defined in a first portion of the polycrystalline silicon film over the gate electrode, and a drain and a source are defined in second and third portions of the polycrystalline silicon film over the insulator substrate. Grain sizes of the drain and source are equal to or greater than a grain size of the channel.

Abstract: On the polycrystal semiconductor film 3 formed on the insulating substrate 1, the source 6 and drain 7 in LDD structure having a low concentration region 4 and a high concentration region 5 are formed. The region 4 has a low impurity concentration, and the region 5 has a high impurity concentration. The length of the low concentration region 4 measured from the edge of gate insulating film 9 is not smaller than the average grain size of the polycrystal semiconductor film 3. The LCD device employing the TFT thus constructed is free from white spots (micro brighter spots) in a high temperature atmosphere.

Abstract: A photoelectric conversion element has a substrate, a lower conductive layer, a first doped layer, an i-layer, a second doped layer, and an upper conductive layer, wherein a surface of the lower conductive layer has an uneven configuration, the i-layer contains prismatic crystalline grains, and longitudinal directions of the prismatic crystalline grains are inclined with respect to a direction of a normal line to the substrate. A percentage of an overall volume of prismatic crystalline grains, each having an angle, defined below, of 20° or less, is 70% or more with respect to an overall volume of the i-layer; the angle is defined as an angle between a straight line passing a prismatic crystalline grain and being parallel to the longitudinal direction thereof and a straight line passing the prismatic crystalline grain out of straight lines taking shortest courses between the interface between the first doped layer and the i-layer and the interface between the second doped layer and the i-layer.

Abstract: A semiconductor material having more excellent electric characteristics than polycrystalline semiconductor materials and readily formed on various kinds of substrates is provided. The semiconductor material is made of substantially single crystalline semiconductor crystal grains 3a. These crystal grains 3a are preferentially oriented in a common surface orientation, such as {100}, {111} or {110}-orientation, and grain boundaries 3b of adjacent ones of the crystal grains 3a are in substantial lattice matching with each other at least in a part thereof. In case of {100} orientation, each crystal grain 3a has an approximately square shape, and they are regularly aligned in rows and columns. In case of {111} orientation, each crystal grain 3a has an approximately equilateral hexagonal shape, and they are aligned in an equilateral turtle shell pattern.

Abstract: A method of forming floating gate to improve tunnel oxide reliability for flash memory devices. A substrate having a source, drain, and channel regions is provided. A tunnel oxide layer is formed over the substrate. A floating gate is formed over the tunnel oxide and the channel region, the floating gate being multi-layered and having a second layer sandwiched between a first layer and a third layer. The first layer of the floating gate overlying the tunnel oxide layer includes an undoped or lightly doped material. The second layer is highly-doped. The third layer is in direct contact with a dielectric layer, e.g., an oxide-nitride-oxide stack, and is made of an undoped or lightly doped material. A dielectric material is formed over the floating gate and a control gate is formed over the dielectric material.

Abstract: A nitride semiconductor light emitting device which uses as a light emitting layer an indium-containing group-III nitride semiconductor layer of a multi-phase structure composed of a main phase and sub-phases having different indium contents is characterized in that the sub-phases are mainly formed of crystal whose boundary with the main phase is surrounded by a strained layer.

Abstract: A method of manufacturing a semiconductor includes the steps of: forming a first semiconductor film on a substrate having an insulating surface; applying an energy to the first semiconductor film to crystallize the first semiconductor film; patterning the first semiconductor film to form a region that forms a seed crystal; etching the seed crystal to selectively leave a predetermined crystal face in the seed crystal; covering the seed crystal to form a second semiconductor film; and applying an energy to the second semiconductor film to conduct a crystal growth from the seed crystal in the second semiconductor film.

Abstract: A semiconductor device comprises, at least, an insulative layer; a semiconductor layer provided in contact with the insulative layer; first and second electrodes provided in contact with the semiconductor layer; and a third electrode provided through the insulative layer. The semiconductor layer has a crystallite layer whose average grain diameter lies within a range from 50 to 350 .ANG. and an amorphous layer.

Abstract: To provide a semiconductor device having a function equivalent to that of IGFET, an activation layer is formed by a crystal silicon film crystallized by using a catalyst element helping promote crystallization and a heating treatment is carried out in an atmosphere including a halogen element by which the catalyst element is removed, the activation layer processed by such steps is constituted by a peculiar crystal structure and according to the crystal structure, a rate of incommensurate bonds in respect of all of bonds at grain boundaries is 5% or less (preferably, 3% or less).

Abstract: In a semiconductor circuit using a silicon film in which crystals grow in the direction parallel to a substrate, the distance between the position of a starting region of crystal growth and the position of the respective active layers are made the same. Thus, the difference of the characteristics due to the difference of the distance of crystal growth is corrected.

Abstract: In forming an electrode on a silicon oxide film on a semiconductor substrate through a silicon oxide film, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers. The portion of the gate electrode is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and of crystallizing (recrystallizing) this amorphous material. Depositing of the amorphous layers is carried out a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and crystallizing the amorphous material are repeated, whereby a laminated structure of polycrystalline layers having a necessary film thickness is obtained.

Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 .mu.m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.

Abstract: A first heat treatment for crystallization is implemented after introducing nickel to an amorphous silicon film 103 disposed on a quartz substrate 101. A crystal silicon film 105 is obtained by this heat treatment. Then, a oxide film 106 is formed by wet oxidation. At this time, the nickel element is gettered to the oxide film 106 by an action of fluorite. Then, the oxide film 106 is removed. Thereby, a crystal silicon film 107 having low concentration of the metal element and a high crystallinity can be obtained.

Abstract: A transistor includes an MILC (metal-induced lateral crystallization) region formed on a substrate with a semiconductor material and including a channel region, and a plurality of MIC (metal-induced crystallization) regions formed on the sides of the MILC region with a semiconductor material, wherein at least one boundary between the MILC region and one of the MIC regions is located outside the channel region. A method of fabricating a transistor includes the steps of forming an MILC (metal-induced lateral crystallization) region on a substrate using a semiconductor material, the MILC region including a channel region, and forming a plurality of MIC (metal-induced crystallization) regions formed on sides of the MILC region using a semiconductor material, wherein at least one boundary between the MILC region and one of the MIC regions is located outside the channel region.

Abstract: Disclosed is an inductively coupled plasma chemical vapor deposition method for depositing a selected thin film on a substrate from inductively coupled plasma, the method including the steps of: providing a vacuum reaction chamber including an interior bounded, in part by a dielectric shield, the dielectric shield having an amorphous silicon layer on its interior surface, and an antenna arranged outside the deposition chamber adjacent to the dielectric shield where RF power is applied; placing the substrate on a stage with the chamber; exhausting the vacuum reaction chamber leaving a vacuum state; introducing a reactant gas to the vacuum reaction chamber at a predetermined pressure; and applying RF power to the antenna, whereby inductively coupled plasma for deposition of a thin film from the reactant gas is formed within the vacuum chamber.

Abstract: A semiconductor device includes a substrate having an insulating film on its surface, and an active layer made of a semiconductive thin film on the substrate surface. The thin film contains a mono-domain region formed of multiple columnar and/or needle-like crystals parallel to the substrate surface without including crystal boundaries therein, allowing the active layer to consist of the mono-domain region only. The insulating film underlying the active layer has a specific surface configuration of an intended pattern in profile, including projections or recesses. To fabricate the active layer, form a silicon oxide film by sputtering on the substrate. Pattern the silicon oxide film providing the surface configuration. Form an amorphous silicon film by low pressure CVD on the silicon oxide film. Retain in the silicon oxide film and/or the amorphous silicon film certain metallic element for acceleration of crystallization.

Abstract: Nickel is selectively held in contact with a particular region of an amorphous silicon film. Crystal growth parallel with a substrate is effected by performing a heat treatment. A thermal oxidation film is formed on the silicon film by performing a heat treatment in an oxidizing atmosphere containing a halogen element. During this step, in the silicon film, impurities included such as oxygen or chlorine, are segregated with extending along the crystal growth, the crystallinity is improved, and the gettering of nickel element proceeds. A thin-film transistor is formed so that the direction connecting source and drain regions coincides with the above crystal growth direction. As a result, a TFT having superior characteristics such as a mobility larger than 200 cm.sup.2 /Vs and an S value smaller than 100 mV/dec. can be obtained.

Abstract: Semiconductor devices such as thin-film transistors formed by annealing a substantially amorphous silicon film at a temperature either lower than normal crystallization temperature of amorphous silicon or lower than the glass transition point of the substrate so as to crystallize the silicon film. Islands, stripes, lines, or dots of nickel, iron, cobalt, or platinum, silicide, acetate, or nitrate of nickel, iron, cobalt, or platinum, film containing various salts, particles, or clusters containing at least one of nickel, iron, cobalt, and platinum are used as starting materials for crystallization. These materials are formed on or under the amorphous silicon film.

Abstract: A thin film transistor includes: an insulating film having a surface; a semiconductor film formed on the surface of the insulating film; a source electrode and a drain electrode which are in contact with the semiconductor film; and a gate electrode which is electrically insulated from the semiconductor film. In the thin film transistor, a portion of the semiconductor film at distances of less than 500 angstroms from the surface of the insulating film contains at least silicon including a microcrystalline structure having a conductivity of 5.times.10.sup.-9 S/cm or more. Also, a method for fabricating such a thin film transistor is disclosed.

Abstract: The invention provides a peripheral drive circuit integrated active matrix LCD device in which thin-film transistors have different characteristics optimized for individual circuits of the active matrix LCD device. A pixel matrix portion includes thin-film transistors, each having offset gate regions 134 and 136 produced in a non-self-alignment manner, an n-channel driver portion includes thin-film transistors, each having lightly-doped regions 128 and 130 produced in a combination of the non-self-alignment manner and a self-alignment manner, and a p-channel driver portion includes thin-film transistors produced in a self-alignment manner. This construction makes it possible to arrange the thin-film transistors having characteristics required by the individual circuits.

Abstract: In those thin-film transistors (TFTs) employing as its active layer a silicon film crystallized using a metal element, the objective is to eliminate bad affection of such metal element to the TFT characteristics. To this end, in a TFT having as its active layer a crystalline silicon film that was crystallized using nickel (Ni), those regions corresponding to the source/drain thereof are doped with phosphorus; thereafter, thermal processing is performed. During this process, nickel residing in a channel formation region is "gettered" into previously phosphorus-doped regions. With such an arrangement, it becomes possible to reduce the Ni concentration in certain regions in which lightly-doped impurity regions will be formed later, which in turn enables suppression of affection to TFT characteristics.

Abstract: A vertical thin film transistor formed in a single grain of polysilicon having few or no grain boundaries for use in memory, logic and display applications. The transistor is formed from a thin film of polysilicon having large columnar grains, in which source and drain regions have been formed. The large grain size and columnar grain orientation of the thin film are provided by recrystallizing a thin amorphous silicon film, or by specialized deposition of the thin film. Use of a thin film permits the transistor to be formed on an insulating substrate such as glass, quartz, or inexpensive silicon rather than a semiconductor chip, thereby significantly decreasing device cost.

Abstract: A semiconductor device having high carrier mobility, which comprises a substrate provided thereon a base film and further thereon a crystalline non-single crystal silicon film by crystal growth, wherein, the crystals are grown along the crystallographic [110] axis, and source/drain regions are provided approximately along the direction of carrier movement which coincides to the direction of crystal growth. Moreover, the electric conductivity along this direction of crystal growth is higher than any in other directions.

Abstract: A circuit adapted to dynamically activate an electro-optical display device is constructed from a thin-film gate-insulated semiconductor device. This device comprises PMOS TFTs producing only a small amount of leakage current. Besides the dynamic circuit, a CMOS circuit comprising both NMOS and PMOS thin-film transistors is constructed to drive the dynamic circuit.

Abstract: A semiconductor storage element has a source region, a drain region, and a channel region connecting the source region with the drain region, which each are formed on an insulation film of a substrate. A gate insulation film is formed between the channel region and a gate electrode. The source region, the drain region, and the channel region consist of an aggregate of spherical grains which are arranged two-dimensionally on the insulation film and connected with one another such that the adjacent spherical grains are conductive to one another. The channel region contains at least one carrier trap region provided at a location other than an electric path thereof.

Abstract: In a circuit including at least one thin film transistor formed on an insulating substrate, a region 105 to which metal elements that promote crystallinity are added is disposed apart from a semiconductor island region 101 that forms the thin film transistor by a distance y, has a width w, and extends longitudinally over an end portion of the semiconductor island region 101 by a distance x. Also, in a TFT manufactured in a region which is not interposed between the nickel added regions, another nickel added region is disposed (resultantly, which is interposed between two nickel added regions). Further, all the intervals between the respective nickel added regions are preferably identified with each other. Thus, a thin film transistor circuit being capable of a high speed operation (in general, some tens of Mhz and more) is formed. In particular, correcting the difference of crystal growths, using a crystalline silicon film added with nickel, TFTs with uniform characteristics can be provided.

Abstract: Any one of an insulating film forming a TFT, a silicon film and a conductive film is formed by applying a solution and annealing it. In a spin coater (102), a coating solution containing a thin film component which is supplied from a solution storage section (105) is spin-coated onto a substrate. The substrate after coating the coating solution is annealed in an annealing section (103) to form a coating film on the substrate. Additional laser annealing improves one of film characteristics, i.e., crystallinity, density and adhesiveness. Application of the coating solution or a resist by an ink jet process increases utilization of the solution and permits forming a patterned coating film. Because a thin film device in accordance with the present invention is inexpensive and has a high throughput, TFT production by a production system having high utilization of the coating solution drastically reduces initial investment and production cost of a liquid crystal display device.

Abstract: The principle portion of a semiconductor device is made from a polycrystalline silicon semiconductor layer which yields an X ray diffraction pattern or an electron beam pattern with the (311) diffraction peak intensity accounting for 15% or more of the total diffraction peak intensity. A semiconductor device improved in performance and reliability can be obtained by reducing the density of states at the boundary between the polycrystalline silicon film and the gate insulating film.

Abstract: A silicon film provided on a blocking film 102 on a substrate 101 is made amorphous by doping Si+, and in a heat-annealing process, crystallization is started in parallel to a substrate from an area 100 where nickel serving as a crystallization-promoting catalyst is introduced.

Abstract: Regions 106 which can be regarded as being monocrystalline are formed locally by irradiating with laser light, and at least the channel-forming region 112 is constructed using these regions. With thin-film transistors which have such a construction it is possible to obtain characteristics which are similar to those which employ monocrystals. Further, by connecting in parallel a plurality of such thin-film transistors it is possible to obtain characteristics which are effectively equivalent to those of a monocrystalline thin-film transistor in which the channel width has been increased.

Abstract: A method is provided of fabricating a thin film transistor semiconductor film of polycrystalline silicon on a transparent substrate suitable for the manufacture of a liquid crystal display. A film of substantially amorphous silicon is placed on the transparent substrate. Suspended in the amorphous silicon are small silicon seed crystals. As the amorphous silicon is annealed, crystal grains, begun from the seed crystals, are formed in the resulting polycrystalline silicon. The seed crystals help regulate the annealment process, and reduce process dependence on precision deposition and heating methods. The use of seed crystals also helps ensure that crystal grains are both large and consistent in size. Large grains promote to production of TFTs with high electron mobility and uniform performance across the entire LCD. An LCD with a TFT polycrystalline film layer over a transparent substrate, formed from annealing substantially amorphous silicon with suspended seed crystals, is also provided.

Abstract: In the crystal structure of a polysilicon thin film having a field effect mobility .mu..sub.FE of about 80 cm.sup.2 /V.multidot.sec, a grain size is about 200 nm and a crystallite size on the (111) plane is about 180 nm. The crystal size corresponds to the size of a completely monocrystallized portion of a grain. The condition of obtaining a field effect mobility .mu..sub.FE of about 80 cm.sup.2 /V.multidot.sec is that the crystallite size on the (111) plane is at least 180 nm (measured value). By taking the crystallite size into consideration, it becomes possible to achieve a high field effect mobility .mu..sub.FE which cannot be obtained merely by increasing the grain size.

Abstract: A crystalline silicon thin film transistor having an LDD (lightly doped drain) structure and a process for fabricating the same, which comprises introducing a catalyst element for accelerating crystallization at a concentration of 1.times.10.sup.15 cm.sup.-3 or more but less than 2.times.10.sup.19 cm.sup.-3 to the impurity region in an amorphous silicon film, crystallizing the amorphous film thereafter, and after forming gate electrode and gate insulating film, implanting an impurity in a self-aligned manner to establish an LDD structure.

Abstract: A thin film transistor includes: a) a thin film transistor layer comprising a source region, a channel region and a drain region; the thin film transistor layer further comprising a drain offset region positioned between the drain region and the channel region; b) the channel region being substantially polycrystalline and having a first average crystalline grain size; and c) the drain offset region being substantially polycrystalline and having a second average crystalline grain size, the second average crystalline grain size being larger than the first average crystalline grain size. A method for forming such a construction using polycrystalline materials, preferably polysilicon, and an amorphizing silicon implant with subsequent recrystallization is also disclosed.

Abstract: A thin film transistor and a method for fabricating the same in which a self alignment method is used to form an offset area and source and drain electrodes are disclosed, the TFT including a substrate; a trench formed in the substrate,; an active layer fromed on the substrate and on the trench; a gate insulating film formed on the active layer; a gate electrode formed on the gate insulating film on at least one side of the trench; a source region formed in the active layer on a bottom side of the trench; and drain regions formed in the active layer on the substrate to be isolated form the gate electrode.

Abstract: A semiconductor device is disclosed. The semiconductor device has a crystalline silicon film as an active layer region. The crystalline silicon film has needle-like or columnar crystals oriented parallel to the substrate and having a crystal growth direction of (111) axis. A method for preparing the semiconductor device comprises steps of adding a catalytic element to an amorphous silicon film; and heating the amorphous silicon film containing the catalytic element at a low temperature to crystallize the silicon film.

Abstract: An epitaxial wafer for a light-emitting device has a double hetero-structure and includes a single-crystal substrate, a lower cladding layer of AlGaN grown on the substrate, an active layer grown on the lower cladding layer, the active layer having a two-phase structure comprised of a matrix of Al.sub.x Ga.sub.y In.sub.z N and crystallets of Al.sub.a Ga.sub.b In.sub.c N, and an upper cladding layer of AlGaN grown on the active layer.

Abstract: A microwave circuit package includes a metallic base plate on which are mounted a plurality of monolithic microwave integrated circuits (MMICs) and a spacer, made of a dielectric material, separating the MMICs from each other, and the MMICs and spacer are sealed in the package. The provision of the spacer substantially reduces the volume of the interior space of the package. A dielectric substrate having generally the same height as substrates of the MMICs may also be mounted on the metallic base plate, and a strip conductor may be provided on the dielectric substrate so as to form a microstrip line thereon.

Abstract: A first polysilicon layer is formed on a substrate, and vacancies are introduced into an upper portion of the first polysilicon layer, thereby forming a second polysilicon layer. Then, a third polysilicon layer is formed on the second polysilicon layer. After depositing a silicon oxide film and a polysilicon film for a gate on the third polysilicon layer, these films are made into a pattern, thereby forming a control gate electrode and a gate oxide film. Impurity ions are then implanted, thereby forming source/drain regions. Thus, a channel region including the second polysilicon layer with the vacancies introduced is disposed below the control gate electrode, and hence, the mobility of a carrier in the channel region can be improved. As a result, a device can be operated at a high speed with a low voltage.

Abstract: A method is provided for forming a hemispherical grain silicon structure on an integrated circuit semiconductor substrate in a processing reactor. The method includes the steps of forming a doped silicon layer upon the semiconductor substrate and forming an amorphous silicon layer upon the doped silicon layer. A hemispherical grain silicon layer is formed upon the amorphous silicon layer. The doped silicon layer is formed at a first deposition temperature and the amorphous silicon layer is formed at a second deposition temperature wherein the second deposition temperature is lower than the first deposition temperature. The first deposition temperature is, for example, in excess of approximately 590.degree. C. and is preferably approximately 625.degree. C. The second deposition temperature is less than approximately 560.degree. C. and is preferably approximately 555.degree. C. The various layers are deposited without removing the semiconductor substrate from the processing reactor.

Abstract: A semiconductor window which is transparent to light in the infrared range and which has good electrical conductivity is formed of a prefabricated semiconductor sheet bonded to a substrate material by optical contact. The sheet is a substantially uniformly doped wafer sufficiently thin that inherent absorption bands do not affect transmission. The sheet is contact bonded to the surface of an undoped transparent substrate without diffusion, growth or deposition on the surface. Windows having particular optical band pass characteristics are formed utilizing a zinc selenide substrate and a gallium arsenide sheet.