Non-single Crystal, Or Recrystallized, Material With Specified Crystal Structure (e.g., Specified Crystal Size Or Orientation) Patents (Class 257/64)
  • Patent number: 6815717
    Abstract: To a polycrystalline silicon layer crystallized by irradiation with laser light, a mixed gas comprised of ozone gas and H2O or N2O gas is fed at a processing temperature of 500° C. or below, or the polycrystalline silicon layer is previously treated with a solution such as ozone water or an aqueous NH3/hydrogen peroxide solution, followed by oxidation treatment with ozone, to form a silicon oxide layer with a thickness of 4 nm or more at the surface of the polycrystalline silicon layer for forming a thin-film transistor having characteristics that are less varying on a glass substrate previously not annealed.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: November 9, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiko Horikoshi, Kiyoshi Ogata, Miwako Nakahara, Takuo Tamura, Yasushi Nakano, Ryoji Oritsuki, Toshihiko Itoga, Takahiro Kamo
  • Patent number: 6815269
    Abstract: A thin-film transistor is formed by a polycrystalline silicon film having a thin-film part and a thick-film part, the thin-film part minimally being used as a channel part. The polycrystalline silicon film is formed by laser annealing with an energy density that completely melts the thin-film part but does not completely melt the thick-film part. Because large coarse crystal grains growing from the boundary between the thin-film part and the thick-film part form the channel part, it is possible to use a conventional laser annealing apparatus to easily achieve high carrier mobility and low leakage current and the like.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: November 9, 2004
    Assignee: NEC LCD Technologies, Ltd.
    Inventor: Hiroshi Okumura
  • Publication number: 20040217352
    Abstract: One aspect of the present invention relates to a method for forming a strained semiconductor structure. In various embodiments, at least two strong bonding regions are defined for a desired bond between a crystalline semiconductor membrane and a crystalline semiconductor substrate. The two strong bonding regions are separated by a weak bonding region. The membrane is bonded to the substrate at a predetermined misorientation. The membrane is pinned to the substrate in the strong bonding regions. The predetermined misorientation provides the membrane in the weak bonding region with a desired strain. In various embodiments, the membrane is bonded to the substrate at a predetermined twist angle to biaxially strain the membrane in the weak bonding region. In various embodiments, the membrane is bonded to the substrate at a predetermined tilt angle to uniaxially strain the membrane in the weak bonding region. Other aspects are provided herein.
    Type: Application
    Filed: April 29, 2003
    Publication date: November 4, 2004
    Applicant: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 6812490
    Abstract: The present invention provide an LDD type TFT having excellent properties, particularly for a liquid crystal display unit. For this purpose, a top gate type LDDTFT gate electrode is converted into a two-stage structure by use of a chemical reaction or plating, and furthermore, into a shape in which an upper portion or a lower portion slightly protrudes on the source electrode side, or the drain electrode side relative to the other portions. Impurities are injected by using this electrode having this structure and shape as a mask. Prior to injection of impurities, the gate insulating film is removed, and a Ti film is formed for preventing hydrogen for dilution from coming in. This is also the case with the LDD-TFT on the bottom gate side.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: November 2, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Shin-itsu Takehashi, Shigeo Ikuta, Tetsuo Kawakita, Mayumi Inoue, Keizaburo Kuramasu
  • Patent number: 6812493
    Abstract: The present invention provides a thin film semiconductor element which is small in area with high on-current enough to be suitable for the power saving, miniaturization, and high definition display of a device. According to the present invention, an outer shape of a semiconductor thin film is processed and regions (a channel region, a source region, and a drain region) in the semiconductor thin film are formed by using, as masks, other element components such as a gate electrode. Specifically, ion-implanted regions are formed by implanting impurity ions into predetermined regions of the semiconductor thin film using, as a mask, the gate electrode overlapped on the thin film via an insulation film. Thereafter, the semiconductor is processed into a predetermined shape by etching using, as masks, previously formed element components such as the gate electrode.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: November 2, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Mikio Nishio
  • Patent number: 6806498
    Abstract: In a polycrystalline silicon thin film transistor, a semiconductor device having a high field effect mobility is achieved by increasing a grain size of a silicon thin film. First, an insulation layer having a two-layer structure is formed on a transparent insulated substrate 201. In the insulation layer, a lower insulation layer 202, which is in contact with the transparent insulating substrate 201, is made to have a higher thermal conductivity than an upper insulation layer 203. Thereafter, the upper insulation layer 203is patterned so that a plurality of stripes are formed thereon. Subsequently, an amorphous silicon thin film 204 is formed on the patterned insulation layer, and the insulation layer is irradiated with a laser light scanning in a direction parallel to the stripe pattern on the upper insulation layer 203. Thus, the amorphous silicon thin film 203 is formed into a polycrystalline silicon thin film 210.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: October 19, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yoshinao Taketomi, Keizaburo Kuramasu, Masumi Izuchi, Hiroshi Satani, Hiroshi Tsutsu, Hikaru Nishitani, Mikihiko Nishitani, Masashi Goto, Yoshiko Mino
  • Patent number: 6787806
    Abstract: A thin film semiconductor transistor structure has a substrate with a dielectric surface, and an active layer made of a semiconductor thin film exhibiting a crystallinity as equivalent to the single-crystalline. To fabricate the transistor, the semiconductor thin film is formed on the substrate, which film includes a mixture of a plurality of crystals which may be columnar crystals and/or capillary crystal substantially parallel to the substrate. The resultant structure is then subject to thermal oxidation in a chosen atmosphere containing halogen, thereby removing away any metallic element as contained in the film. This may enable formation of a mono-domain region in which the individual columnar or capillary crystal is in contact with any adjacent crystals and which is capable of being substantially deemed to be a single-crystalline region without presence or inclusion of any crystal grain boundaries therein. This region is for use in forming the active layer of the transistor.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: September 7, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Akiharu Miyanaga, Takeshi Fukunaga
  • Publication number: 20040169177
    Abstract: The orientation ratio of a crystalline semiconductor film obtained by crystallizing an amorphous semiconductor film through heat treatment and irradiation of intense light such as laser light, ultraviolet rays, or infrared rays is enhanced, and a semiconductor device whose active region is formed from the crystalline semiconductor film and a method of manufacturing the semiconductor device are provided. In a semiconductor film containing silicon and germanium as its ingredient and having a crystal structure, the {101} plane reaches 30% or more of all the lattice planes detected by Electron backscatter diffraction.
    Type: Application
    Filed: March 4, 2004
    Publication date: September 2, 2004
    Applicant: Semiconductor Energy Laboratory Co., Ltd. a Japan corporation
    Inventors: Taketomi Asami, Mitsuhiro Ichijo, Satoshi Toriumi, Takashi Ohtsuki, Toru Mitsuki, Kenji Kasahara, Tamae Takano, Chiho Kokubo, Shunpei Yamazaki, Takeshi Shichi
  • Patent number: 6759679
    Abstract: A poly-silicon layer of a thin film transistor (TFT) having an active channel region, wherein a probability P that a maximum number of a primary grain boundary exists on the active channel region is not 0.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: July 6, 2004
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Ki-Yong Lee
  • Patent number: 6756657
    Abstract: A semiconductor device is disclosed. The semiconductor device has a crystalline silicon film as an active layer region. The crystalline silicon film has needle-like or columnar crystals oriented parallel to the substrate and having a crystal growth direction of (111) axis. A method for preparing the semiconductor device comprises steps of adding a catalytic element to an amorphous silicon film; and heating the amorphous silicon film containing the catalytic element at a low temperature to crystallize the silicon film.
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: June 29, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Toru Takayama, Yasuhiko Takemura, Akiharu Miyanaga, Hisashi Ohtani, Junichi Takeyama
  • Patent number: 6750394
    Abstract: A thin-film solar cell comprises a set of a transparent conductive layer and a photoelectric conversion layer laminated in this order on a substrate, wherein the photoelectric conversion layer is made of a p-i-n junction, the i-layer is made of a crystalline layer and the transparent conductive layer is provided with a plurality of holes at its surface of the side of the photoelectric conversion layer, each of said holes having irregularities formed on its surface.
    Type: Grant
    Filed: January 10, 2002
    Date of Patent: June 15, 2004
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroshi Yamamoto, Kenji Wada
  • Publication number: 20040108503
    Abstract: There is disclosed a method of fabricating a thin-film transistor having excellent characteristics. Nickel element is held in contact with selected regions of an amorphous silicon film. Then, thermal processing is performed to crystallize the amorphous film. Subsequently, thermal processing is carried out in an oxidizing ambient containing a halogen element to form a thermal oxide film. At this time, the crystallinity is improved. Also, gettering of the nickel element proceeds. This crystalline silicon film consists of crystals grown radially from a number of points. Consequently, the thin-film transistor having excellent characteristics can be obtained.
    Type: Application
    Filed: November 14, 2003
    Publication date: June 10, 2004
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Teramoto, Jun Koyama, Yasushi Ogata, Masahiko Hayakawa, Mitsuaki Osame, Hisashi Ohtani, Toshiji Hamatani
  • Patent number: 6737672
    Abstract: An a-Si film is patterned into a linear shape (ribbon shape) or island shape on a glass substrate. The upper surface of the a-Si film or the lower surface of the glass substrate is irradiated and scanned with an energy beam output continuously along the time axis from a CW laser in a direction indicated by an arrow, thereby crystallizing the a-Si film. This implements a TFT in which the transistor characteristics of the TFT are made uniform at high level, and the mobility is high particularly in a peripheral circuit region to enable high-speed driving in applications to a system-on glass and the like.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: May 18, 2004
    Assignee: Fujitsu Limited
    Inventors: Akito Hara, Fumiyo Takeuchi, Kenichi Yoshino, Nobuo Sasaki
  • Patent number: 6737674
    Abstract: There is provided a method for eliminating influence of nickel element from a crystal silicon film obtained by utilizing nickel. A mask made of a silicon oxide film is formed on an amorphous silicon film. Then, the nickel element is held selectively on the surface of the amorphous silicon film by utilizing the mask. Next, a heat treatment is implemented to grow crystal. This crystal growth occurs with the diffusion of the nickel element. Next, phosphorus is doped to a region by using the mask. Then, another heat treatment is implemented to remove the nickel element from the pattern under the mask through the course reverse to the previous course in diffusing the nickel element in growing crystal. Then, the silicon film is patterned by utilizing the mask again to form a pattern. Thus, the pattern of the active layer which has high crystallinity and from which the influence of the nickel element is removed may be obtained without increasing masks in particular (i.e. without complicating the process).
    Type: Grant
    Filed: April 17, 2002
    Date of Patent: May 18, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Hideto Ohnuma
  • Patent number: 6734499
    Abstract: An insulated gate field effect transistor comprises a non-single-crystalline semiconductor layer formed on a substrate, a gate electrode is formed on a portion of the surface of said semiconductor layer, and a gate insulating film is disposed between said gate electrode and said semiconductor layer. A non-single-crystalline channel region is defined within said semiconductor layer just below said gate electrode. A source region and a drain region are transformed from and defined within said semiconductor layer immediately adjacent to said channel region in an opposed relation, said source and drain regions being crystallized to a higher degree than that of said channel region by selectively irradiating portions of said semiconductor layer using said gate electrode as a mask.
    Type: Grant
    Filed: September 28, 1999
    Date of Patent: May 11, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 6720575
    Abstract: An insulating film 103 for making an under insulating layer 104 is formed on a quartz or semiconductor substrate 100. Recesses 105a to 105d corresponding to recesses 101a to 101d of the substrate 100 are formed on the surface of the insulating film 103. The surface of this insulating film 103 is flattened to form the under insulating layer 104. By this flattening process, the distance L1, L2, . . . , Ln between the recesses 106a, 106b, 106d of the under insulating layer 104 is made 0.3 &mgr;m or more, and the depth of the respective recesses is made 10 nm or less. The root-mean-square surface roughness of the surface of the under insulating film 104 is made 0.3 nm or less. By this, in the recesses 106a, 106b, 106d, it can be avoided to block crystal growth of the semiconductor thin film, and crystal grain boundaries can be substantially disappeared.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: April 13, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Toru Mitsuki, Hisashi Ohtani
  • Patent number: 6720578
    Abstract: A polycrystalline silicon thin film for a TFT and a display device using the same where the number of crystal grain boundaries exerts a fatal influence on movement of electric charge carrier, providing a distance “S” between active channels of the TFT having dual or multiple channels with a relation S=mGs·sec &thgr;−L, and also providing a display device in which uniformity of TFT characteristics is improved by synchronizing the number of the crystal grain boundaries included in each of the channels of the dual or multiple channels S=mGs·sec &thgr;−L Gs is a size of crystal grains of the polycrystalline silicon thin film, m is an integer of 1 or more, &thgr; is an inclined angle where fatal crystal grain boundaries, that is, “primary” crystal grain boundaries are inclined in a direction perpendicular to an active channel direction, and L represents a length of active channels for each TFT having dual or multiple channels.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: April 13, 2004
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Ki-Yong Lee
  • Patent number: 6716664
    Abstract: A functional device free from cracking and having excellent functional characteristics, and a method of manufacturing the same are disclosed. A low-temperature softening layer (12) and a heat-resistant layer (13) are formed in this order on a substrate (11) made of an organic material such as polyethylene terephthalate, and a functional layer (14) made of polysilicon is formed thereon. The functional layer (14) is formed by crystallizing an amorphous silicon layer, which is a precursor layer, with laser beam irradiation. When a laser beam is applied, heat is transmitted to the substrate (11) and the substrate (11) tends to expand. However, a stress caused by a difference in a thermal expansion coefficient between the substrate (11) and the functional layer (14) is absorbed by the low-temperature softening layer (12), so that no cracks and peeling occurs in the functional layer (14). The low-temperature softening layer (12) is preferably made of a polymeric material containing an acrylic resin.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: April 6, 2004
    Assignee: Sony Corporation
    Inventors: Akio Machida, Dharam Pal Gosain, Setsuo Usui
  • Patent number: 6713825
    Abstract: A thin film transistor and its fabrication method. The transistor includes a buffer layer on a substrate, and a poly-crystalline semiconductor layer on the buffer layer. The poly-crystalline semiconductor layer includes a channel layer, offset regions along sides of the channel layer, sequential doping regions along sides of the offset regions, and source and drain regions. The doping concentration is sequentially changed in the sequential doping region. A sloped gate insulation layer is on the poly-crystalline semiconductor layer. A gate electrode having a main gate electrode and auxiliary gate electrodes is on the sloped insulation layer. An interlayer is over the gate electrode and source and drain electrodes are formed in contact with the source and drain regions and on the interlayer. The poly-crystalline semiconductor layer is formed by ion doping a poly-crystalline semiconductor layer through the gate insulation layer while using the gate electrode as a mask.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: March 30, 2004
    Assignee: LG. Philips LCD Co., Ltd.
    Inventor: Han-Wook Hwang
  • Patent number: 6713788
    Abstract: An integrated circuit is provided with one or more connectors which allow an opto-electric device to be mounted on the integrated circuit directly on top of or underneath of it. Multiple opto-electric device interface regions can be defined on the integrated circuit such that an opto-electric device can be connected in a variety of directions or such that multiple opto-electric devices can be connected. In addition, an opto-electric device interface may be provided that causes the opto-electric device's leads to be directed to the corresponding integrated circuit lead in the shortest possible distance regardless of how the opto-electric device is positioned. Also disclosed is a substrate-mounted optical transmission system that may be used in connection with the opto-electric device.
    Type: Grant
    Filed: January 14, 2003
    Date of Patent: March 30, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Kevin G. Duesman, Warren M. Farnworth
  • Patent number: 6703289
    Abstract: A plurality of linear catalytic metal element portions are arranged at predetermined intervals just on or just beneath an amorphous silicon layer, and, in this state, the amorphous silicon layer is heat treated to crystallize the amorphous silicon layer and consequently to form a polycrystalline silicon layer. This construction can realize the provision of a method for the formation of an evenly oriented, high-quality crystalline silicon layer in a large area, and a crystalline silicon semiconductor device produced by this method.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: March 9, 2004
    Assignee: Hitachi Cable, Ltd.
    Inventors: Shinichi Muramatsu, Yasushi Minakawa, Fumihito Oka, Tadashi Sasaki
  • Patent number: 6690068
    Abstract: The TFT has a channel-forming region formed of a crystalline semiconductor film obtained by heat-treating and crystallizing an amorphous semiconductor film containing silicon as a main component and germanium in an amount of not smaller than 0.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: February 10, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Toru Mitsuki, Kenji Kasahara, Taketomi Asami, Tamae Takano, Takeshi Shichi, Chiho Kokubo, Yasuyuki Arai
  • Patent number: 6680485
    Abstract: A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The silicon based thin film transistor produced by the process includes a low temperature substrate incapable of withstanding sustained processing temperatures greater than about 250° C., an insulating layer on the substrate, a layer of silicon on the insulating layer having sections of doped silicon, undoped silicon, and poly-silicon, a gate dielectric layer on the layer of silicon, a layer of gate metal on the dielectric layer, a layer of oxide on sections of the layer of silicon and the layer of gate metal, and metal contacts on sections of the layer of silicon and layer of gate metal defining source, gate, and drain contacts, and interconnects.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: January 20, 2004
    Assignee: The Regents of the University of California
    Inventors: Paul G. Carey, Patrick M. Smith, Thomas W. Sigmon, Randy C. Aceves
  • Patent number: 6677611
    Abstract: A practical operational amplifier circuit is formed using thin film transistors. An operational amplifier circuit is formed by thin film transistors formed on a quartz substrate wherein 90% or more of n-channel type thin film transistors have mobility at a value of 260 cm2/Vs or more and wherein 90% or more of p-channel type thin film transistors have mobility at a value of 150 cm2/Vs or more. The thin film transistors have active layers formed using a crystalline silicon film fabricated using a metal element that promoted crystallization of silicon. The crystalline silicon film is a collection of a multiplicity of elongate crystal structures extending in a certain direction, and the above-described characteristics can be achieved by matching the extending direction and the moving direction of carriers.
    Type: Grant
    Filed: September 4, 2001
    Date of Patent: January 13, 2004
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Hisashi Ohtani
  • Patent number: 6670639
    Abstract: The present invention relates to a copper interconnection comprising a copper or copper alloy layer, wherein at least 50% of crystal grains of copper or a copper alloy form twins. A copper interconnection of the present invention is, therefore, highly reliable, and, a production cost thereof is low.
    Type: Grant
    Filed: December 11, 2001
    Date of Patent: December 30, 2003
    Assignee: NEC Corporation
    Inventors: Hidekazu Okabayashi, Akiko Fujii, Kazuyoshi Ueno, Shuichi Saito
  • Patent number: 6670638
    Abstract: Disclosed is a polysilicon film adapted for use in a liquid crystal display, and method of manufacturing such film. In manufacturing the film, a native oxide layer formed on a surface of an amorphous silicon film is completely removed by a hydrofluoric acid solution, followed by immersing in an H2O2 solution to newly form an extremely thin oxide layer, prior to a crystallizing processing performed by a laser beam irradiation. The crystallizing processing forms a polysilicon film formed of crystal grains Preferentially oriented on the (111) plane in a direction parallel to the substrate surface, an average crystal grain size being not larger than 300 nm, the standard deviation of the grain sizes being not larger than 30% of the average grain size, and the standard deviation of the roughness being not larger than 10% of the average grain size.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: December 30, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Takuo Tamura, Kiyoshi Ogata, Yoichi Takahara, Hironaru Yamaguchi, Yoshinobu Kimura, Makoto Ohkura, Hironobu Abe, Shigeo Shimomura, Masakazu Saitou, Michiko Takahashi
  • Patent number: 6657227
    Abstract: An amorphous silicon film is laser irradiated a plural number of times to make the film composed of a plurality of crystal grains while suppressing the formation of protrusions at the boundaries of the adjoining grains to realize a polycrystalline silicon thin film transistor having at least partly therein the clusters of grains, or the aggregates of at least two crystal grains, with preferred orientation in the plane (111), and having high electron mobility of 200 cm2/Vs or above.
    Type: Grant
    Filed: July 19, 2001
    Date of Patent: December 2, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Takuo Tamura, Kiyoshi Ogata, Yoichi Takahara, Kazuhiko Horikoshi, Hironaru Yamaguchi, Makoto Ohkura, Hironobu Abe, Masakazu Saitou, Yoshinobu Kimura, Toshihiko Itoga
  • Publication number: 20030218171
    Abstract: An objective is to provide a method of manufacturing a semiconductor device, and a semiconductor device manufactured by using the manufacturing method, in which a laser crystallization method is used that is capable of preventing the formation of grain boundaries in TFT channel formation regions, and is capable of preventing conspicuous drops in TFT mobility, reduction in the ON current, and increases in the OFF current, all due to grain boundaries. Stripe shape or rectangular shape unevenness or opening is formed. Continuous wave laser light is then irradiated to a semiconductor film formed on an insulating film. Note that although it is most preferable to use continuous wave laser light at this point, pulse wave oscillation laser light may also be used.
    Type: Application
    Filed: January 28, 2003
    Publication date: November 27, 2003
    Inventors: Atsuo Isobe, Shunpei Yamazaki, Chiho Kokubo, Koichiro Tanaka, Akihisa Shimomura, Tatsuya Arao, Hidekazu Miyairi, Mai Akiba
  • Patent number: 6653554
    Abstract: A thin film polycrystalline solar cell which includes a substrate, a first semiconductor layer provided on the substrate and including Si highly doped with a conductivity-type controlling impurity, a second semiconductor layer provided on the first semiconductor layer and including polycrystalline Si slightly doped with a conductivity-type controlling impurity of the same conductivity-type as that of the first semiconductor layer, and a third semiconductor layer provided on the second semiconductor layer and highly doped with a conductivity-type controlling impurity of a conductivity-type opposite to that of the impurities for the doping of the first and the second semiconductor layers. Crystal grains grown from crystal nuclei generated in the first semiconductor layer are continuously grown to form the first and second semiconductor layers, are horizontally grown to contact neighboring crystal grains, and are perpendicularly grown to form an interface with the third semiconductor layer.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: November 25, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shunichi Ishihara
  • Patent number: 6653657
    Abstract: To provide a TFT that can operate at a high speed by forming a crystalline semiconductor film while controlling the position and the size of a crystal grain in the film to use the crystalline semiconductor film for a channel forming region of the TFT. Instead of a metal or a highly heat conductive insulating film, only a conventional insulating film is used as a base film to introduce a temperature gradient. A level difference of the base insulating film is provided in a desired location to generate the temperature distribution in the semiconductor film in accordance with the arrangement of the level difference. The starting point and the direction of lateral growth are controlled utilizing the temperature distribution.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: November 25, 2003
    Assignee: Semoconductor Energy Laboratory Co., Ltd.
    Inventors: Ritsuko Kawasaki, Kenji Kasahara, Hisashi Ohtani
  • Publication number: 20030213957
    Abstract: In a thin film semiconductor device according to the present invention, a continuous oscillating light beam from a solid laser or the like is modulated on time axis and spatially, thereby realizing crystal growth that is nearly optimum for a crystal structure and a growth speed of crystals in a Sin thin film. Crystal grains with a large diameter, flatness with no projections at their grain boundaries, and controlled surface orientations are thereby formed. By forming channels with these crystal grains, high-mobility semiconductor devices and an image display device using these semiconductor devices are realized.
    Type: Application
    Filed: May 16, 2003
    Publication date: November 20, 2003
    Inventors: Shinya Yamaguchi, Mutsuko Hatano, Mitsuharu Tai, Sedng-Kee Park, Takeo Shiba
  • Publication number: 20030201441
    Abstract: A semiconductor light emitting device of the present invention includes: a substrate; a light emitting layer; a semiconductor layer of a hexagonal first III-group nitride crystal; and a cladding layer of a second III-group nitride crystal. A stripe groove is provided in the semiconductor layer along a <1, 1, −2, 0> direction.
    Type: Application
    Filed: April 2, 2003
    Publication date: October 30, 2003
    Inventors: Shinji Nakamura, Masahiro Ishida, Masaaki Yuri, Osamu Imafuji, Kenji Orita
  • Patent number: 6635899
    Abstract: In a semiconductor element comprising microcrystalline semiconductor, a semiconductor junction is provided within a microcrystal grain. Further, in a semiconductor element comprising microcrystalline semiconductor, providing microcrystal grains of different grain diameters as a mixture to form a semiconductor layer. Thereby, discontinuity of a semiconductor junction is improved to improve the characteristics, durability, and heat resisting properties of a semiconductor element. Distortion in a semiconductor layer is also reduced.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: October 21, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keishi Saito, Masafumi Sano
  • Patent number: 6627919
    Abstract: A thermally stable nickel germanosilicide on SiGe integrated circuit device, and a method of making the same, is disclosed. During fabrication of the device iridium or cobalt is added at the Ni/SiGe interface to decrease the sheet resistance of the device. The device comprising nickel silicide with iridium on SiGe shows thermal stability at temperatures up to 800° C. The device comprising nickel silicide with cobalt on SiGe shows a decrease in the sheet resistance with temperature, i.e., the resistance remains low when annealing temperatures extend up to and beyond 800° C.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: September 30, 2003
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Jer-shen Maa, Douglas James Tweet, Sheng Teng Hsu
  • Publication number: 20030160239
    Abstract: A crystalline semiconductor having an even surface and a large crystal grain size is formed on an economical glass substrate using a laser crystallizing technology. A series of processes, including forming an insulation film on a glass substrate; forming a semiconductor film in the first layer; crystallizing the semiconductor film in the first layer by irradiating laser light stepwise from weak energy laser light to strong energy laser light; forming a semiconductor film in a second layer having a film thickness thinner than that of the semiconductor film in the first layer; performing laser crystallization of the semiconductor thin film in the second layer by irradiating laser light stepwise from weak energy laser light to strong energy laser light, are continuously performed without exposing the workpiece to the atmosphere.
    Type: Application
    Filed: March 17, 2003
    Publication date: August 28, 2003
    Inventors: Youmei Shinagawa, Akio Mimura, Genshiro Kawachi, Takeshi Satoh
  • Patent number: 6610996
    Abstract: Semiconductor devices based on thin film transistors formed over substrates. In one embodiment, a semiconductor device comprises at least two thin film transistors formed over a substrate, each of said thin film transistors having a crystalline semiconductor film comprising silicon formed on an insulating surface as an active region thereof, wherein said crystalline semiconductor film of each of said two thin film transistors has substantially no grain boundary therein, and a crystal axis of said crystalline semiconductor film in one of said two thin film transistors deviates from a crystal axis of the crystalline semiconductor film of the other, and the deviation of the crystal axis is within ±10°.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: August 26, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Akiharu Miyanaga, Satoshi Teramoto
  • Patent number: 6608325
    Abstract: A semiconductor device having high carrier mobility, which comprises a substrate provided thereon a base film and further thereon a crystalline non-single crystal silicon film by crystal growth, wherein, the crystals are grown along the crystallographic [110] axis, and source/drain regions are provided approximately along the direction of carrier movement which coincides to the direction of crystal growth. Moreover, the electric conductivity along this direction of crystal growth is higher than any in other directions.
    Type: Grant
    Filed: January 5, 2000
    Date of Patent: August 19, 2003
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hongyong Zhang, Toru Takayama, Yasuhiko Takemura, Akiharu Miyanaga, Hisashi Ohtani
  • Patent number: 6608326
    Abstract: A crystalline semiconductor having an even surface and a large crystal grain size is formed on an economical glass substrate using a laser crystallizing technology. A series of processes, including forming an insulation film on a glass substrate; forming a semiconductor film in the first layer; crystallizing the semiconductor film in the first layer by irradiating laser light stepwise from weak energy laser light to strong energy laser light; forming a semiconductor film in a second layer having a film thickness thinner than that of the semiconductor film in the first layer; performing laser crystallization of the semiconductor thin film in the second layer by irradiating laser light stepwise from weak energy laser light to strong energy laser light, are continuously performed without exposing the workpiece to the atmosphere.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: August 19, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Youmei Shinagawa, Akio Mimura, Genshiro Kawachi, Takeshi Satoh
  • Patent number: 6605498
    Abstract: A stressed channel is formed in a PMOS transistor by etching a recess and subsequently backfilling the recess with an epitaxially formed alloy of silicon, germanium, and an n-type dopant. The alloy has the same crystal structure as the underlying silicon, but the spacing of the crystal is larger, due to the inclusion of the germanium. An NMOS transistor can be formed by including carbon instead of germanium.
    Type: Grant
    Filed: March 29, 2002
    Date of Patent: August 12, 2003
    Assignee: Intel Corporation
    Inventors: Anand S. Murthy, Brian S. Doyle, Brian E. Roberds
  • Patent number: 6602671
    Abstract: A novel encoding system, compositions for use therein and methods for determining the source, location and/or identity of a particular item or component of interest is provided. In particular, the present invention utilizes a collection of one or more sizes of populations of semiconductor nanocrystals having characteristic spectral emissions, to “track” the source or location of an item of interest or to identify a particular item of interest. The semiconductor nanocrystals used in the inventive compositions can be selected to emit a desired wavelength to produce a characteristic spectral emission in narrow spectral widths, and with a symmetric, nearly Gaussian line shape, by changing the composition and size of the semiconductor nanocrystal. Additionally, the intensity of the emission at a particular characteristic wavelength can also be varied, thus enabling the use of binary or higher order encoding schemes.
    Type: Grant
    Filed: September 17, 1999
    Date of Patent: August 5, 2003
    Assignee: Massachusetts Institute of Technology
    Inventors: Moungi G. Bawendi, Klavs F. Jensen
  • Publication number: 20030141503
    Abstract: A polycrystalline silicon thin film for a TFT and a display device using the same where the number of crystal grain boundaries exerts a fatal influence on movement of electric charge carrier, providing a distance “S” between active channels of the TFT having dual or multiple channels with a relation S=mGs·sec &thgr;−L, and also providing a display device in which uniformity of TFT characteristics is improved by synchronizing the number of the crystal grain boundaries included in each of the channels of the dual or multiple channels
    Type: Application
    Filed: November 19, 2002
    Publication date: July 31, 2003
    Applicant: Samsung SDI Co., Ltd.
    Inventor: Ki-Yong Lee
  • Publication number: 20030132437
    Abstract: The present invention provides a method for crystallizing a polycrystalline silicon layers used for the material of thin film transistors at large size (more than 8 microns) with crystal orientation aligned to a specific orientation, and for controlling the positioning of crystal grains at high precision. On a polycrystalline silicon layer, projections at regular intervals are formed by using anisotropic etching and a photomask. The tip of projections is comprised of single crystal silicon of a specific crystal orientation selectively left by the anisotropic etching, which is a candidate for nuclei of amorphous silicon to be deposited thereon. By iterating above process at a plurality of times, and by gradually enlarging the interval, span, size and height of projections, the size of crystal grains of silicon at the surface may be enlarged to the extent required. Thereby silicon crystal grains of large grains with crystal orientation aligned may be formed at controllable positions.
    Type: Application
    Filed: January 30, 2003
    Publication date: July 17, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Shinya Yamaguchi, Masanobu Miyao, Kiyokazu Nakagawa, Nobuyuki Sugii
  • Publication number: 20030122129
    Abstract: Phosphorus is implanted into a crystalline semiconductor film by an ion dope method. However, a concentration of phosphorus required for gettering is 1×1020/cm3 or higher which hinders recrystallization by later anneal, and thus this becomes a problem. Also, when phosphorus is added at a high concentration, processing time required for doping is increased and throughput in a doping step is reduced, and thus this becomes a problem. The present invention is characterized in that impurity regions to which an element belonging to the group 18 of the periodic table is added are formed in a semiconductor film having a crystalline structure and gettering for segregating in the impurity regions a metal element contained in the semiconductor film is performed by heat treatment. Also, a one conductivity type impurity may be contained in the impurity regions.
    Type: Application
    Filed: December 19, 2001
    Publication date: July 3, 2003
    Inventors: Shunpei Yamazaki, Osamu Nakamura, Masayuki Kajiwara, Junichi Koezuka
  • Publication number: 20030111665
    Abstract: A method of forming a periodic index of refraction pattern in a superlattice of a solid material to achieve photonic bandgap effects at desired optical wavelengths is disclosed. A plurality of space group symmetries, including a plurality of empty-spaced buried patterns, are formed by drilling holes in the solid material and annealing the solid material to form empty-spaced patterns of various geometries. The empty-spaced patterns may have various sizes and may be formed at different periodicities, so that various photonic band structures can be produced for wavelength regions of interest.
    Type: Application
    Filed: November 26, 2002
    Publication date: June 19, 2003
    Inventors: Joseph E. Geusic, Kevin G. Donohoe
  • Patent number: 6576831
    Abstract: Directionally solidified, multicrystalline silicon having a low proportion of electrically active grain borders, its manufacturing and utilisation, as well as solar cells comprising said silicon and a method of manufacturing said cells.
    Type: Grant
    Filed: November 14, 2001
    Date of Patent: June 10, 2003
    Assignee: Deutsche Solar GmbH
    Inventors: Peter Woditsch, Gunther Stollwerck, Christian Hässler, Wolfgang Koch
  • Publication number: 20030104662
    Abstract: A thin film semiconductor device has a semiconductor thin film with a film thickness of 200 nm or less. The semiconductor thin film is formed over a dielectric substrate with a warping point of 600° C. or lower. The semiconductor thin film has a region in which a first semiconductor thin film region with the defect density of 1×1017 cm−3 or less and a second semiconductor thin film region with the defect density of 1×1017 cm−3 or more are disposed alternately in the form of stripes. The width of the first semiconductor thin film region is larger than the width of the semiconductor thin film region. The grain boundaries, grain size and orientation of crystals over the dielectric substrate are controlled, so that a high quality thin film semiconductor device is obtained.
    Type: Application
    Filed: July 5, 2002
    Publication date: June 5, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Mutsuko Hatano, Shinya Yamaguchi, Takeo Shiba
  • Publication number: 20030096098
    Abstract: A non-single crystalline semiconductor material includes coordinatively irregular structures characterized by distorted chemical bonding, reduced dimensionality and novel electronic properties. A process for forming the material permits variation of the size, concentration and spatial distribution of coordinatively irregular structures. The electronic properties of the material can be changed by controlling the characteristics of the coordinatively irregular structures.
    Type: Application
    Filed: October 5, 2001
    Publication date: May 22, 2003
    Inventors: Stanford R. Ovshinsky, Boil Pashmakov, David V. Tsu
  • Patent number: 6566173
    Abstract: The present invention discloses a polycrystalline silicon thin film transistor connected to a gate line and a data line that includes a source electrode contacting the data line; a gate electrode contacting the gate line; a drain electrode spaced apart from the source electrode; a polysilicon layer positioned between and contacting the source and the drain electrodes, and acting as a channel area in which electrons flow; at least one metal layer positioned near the polysilicon layer and parallel to a flow direction of the electrons; and a buffer layer interposed between the metal layer and the polysilicon layer.
    Type: Grant
    Filed: March 17, 2000
    Date of Patent: May 20, 2003
    Assignee: LG Philips LCD Co., Ltd.
    Inventor: Jaebeom Choi
  • Patent number: 6555844
    Abstract: A transistor device that includes at least two transistors, each transistor including a source region, a drain region, and a shallow trench isolation formed between and contiguous with the source and drain regions, wherein the shallow trench isolation electrically isolates the source and drain regions to minimize the short-channel effects, a conductor layer disposed over the source region, shallow trench isolation, and drain region, wherein the conductor layer electrically connects the source and drain regions to serve as a channel region, a gate oxide disposed over the conductor layer, and a gate structure formed over the gate oxide.
    Type: Grant
    Filed: March 21, 2002
    Date of Patent: April 29, 2003
    Assignee: Macronix International Co., Ltd.
    Inventors: Hung-Sui Lin, Han Chao Lai, Tao Cheng Lu
  • Publication number: 20030075717
    Abstract: The present invention provides a semiconductor element comprising a semiconductor junction composed of silicon-based films, the element being characterized in that at least one of the silicon-based films contains a microcrystal, and microcrystal located in at least one interface region of the silicon-based films containing the microcrystal has no orientation property. Further, the present invention provides a semiconductor element comprising a semiconductor junction composed of silicon-based films, wherein at least one of the silicon-based films contains a microcrystal, and the orientation property of the microcrystal in the silicon-based film containing the microcrystal changes in a film thickness direction of the silicon-based film containing the microcrystal.
    Type: Application
    Filed: March 8, 2002
    Publication date: April 24, 2003
    Inventors: Takaharu Kondo, Shotaro Okabe, Masafumi Sano, Akira Sakai, Ryo Hayashi, Shuichiro Sugiyama