Abstract: A first semiconductor zone of a first conduction type is formed from a semiconductor base material doped with first and second dopants. The first and second dopants are different substances and also different from the semiconductor base material. The first dopant is electrically active and causes a doping of the first conduction type in the semiconductor base material, and causes either a decrease or an increase of a lattice constant of the pure, undoped first semiconductor zone. The second dopant may be electrically active, and may be of the same doping type as the first dopant, causes one or both of: a hardening of the first semiconductor zone; an increase of the lattice constant of the pure, undoped first semiconductor zone if the first dopant causes a decrease, and a decrease of the lattice constant of the pure, undoped first semiconductor zone if the first dopant causes an increase, respectively.

Abstract: Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing platinum- or gold-comprising residues remaining on the one of the first and second surfaces after diffusing the platinum or gold, forming a phosphorus- or boron-doped surface barrier layer on the first or second surface, and heating the semiconductor substrate for local gettering of the platinum or gold by the phosphorus- or boron-doped surface barrier layer.

Abstract: Provided is a method for manufacturing a semiconductor device. Also provided are: a semiconductor device which can be obtained by the method; and a dispersion that can be used in the method. A method for manufacturing a semiconductor device (500a) of the present invention comprises the steps (a)-(c) described below and is characterized in that the crystal orientation of a first dopant implanted layer (52) is the same as the crystal orientation of a semiconductor layer or a base (10) that is formed of a semiconductor element. (a) A dispersion which contains doped particles is applied to a specific part of a layer or a base. (b) An unsintered dopant implanted layer is obtained by drying the applied dispersion. (c) The specific part of the layer or the base is doped with a p-type or n-type dopant by irradiating the unsintered dopant implanted layer with light, and the unsintered dopant implanted layer is sintered, thereby obtaining a dopant implanted layer that is integrated with the layer or the base.

Abstract: The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.

Abstract: Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM's, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET's, and a host of other applications.

Abstract: A semiconductor device having a trench gate structure is formed by self alignment. The manufacturing method of the semiconductor device includes: forming a control electrode in an interior of trenches, etching a semiconductor layer between adjacent trenches to form an opening having a depth that is about level with an upper end of the control electrode with a portion of the semiconductor layer remaining between the opening and the control electrode, forming a first semiconductor region of the second conductive type from the surface of the semiconductor layer to a depth above the lower end of the control electrode, forming a single crystallized conductive layer from the first semiconductor region and the portion of the semiconductor layer, and forming a second semiconductor region, the second semiconductor region including the portion of the semiconductor layer and the single crystallized portion of the conductive layer.

Abstract: A semiconductor device includes a drift zone of a first conductivity type formed within a semiconductor body, wherein one side of opposing sides of the drift zone adjoins a first zone within the semiconductor body and the other side adjoins a second zone within the semiconductor body. First semiconductor subzones of a second conductivity type different from the first conductivity type are formed within each of the first and second zones opposing each other along a lateral direction extending parallel to a surface of the semiconductor body. A second semiconductor subzone is formed within each of the first and second zones and between the first semiconductor subzones along the lateral direction. An average concentration of dopants within the second semiconductor subzone along 10% to 90% of an extension of the second semiconductor subzone along a vertical direction perpendicular to the surface is smaller than the average concentration of dopants along a corresponding section of extension within the drift zone.

Abstract: An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a second node, wherein the ESD protection device may be configured to sink current from the first node to the second node in response to an ESD event. The transistors may be coupled such that a collector of the NPN may be coupled to the first node. A collector of the PNP may be coupled to the second node. A base of the NPN may be coupled to the emitter of the PNP. An emitter of the NPN may be coupled to a base of the PNP.

Abstract: A wafer, a fabricating method of the same, and a semiconductor substrate are provided. The wafer includes a first substrate layer formed at a first surface, a second substrate layer formed at a second surface opposite to the first surface, the second substrate layer having a greater oxygen concentration than the first substrate layer, and an oxygen diffusion protecting layer formed between the first substrate layer and the second substrate layer, the oxygen diffusion protecting layer being located closer to the first surface than to the second surface.

Abstract: Methods of forming and tuning a multilayer select device are provided, along with apparatus and systems which include them. As is broadly disclosed in the specification, one such method can include forming a first region having a first conductivity type; forming a second region having a second conductivity type and located adjacent to the first region; and forming a third region having the first conductivity type and located adjacent to the second region and, such that the first, second and third regions form a structure located between a first electrode and a second electrode, wherein each of the regions have a thickness configured to achieve a current density in a range from about 1×e4 amps/cm2 up to about 1×e8 amps/cm2 when a voltage in a selected voltage range is applied between the first electrode and the second electrode.

Abstract: A semiconductor apparatus includes a p-type doped layer, an n-type doped layer, and an internal electrical connection layer that is deposited and electrically coupled between the p-type doped layer and the n-type doped layer. In one embodiment, the internal electrical connection layer includes a group IV element and a nitrogen element, and the number of atoms of the group IV element and the nitrogen element is greater than 50% of the total number of atoms in the internal electrical connection layer. In another embodiment, the internal electrical connection layer includes carbon element with a concentration greater than 1017 atoms/cm3. In a further embodiment, the internal electrical connection layer is formed at a temperature lower than those of the p-type doped layer and the n-type doped layer.

Abstract: A thin film transistor with favorable electric characteristics is provided. The thin film transistor includes a gate electrode, a gate insulating layer, a semiconductor layer which includes a microcrystalline semiconductor region and an amorphous semiconductor region, an impurity semiconductor layer, a wiring, a first oxide region provided between the microcrystalline semiconductor region and the wiring, and a second oxide region provided between the amorphous semiconductor region and the wiring, wherein a line tangent to the highest inclination of an oxygen profile in the first oxide region (m1) and a line tangent to the highest inclination of an oxygen profile in the second oxide region (m2) satisfy a relation of 1<m1/m2<10, on the semiconductor layer side from an intersection of a profile of an element included in the wiring and a profile of an element included in the semiconductor layer.

Abstract: An ingot, a substrate, and a substrate group are obtained each of which is made of silicon carbide and is capable of suppressing variation of characteristics of semiconductor devices. The ingot is made of single-crystal silicon carbide, and has p type impurity. The ingot has a thickness of 10 mm or greater in a growth direction thereof. Further, the ingot has an average carrier density of 1×1016 cm?3or greater. Further, the ingot has a carrier density fluctuating in the growth direction by ±80% or smaller relative to the average carrier density. In this way, variation of carrier density among substrates obtained from the ingot is suppressed, thereby suppressing variation of characteristics of semiconductor devices manufactured using the substrates.

Abstract: A substrate is treated by means of at least one pulse of a luminous flux of determined wavelength. The substrate comprises an embedded layer that absorbs the luminous flux independently of the temperature. The embedded layer is interleaved between a first treatment layer, layer and a second treatment layer. The first treatment layer has a coefficient of absorption of luminous flux that is low at ambient temperature and grows as the temperature rises. The luminous flux may be applied in several places of the surface of the first layer to heat regions of the embedded layer and generate a propagating thermal front in the first layer opposite the heated regions of the embedded layer, which generate constraints within the second layer.

Abstract: A semiconductor substrate includes a first side and a second side opposite the first side. A semiconductor material extends between the first and second sides and is devoid of active device regions. The semiconductor material has a first region and a second region. The first region extends from the first side to a depth into the semiconductor material and includes chalcogen dopant atoms which provide a base doping concentration for the first region. The second region extends from the first region to the second side and is devoid of base doping. Further, a power semiconductor component is provided.

Abstract: A semiconductor component is disclosed. One embodiment provides a semiconductor body having a cell region with at least one zone of a first conduction type and at least one zone of a second conduction type in a rear side. A drift zone of the first conduction type in the cell region is provided. The drift zone contains at least one region through which charge carriers flow in an operating mode of the semiconductor component in one polarity and charge carriers do not flow in an operating mode of the semiconductor component in an opposite polarity.

Abstract: A compound semiconductor device includes: a first compound semiconductor layer in which carriers are formed; a second compound semiconductor layer, provided above the first compound semiconductor layer, to supply the carriers; and a third compound semiconductor layer provided above the second compound semiconductor layer, wherein the third compound semiconductor layer includes a area that has a carrier concentration higher than a carrier concentration of the second compound semiconductor layer.

Abstract: According to one embodiment, an information recording and reproducing device includes a recording layer which includes a typical element and a transition element, and stores a state of a first electric resistivity and a state of a second electric resistivity different from the first electric resistivity by a movement of the typical element, and an electrode layer which is disposed at one end of the recording layer to apply a voltage or a current to the recording layer. The recording layer includes a first region which is in contact with the electrode layer and the electrode layer includes a second region which is in contact with the recording layer. The first and second regions are opposite to each other. And the first and second regions include the typical element, and a concentration of the typical element in the second region is higher than that in the first region.

Abstract: An ESD protection device includes a semiconductor body, a gate formed over a channel in the semiconductor body, the channel being doped with a first concentration of dopants of a first conductivity type. A first source/drain region is formed on the surface of the semiconductor body adjacent to a first edge of the gate, wherein the first source/drain region is doped with a dopant of a second conductivity type opposite the first conductivity type, and at least a portion of the first source/drain region is doped with a dopant of the first conductivity type. The concentration of the second conductivity type dopant exceeds the concentration of the first conductivity type dopant, and the concentration of the first conductivity type dopant in the first source/drain exceeds the first concentration.

Abstract: A semiconductor device includes: an N-type drift layer; a P-type anode layer above the N-type drift layer; an N-type cathode layer below the N-type drift layer; a first short lifetime layer between the N-type drift layer and the P-type anode layer; and a second short lifetime layer between the N-type drift layer and the N-type cathode layer. A carrier lifetime in the first and second short lifetime layers is shorter than a carrier lifetime in the N-type drift layer. A carrier lifetime in the N-type cathode layer is longer than the carrier lifetime in the N-type drift layer.

Abstract: Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By grading the dopant concentration, the performance in various semiconductor devices can be significantly improved. Performance improvements can be obtained in application specific areas like increase in frequency of operation for digital logic, various power MOSFET and IGBT ICS, improvement in refresh time for DRAM's, decrease in programming time for nonvolatile memory, better visual quality including pixel resolution and color sensitivity for imaging ICs, better sensitivity for varactors in tunable filters, higher drive capabilities for JFET's, and a host of other applications.

Abstract: A semiconductor device includes a drift zone of a first conductivity type formed within a semiconductor body, wherein one side of opposing sides of the drift zone adjoins a first zone within the semiconductor body and the other side adjoins a second zone within the semiconductor body. First semiconductor subzones of a second conductivity type different from the first conductivity type are formed within each of the first and second zones opposing each other along a lateral direction extending parallel to a surface of the semiconductor body. A second semiconductor subzone is formed within each of the first and second zones and between the first semiconductor subzones along the lateral direction. An average concentration of dopants within the second semiconductor subzone along 10% to 90% of an extension of the second semiconductor subzone along a vertical direction perpendicular to the surface is smaller than the average concentration of dopants along a corresponding section of extension within the drift zone.

Abstract: New designs for silicon carbide (SiC) bipolar junction transistors (BJTs) and new methods of manufacturing such SiC BJTs are provided. The SiC BJT can include a collector region, a base region, and an emitter region where the collector region, the base region, and the emitter region are arranged as a stack. The emitter region can form an elevated structure defined by outer sidewalls disposed on the stack. The base region can have a portion interfacing the emitter region and defining an intrinsic base region. The intrinsic base region can include a first portion laterally spaced away from the outer sidewalls of the emitter region by a second portion of the base region that has a dopant dose higher than a dopant dose of the first portion.

Abstract: A semiconductor component having at least one pn junction and an associated production method. The semiconductor component has a layer sequence of a first zone having a first dopant. The first zone faces a first main area. Adjacent to the first zone are a second zone having a low concentration of a second dopant, a subsequent buffer layer, the third zone, also having the second dopant and a subsequent fourth zone having a high concentration of the second dopant. The fourth zone faces a second main area. In this case, the concentration of the second doping of the buffer layer is higher at the first interface of the barrier layer with the second zone than at the second interface with the fourth zone. According to the invention, the buffer layer is produced by ion implantation.

Abstract: A semiconductor device with a lateral element includes a semiconductor substrate, first and second electrodes on the substrate, and a resistive field plate extending from the first electrode to the second electrode. The lateral element passes a current between the first and second electrodes. A voltage applied to the second electrode is less than a voltage applied to the first electrode. The resistive field plate has a first end portion and a second end portion opposite to the first end portion. The second end portion is located closer to the second electrode than the first end portion. An impurity concentration in the second end portion is equal to or greater than 1×1018 cm?3.

Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided.

Abstract: There are disclosed herein various implementations of a semiconductor structure and method. The semiconductor structure comprises a substrate, a transition body over the substrate, and a group III-V intermediate body having a bottom surface over the transition body. The semiconductor structure also includes a group III-V device layer over a top surface of the group III-V intermediate body. The group III-V intermediate body has a continuously reduced impurity concentration wherein a higher impurity concentration at the bottom surface is continuously reduced to a lower impurity concentration at the top surface.

Abstract: A fast recovery diode includes an n-doped base layer having a cathode side and an anode side opposite the cathode side. A p-doped anode layer is arranged on the anode side. The anode layer has a doping profile and includes at least two sublayers. A first one of the sublayers has a first maximum doping concentration, which is between 2*1016 cm?3 and 2*1017 cm?3 and which is higher than the maximum doping concentration of any other sublayer. A last one of the sublayers has a last sublayer depth, which is larger than any other sublayer depth. The last sublayer depth is between 90 to 120 ?m. The doping profile of the anode layer declines such that a doping concentration in a range of 5*1014 cm?3 and 1*1015 cm?3 is reached between a first depth, which is at least 20 ?m, and a second depth, which is at maximum 50 ?m. Such a profile of the doping concentration is achieved by using aluminum diffused layers as the at least two sublayers.

Abstract: System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate.

Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

Abstract: A bonded wafer structure having a handle wafer, a device wafer, and an interface region with an abrupt transition between the conductivity profile of the device wafer and the handle wafer is used for making semiconductor devices. The improved doping profile of the bonded wafer structure is well suited for use in the manufacture of integrated circuits. The bonded wafer structure is especially suited for making radiation-hardened integrated circuits.

Abstract: A method for producing a semiconductor includes providing a p-doped semiconductor body having a first side and a second side; implanting protons into the semiconductor body via the first side to a target depth of the semiconductor body; bonding the first side of the semiconductor body to a carrier substrate; forming an n-doped zone in the semiconductor body by heating the semiconductor body such that a pn junction arises in the semiconductor body; and removing the second side of the semiconductor body at least as far as a space charge zone spanned at the pn junction.

Abstract: A semiconductor substrate (100) has three doped zones (1), (2) and (3), forming a P-N junction (101), the third zone being located between the first zone and the second zone. The P-N junction of the substrate further has a fourth doped zone (4) having a first portion (4A) in contact with the first zone; and a second portion (4B) in contact with the third zone (3), said second portion (4B) extending in the direction of the second zone (2), and not being in contact with the second zone (2); where the fourth zone (4) being doped with the same type of doping as that of the first zone.

Abstract: A semiconductor device includes: a first semiconductor layer; a first electrode provided on a first surface side of the first semiconductor layer; a first insulating layer; and a second semiconductor layer. The first insulating layer is provided between the first semiconductor layer and the first electrode and configured to constrict current flowing between the first semiconductor layer and the first electrode. The second semiconductor layer has a first conductivity type and is provided at least on a path of the current constricted by the first insulating layer. The second semiconductor layer is in contact with the first electrode. The second semiconductor layer contains first impurities at a concentration higher than a concentration of impurities contained in the first semiconductor layer.

Abstract: A semiconductor device with a high voltage compensation component is manufactured by etching a trench into an epitaxial semiconductor material doped with n-type dopant atoms and p-type dopant atoms and disposing a first semiconductor or insulating material along one or more sidewalls of the trench. The first semiconductor or insulating material has a dopant diffusion constant which is at least 2× different for the n-type dopant atoms than the p-type dopant atoms. A second semiconductor material is disposed in the trench along the first semiconductor or insulating material. The second semiconductor material has a different dopant diffusion constant than the first semiconductor or insulating material.

Abstract: An integrated circuit and method for making an integrated circuit including doping a semiconductor body is disclosed. One embodiment provides defect-correlated donors and/or acceptors. The defects required for this are produced by electron irradiation of the semiconductor body. Form defect-correlated donors and/or acceptors with elements or element compounds are introduced into the semiconductor body.

Abstract: A semiconductor chip includes a semiconductor body with a semiconductor layer sequence. An active region intended for generating radiation is arranged between an n-conductive multilayer structure and a p-conductive semiconductor layer. A doping profile is formed in the n-conductive multilayer structure which includes at least one doping peak.

Abstract: A memory cell is provided that includes a semiconductor pillar and a reversible state-change element coupled to the semiconductor pillar. The semiconductor pillar includes a heavily doped bottom region of a first conductivity type, a heavily doped top region of a second conductivity type, and a lightly doped or intrinsic middle region interposed between and contacting the top and bottom regions. The middle region comprises a first proportion of germanium, and either the top region or the bottom region comprises no germanium or comprises a second proportion of germanium less than the first proportion. The reversible state-change element includes a layer of a resistivity-switching metal oxide or nitride compound selected from the group consisting of NiO, Nb2O5, TiO2, HfO2, Al2O3, CoO, MgOx, CrO2, VO, BN, and AlN. Numerous other aspects are provided.

Abstract: According to an embodiment of the present invention, a thin film transistor array panel includes a gate line and a data line insulated from each other on an insulating substrate where the gate line and the data line cross each other to define a pixel region, a thin film transistor (TFT) disposed at an intersection of the gate line and the data line, a floating electrode where at least a portion of the floating electrode overlaps the data line, and a pixel electrode disposed at the pixel region where the pixel electrode is connected to the TFT and overlaps the at least a portion of the floating electrode.

Abstract: A field effect transistor includes a Schottky layer; a stopper layer formed of InGaP and provided in a recess region on the Schottky layer; a cap layer provided on the stopper layer and formed of GaAs; and a barrier rising suppression region configured to suppress rising of a potential barrier due to interface charge between the stopper layer and the cap layer. The cap layer includes a high concentration cap layer; and a low concentration cap layer provided directly or indirectly under the high concentration cap layer and having an impurity concentration lower than the high concentration cap layer.

Abstract: A p anode layer (2) is formed on one main surface of an n? drift layer (1). An n+ cathode layer (3) having an impurity concentration more than that of the n? drift layer (1) is formed on the other main surface of the n? drift layer (1). An anode electrode (4) is formed on the surface of the p anode layer (2). A cathode electrode (5) is formed on the surface of the n+ cathode layer (3). An n-type broad buffer region (6) that has a net doping concentration more than the bulk impurity concentration of a wafer and less than that of the n+ cathode layer (3) and the p anode layer (2) is formed in the n? drift layer (1). The resistivity ?0 of the n? drift layer (1) satisfies 0.12V0??0?0.25V0 with respect to a rated voltage V0. The total amount of the net doping concentration of the broad buffer region (6) is equal to or more than 4.8×1011 atoms/cm2 and equal to or less than 1.0×1012 atoms/cm2.

Abstract: The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities.

Abstract: An insulating film provided between adjacent pixels is referred to as a bank, a partition, a barrier, an embankment or the like, and is provided above a source wiring or a drain wiring for a thin film transistor, or a power supply line. In particular, at an intersection portion of these wirings provided in different layers, a larger step is formed there than in other portions. Even in a case that the insulating film provided between adjacent pixels is formed by a coating method, there is a problem that thin portions are partially formed due to this step and the withstand pressure is reduced. In the present invention, a dummy material is arranged near the large step portion, particularly, around the intersection portion of wirings, so as to alleviate unevenness formed thereover. The upper wring and the lower wiring are arranged in a misaligned manner so as not to align the end portions.

Abstract: The use of doped silicon nanoparticle inks and other liquid dopant sources can provide suitable dopant sources for driving dopant elements into a crystalline silicon substrate using a thermal process if a suitable cap is provided. Suitable caps include, for example, a capping slab, a cover that may or may not rest on the surface of the substrate and a cover layer. Desirable dopant profiled can be achieved. The doped nanoparticles can be delivered using a silicon ink. The residual silicon ink can be removed after the dopant drive-in or at least partially densified into a silicon material that is incorporated into the product device. The silicon doping is suitable for the introduction of dopants into crystalline silicon for the formation of solar cells.

Abstract: A semiconductor device has at least two main carbon-rich regions and two additional carbon-rich regions. The main carbon-rich regions are separately located in a substrate so that a channel region is located between them. The additional carbon-rich regions are respectively located underneath the main carbon-rich regions. The carbon concentrations is higher in the main carbon-rich regions and lower in the additional carbon-rich regions, and optionally, the absolute value of a gradient of the carbon concentration of the bottom portion of the main carbon-rich regions is higher than the absolute value of a gradient of the carbon concentration of the additional carbon-rich regions. Therefore, the leakage current induced by a lattice mismatch effect at the carbon-rich and the carbon-free interface can be minimized.

Abstract: A method of fabricating an integrated circuit on a compound semiconductor III-V wafer including at least two different types of active devices by providing a substrate; growing a first epitaxial structure on the substrate; growing a second epitaxial structure on the first epitaxial structure; and processing the epitaxial structures to form different types of active devices, such as HBTs and FETs.

Abstract: In a memory cell, the drive current capabilities of the transistors may be adjusted by locally providing an increased gate dielectric thickness and/or gate length of one or more of the transistors of the memory cell. That is, the gate length and/or the gate dielectric thickness may vary along the transistor width direction, thereby providing an efficient mechanism for adjusting the effective drive current capability while at the same time allowing the usage of a simplified geometry of the active region, which may result in enhanced production yield due to enhanced process uniformity. In particular, the probability of creating short circuits caused by nickel silicide portions may be reduced.

Abstract: A solar cell include a polycrystalline semiconductor substrate of a p-type, an emitter region of an n-type and forming a p-n junction with the polycrystalline semiconductor substrate, a first electrode connected to the emitter region, and a second electrode connected to the polycrystalline semiconductor substrate, wherein the polycrystalline semiconductor substrate has a pure p-type impurity concentration of substantially 7.2×1015/cm3 to 3.5×1016/cm3.

Abstract: An impurity doping system is disclosed, which includes an impurity doping device for doping an impurity into a surface of a solid state base body, a measuring device for measuring an optical characteristic of an area into which the impurity is doped, and an annealing device for annealing the area into which the impurity is doped. The impurity doping system realizes an impurity doping not to bring about a rise of a substrate temperature, and measures optically physical properties of a lattice defect generated by the impurity doping step to control such that subsequent steps are optimized.