With High Resistivity (e.g., "intrinsic") Layer Between P And N Layers (e.g., Pin Diode) Patents (Class 257/656)
  • Patent number: 10290711
    Abstract: The present invention relates to a vertical semiconductor device such as an IGBT or a diode which includes an N buffer layer formed in the undersurface of and adjacent to an N? drift layer. A concentration slope ?, which is derived from displacements in a depth TB (?m) and an impurity concentration CB (cm?3), from the upper surface to the lower surface in a main portion of the N buffer layer satisfies a concentration slope condition defined by {0.03???0.7}.
    Type: Grant
    Filed: January 27, 2015
    Date of Patent: May 14, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventor: Katsumi Nakamura
  • Patent number: 9960248
    Abstract: Methods for forming a fin-based RF diode with improved performance characteristics and the resulting devices are disclosed. Embodiments include forming fins over a substrate, separated from each other, each fin having a lower portion and an upper portion; forming STI regions over the substrate, between the lower portions of adjacent fins; implanting the lower portion of each fin with a first-type dopant; implanting the upper portion of each fin, above the STI region, with the first-type dopant; forming a junction region around a depletion region and along exposed sidewalls and a top surface of the upper portion of each fin; and forming a contact on exposed sidewalls and a top surface of each junction region.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: May 1, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Jagar Singh
  • Patent number: 9852981
    Abstract: An anti-fuse is provided above a semiconductor material. The anti-fuse includes a first end region including a first metal structure; a second end region including a second metal structure; and a middle region located between the first end region and the second end region. In accordance with the present application, the middle region of the anti-fuse includes at least a portion of the second metal structure that is located in a gap positioned between a bottom III-V compound semiconductor material and a top III-V compound semiconductor material. A high-k dielectric material liner separates the second metal structure from a portion of the first metal structure.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: December 26, 2017
    Assignee: International Business Machines Corporation
    Inventors: Praneet Adusumilli, Alexander Reznicek, Oscar van der Straten, Chih-Chao Yang
  • Patent number: 9818877
    Abstract: A shallow trench isolation layer is formed on a structure comprising semiconductor fins. Portions of the fins are recessed to a level below the shallow trench isolation layer. Epitaxial stressor regions are then formed on the recessed fin areas. A bottom portion of the epitaxial stressor regions are contained by the shallow trench isolation layer, which delays formation of the diamond shape as the epitaxial region is grown. Once the epitaxial stressor regions exceed the level of the shallow trench isolation layer, the diamond shape starts to form. The result of delaying the start of the diamond growth pattern is that the epitaxial regions are narrower for a given fin height. This allows for taller fins, which provide more current handling capacity, while the narrower epitaxial stressor regions enable a smaller fin pitch, allowing for increased circuit density.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz, Henry K. Utomo, Reinaldo Ariel Vega
  • Patent number: 9709739
    Abstract: A coupling module includes optical couplers that are coupled to waveguides. The optical couplers are configured to couple to cores of a multi-core optical fiber. The waveguides each include an external part extending from the module and an internal part extending into the module for connecting the external part to the associated optical coupler. The external part of some of the waveguides extends in a preferential direction, while the external part of others of the waveguides extends in a direction opposite to the preferential direction. The internal parts may include a curved portion configured for forming a turn-back.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: July 18, 2017
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Jean-Francois Carpentier, Patrick Le Maitre, Bertrand Borot
  • Patent number: 9704966
    Abstract: Methods for forming a fin-based RF diode with improved performance characteristics and the resulting devices are disclosed. Embodiments include forming fins over a substrate, separated from each other, each fin having a lower portion and an upper portion; forming STI regions over the substrate, between the lower portions of adjacent fins; implanting the lower portion of each fin with a first-type dopant; implanting the upper portion of each fin, above the STI region, with the first-type dopant; forming a junction region around a depletion region and along exposed sidewalls and a top surface of the upper portion of each fin; and forming a contact on exposed sidewalls and a top surface of each junction region.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: July 11, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Jagar Singh
  • Patent number: 9651838
    Abstract: The invention provides an array substrate and a manufacturing method thereof, a display panel and a display device, the array substrate includes a base substrate, and a data line, a switching device and a voltage compensation module arranged on the base substrate, the switching device is connected between the data line and the voltage compensation module so that the data line is electrically connected to the voltage compensation module when a voltage on the data line is lower than a preset low voltage or higher than a preset high voltage. The array substrate uses a PN junction as the switching device between the data line and the voltage compensation module, and due to a low leakage current between a P terminal and an N terminal of the PN junction, the power consumption of the array substrate can be reduced.
    Type: Grant
    Filed: July 16, 2015
    Date of Patent: May 16, 2017
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., ORDOS YUANSHENG OPTOELECTRONICS CO., LTD.
    Inventors: Yun Qiao, Jian Sun, Cheng Li, Seongjun An
  • Patent number: 9627412
    Abstract: The invention provides a high-precision display device having a reliable top- and single-gate TFT causing less current leakage. Part of a gate line 10 that crosses a semiconductor layer 103 acts as a gate electrode to form a TFT. The semiconductor layer 103 is connected to a data line 20 via a through-hole 140 on one side of the TFT and also connected to a contact electrode 107 via a through-hole 120 on the other side of the TFT. A floating electrode 30 is formed between the TFT and the through-hole 140 or between the TFT and the through-hole 120. The floating electrode 30 is formed on a layer above the semiconductor layer 103 with the use of the same material and at the same time as the gate electrode.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: April 18, 2017
    Assignee: Japan Display Inc.
    Inventor: Seiichi Uramoto
  • Patent number: 9627209
    Abstract: A method for producing a semiconductor is disclosed, the method having: providing a semiconductor body having a first side and a second side; forming an n-doped zone in the semiconductor body by a first implantation into the semiconductor body via the first side to a first depth location of the semiconductor body; and forming a p-doped zone in the semiconductor body by a second implantation into the semiconductor body via the second side to a second depth location of the semiconductor body, a pn-junction forming between said n-doped zone and said p-doped zone in the semiconductor body.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: April 18, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Hans-Joachim Schulze, Ingo Muri, Friedrich Kroener, Werner Schustereder
  • Patent number: 9553210
    Abstract: High frequency power diode including a semiconductor wafer having first and second main sides, a first layer of a first conductivity type formed on the first main side, a second layer of a second conductivity type formed on the second main side and a third layer of the second conductivity type formed between the first layer and the second layer. The first layer has a dopant concentration decreasing from 1019 cm?3 or more adjacent to the first main side of the wafer to 1.5·1015 cm?3 or less at an interface of the first layer with the third layer. The second layer has a dopant concentration decreasing from 1019 cm?3 or more adjacent to the second main side of the wafer to 1.5·1015 cm?3 at an interface of the second layer with the third layer and the third layer has a dopant concentration of 1.5·1015 cm?3 or less.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: January 24, 2017
    Assignee: ABB Schweiz AG
    Inventors: Jaroslav Homola, Jiri Podzemsky, Ladislav Radvan, Ilja Muller
  • Patent number: 9478662
    Abstract: One illustrative device disclosed herein includes, among other things, a dielectric layer disposed above a source/drain region and a gate structure of a transistor, a first conductive contact positioned in the dielectric layer and contacting the gate structure, wherein a first spacer is disposed on a sidewall of the first conductive contact, and a second conductive contact positioned in the dielectric layer and contacting the source/drain region, wherein the first spacer at least partially defines a spacing between the first conductive contact and the second conductive contact.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Andre Labonte, Ruilong Xie
  • Patent number: 9466361
    Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: October 11, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Patent number: 9412654
    Abstract: After forming a copper seed layer on a diffusion barrier layer present on sidewalls and a bottom surface of at least one opening, a graphene sacrificial layer is deposited over the copper seed layer before the copper seed layer is exposed to an environment that oxidizes the copper seed layer, thus providing process flexibility for longer queue times (Q-times) between copper seed layer deposition and copper plating. Next, the graphene sacrificial layer is subjected to a plasma treatment to introduce disorders and defects into the graphene sacrificial layer for removal just before the copper plating. The entire structure is then immersed in a copper plating solution. The copper plating solution dissolves the plasma treated graphene sacrificial layer and forms a copper-containing layer on the re-exposed copper seed layer.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: August 9, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Junjing Bao, Lawrence A. Clevenger, Vincent J. McGahay, Joyeeta Nag, Richard S. Wise, Yiheng Xu
  • Patent number: 9397206
    Abstract: A semiconductor device including a semiconductor substrate in which a diode region and an IGBT region are formed is provided. In the semiconductor device, the diode region includes a second conductivity type cathode layer. An impurity concentration of second conductivity type impurities of the cathode layer is distributed in a curve pattern having at least two peaks, and the impurity concentration of the second conductivity type impurities is higher than that of first conductivity type impurities at all depths of the cathode layer.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: July 19, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Satoru Kameyama
  • Patent number: 9368649
    Abstract: A schottky barrier diode includes an n? type epitaxial layer disposed at a first surface of an n+ type silicon carbide substrate, a plurality of n type pillar areas disposed in the n? type epitaxial layer at a first portion of a first surface of the n+ type silicon carbide substrate, a plurality of p+ areas disposed at a surface of the n? type epitaxial layer and separated from the n type pillar area, a schottky electrode disposed on the n? type epitaxial layer and the p+ area, and an ohmic electrode disposed at a second surface of the n+ type silicon carbide substrate. A doping density of the n type pillar area is larger than a doping density of the n? type epitaxial layer.
    Type: Grant
    Filed: December 3, 2013
    Date of Patent: June 14, 2016
    Assignee: HYUNDAI MOTOR COMPANY
    Inventors: Dae Hwan Chun, Jong Seok Lee, Kyoung-Kook Hong, Youngkyun Jung
  • Patent number: 9318584
    Abstract: Device structures and design structures for a bipolar junction transistor. The device structure includes a collector region in a substrate, a plurality of isolation structures extending into the substrate and comprised of an electrical insulator, and an isolation region in the substrate. The isolation structures have a length and are arranged with a pitch transverse to the length such that each adjacent pair of the isolation structures is separated by a respective section of the substrate. The isolation region is laterally separated from at least one of the isolation structures by a first portion of the collector region. The isolation region laterally separates a second portion of the collector region from the first portion of the collector region. The device structure further includes an intrinsic base on the second portion of the collector region and an emitter on the intrinsic base. The emitter has a length transversely oriented relative to the length of the isolation structures.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: April 19, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Peng Cheng, Peter B. Gray, Vibhor Jain, Robert K. Leidy, Qizhi Liu
  • Patent number: 9293330
    Abstract: A method for producing a semiconductor is disclosed, the method having: providing a semiconductor body having a first side and a second side; forming an n-doped zone in the semiconductor body by a first implantation into the semiconductor body via the first side to a first depth location of the semiconductor body; and forming a p-doped zone in the semiconductor body by a second implantation into the semiconductor body via the second side to a second depth location of the semiconductor body, a pn-junction forming between said n-doped zone and said p-doped zone in the semiconductor body.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: March 22, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Hans-Joachim Schulze, Ingo Muri, Friedrich Kroener, Werner Schustereder
  • Patent number: 9279837
    Abstract: A sensor apparatus includes an array of active sensor elements arranged in columns and rows. Each sensor element is associated with a thin film access device disposed in a first current path through which an activation current is provided to activate the sensor element. Each sensor element is read through a respective second current path. The second current paths do not include the thin film access device of the first current path. As such, noise from the thin film access device is isolated from the second current paths.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: March 8, 2016
    Assignee: NEXT BIOMETRICS GROUP ASA
    Inventor: Matias Troccoli
  • Patent number: 9087926
    Abstract: A semiconductor device includes a diode, a passivation layer and a conductive layer. The diode includes an epitaxial layer on a semiconductor substrate, and first and second diode contacts on different planes. The passivation layer has a planar top surface, and includes multiple consecutive layers of a benzocyclobutene (BCB) material formed on the diode, an aggregate thickness of the passivation layer exceeding a thickness of the epitaxial layer. The conductive layer is formed on the top surface of passivation layer, the conductive layer connecting with the first and the second diodes contact through first and second openings in the passivation layer, respectively. The passivation layer enhances a capacitive isolation between the conductive layer and the diode.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: July 21, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventor: Rick D. Snyder
  • Patent number: 9060146
    Abstract: A sensor apparatus includes an array of active sensor elements arranged in columns and rows. Each sensor element is associated with a thin film access device disposed in a first current path through which an activation current is provided to activate the sensor element. Each sensor element is read through a respective second current path. The second current paths do not include the thin film access device of the first current path. As such, noise from the thin film access device is isolated from the second current paths.
    Type: Grant
    Filed: January 5, 2010
    Date of Patent: June 16, 2015
    Assignee: Next Biometrics Group ASA
    Inventor: Matias Troccoli
  • Patent number: 9059328
    Abstract: A nitride semiconductor element having a high reverse breakdown voltage and a method of manufacturing the same are provided. A diode (a vertical-type SBD) has an n?-type nitride semiconductor layer (a drift region) formed on an n-type nitride semiconductor substrate, a p-type nitride semiconductor layer formed on the n?-type nitride semiconductor layer, and besides, an anode electrode formed on the p-type nitride semiconductor layer. The p-type nitride semiconductor layer has a relatively-thin first portion and a relatively-thick second portion provided so as to surround the first portion as being in contact with an outer circumference of the first portion. Also, the relatively-thin first portion of the p-type nitride semiconductor layer is formed thinner than the second portion so as to be depleted. The relatively-thick second portion of the p-type nitride semiconductor layer forms a guard ring part.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: June 16, 2015
    Assignee: Hitachi Metals, Ltd.
    Inventors: Akihisa Terano, Kazuhiro Mochizuki, Tomonobu Tsuchiya, Tadayoshi Tsuchiya, Naoki Kaneda, Tomoyoshi Mishima
  • Patent number: 9035336
    Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: May 19, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi Tachibana, Chie Hongo, Hajime Nago, Shinya Nunoue
  • Patent number: 9006863
    Abstract: A diode string voltage adapter includes diodes formed in a substrate of a first conductive type. Each diode includes a deep well region of a second conductive type formed in the substrate. A first well region of the first conductive type formed on the deep well region. A first heavily doped region of the first conductive type formed on the first well region. A second heavily doped region of the second conductive type formed on the first well region. The diodes are serially coupled to each other. A first heavily doped region of a beginning diode is coupled to a first voltage. A second heavily doped region of each diode is coupled to a first heavily doped region of a next diode. A second heavily doped region of an ending diode provides a second voltage. The deep well region is configured to be electrically floated.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: April 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Peng Hsieh, Jaw-Juinn Horng
  • Publication number: 20150061090
    Abstract: A semiconductor device includes: a drift layer having a first conductive type; a first semiconductor layer having a second conductive type and arranged in a surface portion of the drift layer; a second semiconductor layer having the first conductive type, arranged at a position of the drift layer spaced apart from the first semiconductor layer, and having a carrier density larger than the drift layer; a hole injection layer having the second conductive type and arranged selectively in the second semiconductor layer; a first electrode electrically connecting to the first semiconductor layer; a second electrode electrically connecting to the second semiconductor layer and the hole injection layer. The second semiconductor layer has a carrier density smaller than a spatial charge density.
    Type: Application
    Filed: April 17, 2013
    Publication date: March 5, 2015
    Inventor: Kazuhiro Oyama
  • Patent number: 8962466
    Abstract: A metal oxide formed by in situ oxidation assisted by radiation induced photo-acid is described. The method includes depositing a photosensitive material over a metal surface of an electrode. Upon exposure to radiation (for example ultraviolet light), a component, such as a photo-acid generator, of the photosensitive material forms an oxidizing reactant, such as a photo acid, which causes oxidation of the metal at the metal surface. As a result of the oxidation, a layer of metal oxide is formed. The photosensitive material can then be removed, and subsequent elements of the component can be formed in contact with the metal oxide layer. The metal oxide can be a transition metal oxide by oxidation of a transition metal. The metal oxide layer can be applied as a memory element in a programmable resistance memory cell. The metal oxide can be an element of a programmable metallization cell.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: February 24, 2015
    Assignee: Macronix International Co., Ltd.
    Inventors: Feng-Min Lee, Erh-Kun Lai, Wei-Chih Chien, Ming-Hsiu Lee, Chih-Chieh Yu
  • Patent number: 8946877
    Abstract: A semiconductor package comprises: a substrate comprising a semiconductor device; a cap comprising a seal ring disposed over a surface of the cap; and a gap between the substrate and the surface of the cap. The seal ring comprises a tread comprising at least two columns.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: February 3, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Rick Snyder, Joel Philliber
  • Patent number: 8946823
    Abstract: An electrostatic discharge (ESD) protection element includes a collector area, a first barrier area, a semiconductor area, a second barrier area and an emitter area. The collector area has a first conductivity type. The first barrier area borders on the collector area and has a second conductivity type. The semiconductor area borders on the first barrier area and is an intrinsic semiconductor area, or has the first or second conductivity type and a dopant concentration which is lower than a dopant concentration of the first barrier area. The second barrier area borders on the semiconductor area and has the second conductivity type and a higher dopant concentration than the semiconductor area. The emitter area borders on the second barrier area and has the first conductivity type.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: February 3, 2015
    Assignee: Infineon Technologies AG
    Inventors: Wolfgang Klein, Hans Taddiken, Winfried Bakalski
  • Patent number: 8941161
    Abstract: A semiconductor device comprises a first substrate portion and a second substrate portion disposed a distance away from the first substrate portion. The first substrate portion includes a first active semiconductor layer defining at least one semiconductor fin and a first polycrystalline layer formed directly on the fin. The first polycrystalline layer is patterned to define at least one semiconductor gate. The second substrate portion includes a doped region interposed between a second active semiconductor region and an oxide layer. The oxide layer protects the second active semiconductor region and the doped region. The doped region includes a first doped area and a second doped area separated by the first doped region to define a depletion region.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: January 27, 2015
    Assignee: International Business Machines Corporation
    Inventors: Veeraraghavan S. Basker, Tenko Yamashita
  • Patent number: 8927957
    Abstract: A memory device includes a first conductor, a diode, a memory element, and a second conductor arranged in series. The diode includes a first semiconductor layer over and in electrical communication with the first conductor. A patterned insulating layer has a sidewall over the first semiconductor layer. The diode includes an intermediate semiconductor layer on a first portion of the sidewall, and in contact with the first semiconductor layer. The intermediate semiconductor layer has a lower carrier concentration than the first semiconductor layer, and can include an intrinsic semiconductor. A second semiconductor layer on a second portion of the sidewall, and in contact with the intermediate semiconductor layer, has a higher carrier concentration than the intermediate semiconductor layer. A memory element is electrically coupled to the second semiconductor layer. The second conductor is electrically coupled to the memory element.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: January 6, 2015
    Assignee: Macronix International Co., Ltd.
    Inventor: Hsiang-Lan Lung
  • Patent number: 8928109
    Abstract: A semiconductor device is disclosed, which includes first and second power supply pads supplied with first and second power voltages, respectively, a first protection circuit coupled between the first and second power supply pads, and an internal circuit including a first power line and a plurality of transistors electrically coupled to the first power line. The first power line includes first and second portions, and the first portion is electrically connected to the first power supply pad. The device further includes a second protection circuit coupled between the second portion of the first power line and the second power supply pad.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: January 6, 2015
    Assignee: PS4 Luxco S.a.r.l.
    Inventors: Takashi Ishihara, Hisayuki Nagamine
  • Patent number: 8901703
    Abstract: The electronic device comprises a network of at least one thin-film capacitor and at least one inductor on a first side of a substrate of a semiconductor material. The substrate has a resistivity sufficiently high to limit electrical losses of the inductor and being provided with an electrically insulating surface layer on its first side. A first and a second lateral pin diode are defined in the substrate, each of the pin diodes having a doped p-region, a doped n-region and an intermediate intrinsic region. The intrinsic region of the first pin diode is larger than that of the second pin diode.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: December 2, 2014
    Assignee: NXP, B.V.
    Inventors: Arnoldus Den Dekker, Johannes Frederik Dijkhuis, Nicolas Jonathan Pulsford, Jozef Thomas Martinus Van Beek, Freddy Roozeboom, Antonius Lucien Adrianus Maria Kemmeren, Johan Hendrik Klootwijk, Maarten Dirk-Johan Nollen
  • Patent number: 8890272
    Abstract: A photodetector is provided, comprising: a radiation-absorbing semiconductor region and a collection semiconductor region separated by and each in contact with a barrier semiconductor region; wherein, at least in the absence of an applied bias voltage, the band gap between the valence band energy and the conduction band energy of the barrier semiconductor region is offset from the band gap between the valence band energy and the conduction band energy of the radiation-absorbing semiconductor region so as to form an energy barrier between the radiation-absorbing semiconductor region and the collection semiconductor region which resists the flow of minority carriers from the radiation-absorbing semiconductor region to the collection semiconductor region. Also provided is a method of manufacturing a photodetector.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: November 18, 2014
    Assignee: BAH Holdings LLC
    Inventor: Michael Tkachuk
  • Patent number: 8883589
    Abstract: A method of forming a memory cell is provided, the method including forming a diode including a first region having a first conductivity type, counter-doping the diode to change the first region to a second conductivity type, and forming a memory element coupled in series with the diode. Other aspects are also provided.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: November 11, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Xiying Costa, Abhijit Bandyopadhyay, Kun Hou, Brian Le, Yung-Tin Chen
  • Patent number: 8860189
    Abstract: Provided is a PIN diode that can suppress thermal destruction from occurring at the time of a reverse bias exceeding a breakdown voltage by current concentration on a curved part of an anode region. The PIN diode is configured to have: a semiconductor substrate 11 that includes an N+ semiconductor layer 1 and an N? semiconductor layer 2; a cathode electrode 18 that is formed on an outer surface of the N+ semiconductor layer 1; a main anode region 16, a separated anode region 15, and an anode connecting region that are formed by selectively diffusing P-type impurities from an outer surface of the N? semiconductor layer 2; and an anode electrode 17 that is formed on the main anode region 16.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: October 14, 2014
    Assignee: Sansha Electric Manufacturing Co., Ltd.
    Inventors: Yoshikazu Nishimura, Hirofumi Yamamoto, Takeyoshi Uchino
  • Patent number: 8853824
    Abstract: An enhanced tunnel field effect transistor includes a substrate, a layer of P-I-N structure, a hetero-material layer, a gate dielectric layer, a gate structure and a spacer, in which the layer of P-I-N structure is disposed on the substrate, the hetero-material layer is disposed on portion of the layer of P-I-N structure, the gate dielectric layer is disposed on the hetero-material layer, the gate structure is disposed the gate dielectric layer and a spacer is disposed on a sidewall of the hetero-material layer, the gate dielectric layer, and the gate structure. The hetero-material layer can increase the tunneling efficiency of the enhanced tunnel field effect transistor to increase the conductor current to improve the enhanced tunnel field effect transistor performance.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: October 7, 2014
    Assignee: National Chiao Tung University
    Inventors: Pei-Yu Wang, Bing-Yue Tsui
  • Patent number: 8847200
    Abstract: A memory cell is provided, the memory cell including a steering element having a vertically-oriented p-i-n junction, and a carbon nanotube fabric. The steering element and the carbon nanotube fabric are arranged electrically in series, and the entire memory cell is formed above a substrate. Other aspects are also provided.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: September 30, 2014
    Assignee: SanDisk 3D LLC
    Inventors: Scott Brad Herner, Roy E. Scheuerlein
  • Patent number: 8847276
    Abstract: In a semiconductor device including an IGBT and a freewheeling diode (FWD), W1, W2, and W3 satisfy predetermined formulas. W1 denotes a distance from a boundary between a cathode region and a collector region to a position, where a peripheral-region-side end of the well layer is projected, on a back side of the drift layer. W2 denotes a distance from a boundary between the IGBT and the FWD in a base region to the peripheral-region-side end of the well layer. W3 denotes a distance from the boundary between the cathode region and the collector region to a position, where a boundary between the base region and the well layer is projected, on the back side.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: September 30, 2014
    Assignee: DENSO CORPORATION
    Inventors: Hiromitsu Tanabe, Kenji Kouno, Yukio Tsuzuki
  • Patent number: 8841741
    Abstract: A high breakdown voltage diode of the present embodiment includes a first conductive semiconductor substrate, a drift layer formed on the first conductive semiconductor substrate and formed of a first conductive semiconductor, a buffer layer formed on the drift layer and formed of a second conductive semiconductor, a second conductive high concentration semiconductor region formed at an upper portion of the buffer layer, a mesa termination unit formed on an end region of a semiconductor apparatus to relax an electric field of the end region when reverse bias is applied between the semiconductor substrate and the buffer layer, and an electric field relaxation region formed at the mesa termination unit and formed of a second conductive semiconductor. A breakdown voltage of a high breakdown voltage diode, in which a pn junction is provided to a semiconductor layer, is increased, and a process yield is improved.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: September 23, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masamu Kamaga, Makoto Mizukami, Takashi Shinohe
  • Patent number: 8835950
    Abstract: A semiconductor device has an active layer, a first semiconductor layer of first conductive type, an overflow prevention layer disposed between the active layer and the first semiconductor layer, which is doped with impurities of first conductive type and which prevents overflow of electrons or holes, a second semiconductor layer of first conductive type disposed at least one of between the active layer and the overflow prevention layer and between the overflow prevention layer and the first semiconductor layer, and an impurity diffusion prevention layer disposed between the first semiconductor layer and the active layer, which has a band gap smaller than those of the overflow prevention layer, the first semiconductor layer and the second semiconductor layer and which prevents diffusion of impurities of first conductive type.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: September 16, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Chie Hongo, Hajime Nago, Shinya Nunoue
  • Patent number: 8829638
    Abstract: Electrical pumping of photonic crystal (PC) nanocavities using a lateral p-i-n junction is described. Ion implantation doping can be used to form the junction, which under forward bias pumps a gallium arsenide photonic crystal nanocavity with indium arsenide quantum dots. Efficient cavity-coupled electroluminescence is demonstrated in a first experimental device. Electrically pumped lasing is demonstrated in a second experimental device. High speed modulation of a single mode LED is demonstrated in a third experimental device. This approach provides several significant advantages. Ease of fabrication is improved because difficult timed etch steps are not required. Any kind of PC design can be employed. Current flow can be lithographically controlled to focus current flow to the active region of the device, thereby improving efficiency, reducing resistance, improving speed, and reducing threshold.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: September 9, 2014
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Gary Shambat, Bryan Ellis, Jelena Vuckovic
  • Patent number: 8823148
    Abstract: A semiconductor device includes a first-conductivity-type semiconductor substrate; a first-conductivity-type first semiconductor layer formed on the semiconductor substrate, and having an impurity concentration lower than that of the semiconductor substrate; a second-conductivity-type second semiconductor layer epitaxially formed on the first semiconductor layer; a second-conductivity-type third semiconductor layer epitaxially formed on the second semiconductor layer, and having an impurity concentration higher than that of the second semiconductor layer; a recess formed in the third semiconductor layer, at least a corner portion of a side face and a bottom surface of the recess being located in the second semiconductor layer; a first electrode in contact with the third semiconductor layer; a second electrode connected to the first electrode and in contact with the second semiconductor layer at the bottom surface of the recess; and a third electrode in contact with a lower surface of the semiconductor substra
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: September 2, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chiharu Ota, Takashi Shinohe, Makoto Mizukami, Johji Nishio
  • Publication number: 20140225234
    Abstract: A semiconductor device having a lateral diode includes a semiconductor layer, a first semiconductor region in the semiconductor layer, a contact region having an impurity concentration greater than that of the first semiconductor region, a second semiconductor region located in the semiconductor layer and separated from the contact region, a first electrode electrically connected through the contact region to the first semiconductor region, and a second electrode electrically connected to the second semiconductor region. The second semiconductor region includes a low impurity concentration portion, a high impurity concentration portion, and an extension portion. The second electrode forms an ohmic contact with the high impurity concentration portion. The extension portion has an impurity concentration greater than that of the low impurity concentration portion and extends in a thickness direction of the semiconductor layer.
    Type: Application
    Filed: April 22, 2014
    Publication date: August 14, 2014
    Applicant: DENSO CORPORATION
    Inventors: Takao YAMAMOTO, Norihito TOKURA, Hisato KATO, Akio NAKAGAWA
  • Patent number: 8791553
    Abstract: Methods of forming and tuning a multilayer select device are provided, along with apparatus and systems which include them. As is broadly disclosed in the specification, one such method can include forming a first region having a first conductivity type; forming a second region having a second conductivity type and located adjacent to the first region; and forming a third region having the first conductivity type and located adjacent to the second region and, such that the first, second and third regions form a structure located between a first electrode and a second electrode, wherein each of the regions have a thickness configured to achieve a current density in a range from about 1×e4 amps/cm2 up to about 1×e8 amps/cm2 when a voltage in a selected voltage range is applied between the first electrode and the second electrode.
    Type: Grant
    Filed: July 12, 2013
    Date of Patent: July 29, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Durai Vishak Nirmal Ramaswamy
  • Patent number: 8791552
    Abstract: A semiconductor memory device includes a cell array layer including a first wire, a memory cell stacked on the first wire, and a second wire formed on the memory cell. The memory cell includes a variable resistance element and a current control element The current control element includes a first conductivity-type semiconductor into which a first impurity is doped, an i-type semiconductor in contact with the first conductivity-type semiconductor, a second conductivity-type semiconductor into which a second impurity is doped, and an impact ionization acceleration unit being formed between the i-type semiconductor and one of the first conductivity-type semiconductor and the second conductivity-type semiconductor.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: July 29, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jun Nishimura, Nobuaki Yasutake, Takayuki Okamura
  • Patent number: 8766415
    Abstract: A protective structure may include: a semiconductor substrate having a doping of a first conductivity type; a semiconductor layer having a doping of a second conductivity type arranged at a surface of the semiconductor substrate; a buried layer having a doping of the second conductivity type arranged in a first region of the semiconductor layer and at the junction between the semiconductor layer and the semiconductor substrate; a first dopant zone having a doping of the first conductivity type arranged in the first region of the semiconductor layer above the buried layer; a second dopant zone having a doping of the second conductivity type arranged in a second region of the semiconductor layer; an electrical insulation arranged between the first region and the second region of the semiconductor layer; and a common connection device for the first dopant zone and the second dopant zone.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: July 1, 2014
    Assignee: Infineon Technologies AG
    Inventors: Andre Schmenn, Damian Sojka, Carsten Ahrens
  • Patent number: 8766396
    Abstract: A semiconductor device comprises a substrate, a cathode, an outer ring, an anode, an electrically insulating layer, and an electrically conducting layer. The substrate includes a semiconducting material having a first conduction type. The substrate has a first face and a second face substantially parallel to the first face. A cathode is disposed at the second face and has the first conduction type. An outer ring, having the first conduction type, is disposed at an outer perimeter of the first face of the substrate. An anode, having the second conduction type, is disposed at the first face of the substrate within an inner perimeter of the outer ring. An electrically insulating layer is disposed over the outer ring. An electrically conducting layer is disposed over the electrically insulating layer and over the outer ring. The electrically conducting layer electrically is insulated from the outer ring by the electrically insulating layer.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: July 1, 2014
    Assignee: Moxtek, Inc.
    Inventors: Keith Decker, Derek Hullinger
  • Patent number: 8766413
    Abstract: A p anode layer (2) is formed on one main surface of an n? drift layer (1). An n+ cathode layer (3) having an impurity concentration more than that of the n? drift layer (1) is formed on the other main surface of the n? drift layer (1). An anode electrode (4) is formed on the surface of the p anode layer (2). A cathode electrode (5) is formed on the surface of the n+ cathode layer (3). An n-type broad buffer region (6) that has a net doping concentration more than the bulk impurity concentration of a wafer and less than that of the n+ cathode layer (3) and the p anode layer (2) is formed in the n? drift layer (1). The resistivity ?0 of the n? drift layer (1) satisfies 0.12V0??0?0.25V0 with respect to a rated voltage V0. The total amount of the net doping concentration of the broad buffer region (6) is equal to or more than 4.8×1011 atoms/cm2 and equal to or less than 1.0×1012 atoms/cm2.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: July 1, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Michio Nemoto, Takashi Yoshimura
  • Patent number: 8766225
    Abstract: According to the embodiment, a storage device includes row lines arranged parallel to one another, column lines arranged parallel to one another to intersect with the row lines, and a memory cell disposed at each of intersections of the row lines and the column lines and including a resistance-change element and a diode connected in series to the resistance-change element. The diode includes a stack of a first semiconductor region containing an impurity of a first conductivity type, a second semiconductor region containing an impurity of the first conductivity type lower in concentration than in the first semiconductor region, and a third semiconductor region containing an impurity of a second conductivity type. An impurity concentration in the second semiconductor region of the diode in a first adjacent portion adjacent to the first semiconductor region is higher than that in a second adjacent portion adjacent to the third semiconductor region.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenichi Murooka, Hiroshi Kanno
  • Publication number: 20140159150
    Abstract: In aspects of the invention, an n-type epitaxial layer that forms an n? type drift layer is formed on the upper surface of an n-type semiconductor substrate formed by being doped with a high concentration of antimony. A p-type anode layer is formed on a surface of the n? type drift layer. An n-type contact layer is formed with an impurity concentration in the same region as the impurity concentration of the n-type cathode layer, or higher than the impurity concentration of the n-type cathode layer, on the lower surface of the n-type cathode layer. A cathode electrode is formed so as to be in contact with the n-type contact layer. The n-type contact layer is doped with phosphorus and, without allowing complete recrystallization using a low temperature heat treatment of 500° C. or less, lattice defects are allowed to remain.
    Type: Application
    Filed: February 10, 2014
    Publication date: June 12, 2014
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Mitsuaki KIRISAWA
  • Patent number: 8748236
    Abstract: A method for manufacturing a semiconductor device includes irradiating light to an effective region of a semiconductor substrate. A wavelength of the light is a wavelength adapted so that light absorptance of the semiconductor substrate increases if an intensity of the light increases. The light is irradiated so that a focus point of the light is made within the semiconductor substrate in the irradiating.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: June 10, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventor: Atsushi Tanida