Abstract: A high fill-factor photosensor array is formed comprising a P-layer, an I-layer, one or more semiconductor structures adjacent to the I-layer and each coupled to a N-layer, an electrically conductive electrode formed on top of the P-layer, and an additional semiconductor structure, adjacent to the N-layer and which is electrically connected to a voltage bias source. The bias voltage applied to the additional semiconductor structure charges the additional semiconductor structure, thereby creating a tunneling effect between the N-layer and the P-layer, wherein electrons leave the N-layer and reach the P-layer and the electrically conductive layer. The electrons then migrate and distribute uniformly throughout the electrically conductive layer, which ensures a uniform bias voltage across to the entire photosensor array. The biasing scheme in this invention allows to achieve mass production of photosensors without the use of wire bonding.

Abstract: A process is described for producing silicon carbide crystals having increased minority carrier lifetimes. The process includes the steps of heating and slowly cooling a silicon carbide crystal having a first concentration of minority carrier recombination centers such that the resultant concentration of minority carrier recombination centers is lower than the first concentration.

Abstract: A semiconductor patch antenna for microwave radiation having a wide pin-junction or pn-junction with the depletion region or embodiments having a separating buried oxide (SiO2) layer between p- and n-doped regions as the natural resonator volume. Embodiments that do not include a metal ground plane and/or a metal patch are disclosed.

Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

Abstract: A light-emitting diode (LED) device is disclosed. The LED device includes a semiconductor substrate with a light-emitting diode chip disposed thereon. At least two isolated outer wiring layers are disposed on the bottom surface of the semiconductor substrate and are electrically connected to the light-emitting diode chip, serving as input terminals. A lens module is adhered to the top surface of the semiconductor substrate to cap the light-emitting diode chip. In one embodiment, the lens module comprises a glass substrate having a first cavity formed at a first surface thereof, a fluorescent layer formed over a portion of a first surface exposed by the first cavity, facing the light-emitting diode chip, and a molded lens formed over a second surface of the glass carrier opposing to the first surface.

Abstract: A semiconductor device includes a stepwise impurity layer provided at one of an anode portion and an cathode portion of the semiconductor device by introducing an impurity of a predetermined conduction type from a major surface of the semiconductor substrate through to a first depth to provide a first region of the semiconductor substrate having the impurity of the predetermined conduction type introduced therein. The predetermined conduction type is a same conduction type as a conduction type of the one of the anode portion and the cathode portion. The stepwise impurity layer is further provided by melting a second, predetermined region of the semiconductor substrate having a second depth deeper than the first depth and including the first region to make uniform the impurity of the predetermined conduction type in a concentration from the major surface through to the second depth to provide a uniform stepwise impurity concentration profile.

Abstract: The present invention relates to various switching device structures including Schottky diode (10), P—N diode, and P—I—N diode, which are characterized by low defect density, low crack density, low pit density and sufficient thickness (>2.5 um) GaN layers (16) of low dopant concentration (<1E16 cm?3) grown on a conductive GaN layer (14). The devices enable substantially higher breakdown voltage on hetero-epitaxial substrates (<2 KV) and extremely high breakdown voltage on homo-epitaxial substrates (>2 KV).

Abstract: A semiconductor device including a base layer of a first conductivity type having a first main surface and a second main surface opposite the first main surface, a first main electrode layer connected to the first main surface, control regions arranged inside grooves penetrating the first main electrode layer and reach inside the base layer, and a second main electrode layer of the first conductivity type and connected to the second main surface.

Abstract: A memory architecture that employs one or more semiconductor PIN diodes is provided. The memory employs a substrate that includes a buried bit/word line and a PIN diode. The PIN diode includes a non-intrinsic semiconductor region, a portion of the bit/word line, and an intrinsic semiconductor region positioned between the non-intrinsic region and the portion of the bit/word line.

Abstract: The present invention provides high-speed, high-efficiency PIN diodes for use in photodetector and CMOS imagers. The PIN diodes include a layer of intrinsic semiconducting material, such as intrinsic Ge or intrinsic GeSi, disposed between two tunneling barrier layers of silicon oxide. The two tunneling barrier layers are themselves disposed between a layer of n-type silicon and a layer of p-type silicon.

Abstract: The present invention provides a photoelectric conversion device in which a leakage current is suppressed. A photoelectric conversion device of the present invention comprises: a first electrode over a substrate; a photoelectric conversion layer including a first conductive layer having one conductivity, a second semiconductor layer, and a third semiconductor layer having a conductivity opposite to the one conductivity of the second semiconductor layer over the first electrode, wherein an end portion of the first electrode is covered with the first semiconductor layer; an insulating film, and a second electrode electrically connected to the third semiconductor film with the insulating film therebetween, over the insulating film, are formed over the third semiconductor film, and wherein a part of the second semiconductor layer and a part of the third semiconductor layer is removed in a region of the photoelectric conversion layer, which is not covered with the insulating film.

Abstract: A method for forming a silicon film may be performed using a microheater including a substrate and a metal pattern spaced apart from the substrate. The silicon film may be formed on the metal pattern by applying a voltage to the metal pattern of the microheater to heat the metal pattern and by exposing the microheater to a source gas containing silicon. The silicon film may be made of polycrystalline silicon. A method for forming a pn junction may be performed using a microheater including a substrate, a conductive layer on the substrate, and a metal pattern spaced apart from the substrate. The pn junction may be formed between the metal pattern and the conductive layer by applying a voltage to the metal pattern of the microheater to heat the metal pattern. The pn junction may be made of polycrystalline silicon.

Abstract: A piezo thin-film diode (piezo-diode) cantilever microelectromechanical system (MEMS) and associated fabrication processes are provided. The method deposits thin-films overlying a substrate. The substrate can be made of glass, polymer, quartz, metal foil, Si, sapphire, ceramic, or compound semiconductor materials. Amorphous silicon (a-Si), polycrystalline Si (poly-Si), oxides, a-SiGe, poly-SiGe, metals, metal-containing compounds, nitrides, polymers, ceramic films, magnetic films, and compound semiconductor materials are some examples of thin-film materials. A cantilever beam is formed from the thin-films, and a diode is embedded with the cantilever beam. The diode is made from a thin-film shared in common with the cantilever beam. The shared thin-film may a film overlying a cantilever beam top surface, a thin-film overlying a cantilever beam bottom surface, or a thin-film embedded within the cantilever beam.

Abstract: A nonvolatile memory cell includes: a rail-shaped first conductor formed at a first height above a substrate; a rail-shaped second conductor formed above the first conductor; and a vertically oriented first pillar comprising a p-i-n first diode; wherein the first pillar is disposed between the second conductor and the first conductor; wherein the first diode comprises an intrinsic or lightly doped region; and wherein the intrinsic or lightly doped region has a first thickness of about 300 angstroms or greater. Numerous additional aspects are provided.

Abstract: In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.

Abstract: A dynamic random access memory cell and a manufacturing method thereof are provided. First, a substrate on which a bottom oxide layer and a semiconductor layer are formed is provided. The semiconductor layer is formed on the bottom oxide layer. Next, a gate is formed on the semiconductor layer. Then, the semiconductor layer is patterned to expose a portion of the bottom oxide layer. Afterwards, an insulation layer is formed at the side walls of the semiconductor layer, wherein the height of the insulation layer is shorter than that of the semiconductor layer, so that a gap is formed between the tops of the insulation layer and the semiconductor layer. Further, a doping layer covering the insulation layer and having the same height with the semiconductor layer is formed on the bottom oxide layer. The doping layer contacts the side walls of the semiconductor layer via the gap.

Abstract: A series-shunt switch is provided. The switch includes a PIN diode having an input electrical terminal, an output electrical terminal and a thermal terminal. The thermal terminal is configured to provide continuity of diode thermal ground with respect to a circuit thermal ground node.

Abstract: A high-frequency switch includes a semiconductor body made of a semiconductor material having a first surface and a second surface, and two direct current terminals and two high-frequency terminals.

Abstract: An integrated circuit including vertically oriented diode structures between conductors and methods of fabricating the same are provided. The diode is a metal-insulator diode having a first metal layer, a first insulating layer, a second insulating layer and a second metal layer. At least one asymmetric interface state is provided at the intersection of at least two of the layers to increase the ratio of the diode's on-current to its reverse bias leakage current. In various examples, the asymmetric interface state is formed by a positive or negative sheet charge that alters the barrier height and/or electric field at one or more portions of the diode. Two-terminal devices such as passive element memory cells can utilize the diode as a steering element in series with a state change element. The devices can be formed using pillar structures at the intersections of upper and lower conductors.

Abstract: A process is provided for fabricating a semiconductor device having a germanium nanofilm layer that is selectively deposited on a silicon substrate in discrete regions or patterns. A semiconductor device is also provided having a germanium film layer that is disposed in desired regions or having desired patterns that can be prepared in the absence of etching and patterning the germanium film layer. A process is also provided for preparing a semiconductor device having a silicon substrate having one conductivity type and a germanium nanofilm layer of a different conductivity type. Semiconductor devices are provided having selectively grown germanium nanofilm layer, such as diodes including light emitting diodes, photodetectors, and like. The method can also be used to make advanced semiconductor devices such as CMOS devices, MOSFET devices, and the like.

Abstract: A Ferroelectric tunnel FET switch as ultra-steep (abrupt) switch with subthreshold swing better than the MOSFET limit of 60 mV/decade at room temperature combining two key principles: ferroelectric gate stack and band-to-band tunneling in gated p-i-n junction, wherein the ferroelectric material included in the gate stack creates, due to dipole polarization with increasing gate voltage, a positive feedback in the capacitive coupling that controls the band-to-band (BTB) tunneling at the source junction of a silicon p-i-n reversed bias structure, wherein the combined effect of BTB tunneling and ferroelectric negative capacitance offers more abrupt off-on and on-off transitions in the present proposed Ferroelectric tunnel FET than for any reported tunnel FET or any reported ferroelectric FET.

Abstract: A PIN photodiode structure includes a substrate, a P-doped region disposed in the substrate, an N-doped region disposed in the substrate, and a first semiconductor material disposed in the substrate and between the P-doped region and the N-doped region.

Abstract: A semiconductor device formed by decreasing thickness of a substrate by grinding, and performing ion implantation. In a diode in which a P anode layer and an anode electrode are formed at a side of a right face of an N? drift layer, and an N+ cathode layer and a cathode electrode are formed at a side of a back face of the N? drift layer, an N cathode buffer layer is formed thick compared with the N+-type cathode layer between the N?-type drift layer and the N+ cathode layer, the buffer layer being high in concentration compared with the N? drift layer, and low compared with the N+ cathode layer. When a reverse bias voltage is applied, a depletion layer is stopped in the middle of the N cathode buffer layer, and thus prevented from reaching the N+ cathode layer, so that the leakage current is suppressed.

Abstract: A method of making a semiconductor device includes forming a first conductivity type polysilicon layer over a substrate, forming an insulating layer over the first conductivity type polysilicon layer, where the insulating layer comprises an opening exposing the first conductivity type polysilicon layer, and forming an intrinsic polysilicon layer in the opening over the first conductivity type polysilicon layer. A nonvolatile memory device contains a first electrode, a steering element located in electrical contact with the first electrode, a storage element having a U-shape cross sectional shape located over the steering element, and a second electrode located in electrical contact with the storage element.

Abstract: A scanning head for an optical position-measuring system includes a receiver grating, formed of photosensitive areas, for the scanning of locally intensity-modulated light of differing wavelengths. The receiver grating is formed from a semiconductor layer stack of a doped p-layer, an intrinsic i-layer and a doped n-layer. The individual photosensitive areas have a first doped layer and at least a part of the intrinsic layer in common and are electrically separated from one another by interruptions in the second doped layer.

Abstract: A diode having a first semiconductor region of a first polarity and a second semiconductor region of an opposite polarity at least partially surrounding the first semiconductor region. A metal contact coupled to the second semiconductor region at least partially surrounding the first semiconductor region. The diode offers improvements in switching speed.

Abstract: A semiconductor diode with integrated resistor has a semiconductor body with a front surface, a back surface and a diode structure with an anode electrode and a cathode electrode.

Abstract: A semiconductor device includes: a first semiconductor layer; a first electrode provided on a first surface side of the first semiconductor layer; a first insulating layer; and a second semiconductor layer. The first insulating layer is provided between the first semiconductor layer and the first electrode and configured to constrict current flowing between the first semiconductor layer and the first electrode. The second semiconductor layer has a first conductivity type and is provided at least on a path of the current constricted by the first insulating layer. The second semiconductor layer is in contact with the first electrode. The second semiconductor layer contains first impurities at a concentration higher than a concentration of impurities contained in the first semiconductor layer.

Abstract: A high voltage/power semiconductor device has at least one active region having a plurality of high voltage junctions electrically connected in parallel. At least part of each of the high voltage junctions is located in or on a respective membrane such that the active region is provided at least in part over plural membranes. There are non-membrane regions between the membranes. The device has a low voltage terminal and a high voltage terminal. At least a portion of the low voltage terminal and at least a portion of the high voltage terminal are connected directly or indirectly to a respective one of the high voltage junctions. At least those portions of the high voltage terminal that are in direct or indirect contact with one of the high voltage junctions are located on or in a respective one of the plural membranes.

Abstract: Provided is an image sensor. The image sensor can include a first substrate comprising a pixel portion in which a readout circuitry is provided and a peripheral portion in which a peripheral circuitry is provided. An interlayer dielectric including lines can be formed on the first substrate to connect with the readout circuitry and the peripheral circuitry. A crystalline semiconductor layer can be provided on a portion of the interlayer dielectric corresponding to the pixel portion through a bonding process. The crystalline semiconductor layer can include a first photodiode and second photodiode. The first and second photodiodes can be defined by device isolation trenches in the crystalline semiconductor layer. A device isolation layer can be formed on the crystalline semiconductor layer comprising the device isolation trenches. An upper electrode layer passes through the device isolation layer to connect with a portion of the first photodiode.

Abstract: An improved Fast Recovery Diode comprises a main PN junction defining a central conduction region for conducting high current in a forward direction and a peripheral field spreading region surrounding the central conduction region for blocking high voltage in the reverse direction. The main PN junction has an avalanche voltage equal to or lower than an avalanche voltage of the peripheral field spreading region so substantially the entire said main PN junction participates in avalanche conduction. This rugged FRED structure can also be formed in MOSFETS, IGBTS and the like.

Abstract: A power semiconductor device that realizes high-speed turnoff and soft switching at the same time has an n-type main semiconductor layer that includes lightly doped n-type semiconductor layers and extremely lightly doped n-type semiconductor layers arranged alternately and repeatedly between a p-type channel layer and an n+-type field stop layer, in a direction parallel to the first major surface of the n-type main semiconductor layer. A substrate used for manufacturing the semiconductor device is fabricated by forming trenches in an n-type main semiconductor layer 1 and performing ion implantation and subsequent heat treatment to form an n+-type field stop layer in the bottom of the trenches. The trenches are then filled with a semiconductor doped more lightly than the n-type main semiconductor layer for forming extremely lightly doped n-type semiconductor layers. The manufacturing method is applicable with variations to various power semiconductor devices such as IGBT's, MOSFET's and PIN diodes.

Abstract: A PIN diode has an n? drift layer, a p anode layer, an n buffer layer, an n+ layer, a front surface electrode and a back surface electrode. The n+ layer has an impurity concentration having a stepwise profile substantially fixed for a predetermined depth measured from a second major surface. The n buffer layer has an impurity concentration gently decreasing as seen at the n+ layer toward n? drift layer. The n? drift layer has an impurity concentration reflecting that of the semiconductor substrate and thus substantially fixed depthwise. The p anode layer has an impurity concentration relatively steeply decreasing as seen at a first major surface toward the n? drift layer. Thus there can be provided a semiconductor device that can provide characteristics, as desired, with high precision to accommodate the product applied, and a method of fabricating the semiconductor device.

Abstract: A semiconductor photodetector 10 has a first semiconductor substrate 1 that is of a first conductive type and a low resistivity and has a (111) front surface, and a second semiconductor substrate 2 that is of the first conductive type and a high resistivity, has a (100) front surface, and is adhered onto first semiconductor substrate 1. A semiconductor region 3 of a second conductive type is formed on the front surface side of second semiconductor substrate 2. A region of a periphery of semiconductor region 3 is etched until first semiconductor substrate 1 is exposed. A first electrode 1e and a second electrode 2e are electrically connected to the exposed front surface of first semiconductor substrate 1 and to semiconductor region 3, respectively.

Abstract: A vertical semiconductor device comprises a semiconductor body, a first contact and a second contact, wherein a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and a third semiconductor region of a second conductivity type are formed in the semiconductor body in a direction from the first contact to the second contact, wherein a basic doping density of the second semiconductor region is smaller than a doping density of the third semiconductor region, and wherein in the second semiconductor region a semiconductor zone of the second conductivity type is arranged in which the doping density is increased relative to the basic doping density of the second semiconductor region.

Abstract: A first memory level includes a first plurality of memory cells that includes every memory cell in the first memory level. Each memory cell includes a vertically oriented p-i-n diode in the form of a pillar that includes a bottom heavily doped p-type region, a middle intrinsic or lightly doped region, and a top heavily doped n-type region. The first plurality of memory cells includes programmed cells and unprogrammed cells, wherein programmed cells comprise at least half of the first plurality of memory cells. Current flowing through the p-i-n diodes of at least 99 percent of the programmed cells when a voltage between about 1.5 volts and about 3.0 volts is applied between the bottom heavily doped p-type region and the top heavily doped n-type region is at least 1.5 microamps.

Abstract: An over-voltage protection device includes a substrate including an upper surface and a lower surface; a first electrode provided on the upper surface of the substrate; a second electrode provided on the lower surface on the substrate; a first conductive layer overlying the lower surface of the substrate, the first conductive region being a conductive region of a first type; a plurality of first conductive regions provided proximate the upper surface of the substrate, the plurality of first conductive regions being conductive regions of the first type; and a plurality of second conductive region provided proximate the upper surface of the substrate, the plurality of second conductive region being conductive regions of a second type. The plurality of the first conductive regions are provided in an alternating manner with the plurality of second conductive regions. The first electrode is contacting the plurality of the first and second conductive regions.

Abstract: One embodiment of the invention provides a semiconductor diode device including a first conductivity type region, a second conductivity type region, where the second conductivity type is different from the first conductivity type, an intrinsic region located between the first conductivity type region and the second conductivity type region; a first halo region of the first conductivity type located between the second conductivity type region and the intrinsic region, and optionally a second halo region of the second conductivity type located between the first conductivity type region and the intrinsic region.

Abstract: A method is provided for reducing or eliminating leakage between a pinned photodiode and shallow trench isolation structure fabricated therewith while optimizing the sensitivity of the photodiode. An N+ region is implanted in a P-type substrate and a P-type well separates the N+ region from the shallow trench isolation (STI) structure. At least a P+ region is formed over the N+ region and overlapping at least part of the P-type well and a substrate portion between the N+ region and P-type well. The space between the N+ region and a damaged region adjacent the STI is greater than the expansion distance of the depletion region between the N+ region and the P-type well. The junctions of the various features are optimized to maximize a photosensitive response for the wavelength of the absorbed light as well as for reducing or eliminating electrical leakage.

Abstract: Embodiments of the present invention generally relate to solar cells and methods and apparatuses for forming the same. More particularly, embodiments of the present invention relate to thin film multi-junction solar cells and methods and apparatuses for forming the same.

Abstract: A photo sensor that is capable of generating a photo sensing signal corresponding only to ambient light by comprehending changes in electrical current depending on the change of temperature and compensating for the electrical current according the change of temperature and a flat panel display device using the photo sensor, and the photo sensor including a photo sensing unit generating a first current corresponding to an ambient light and a second current corresponding to an ambient temperature; a temperature compensating unit including a dark diode generating a third current having a same magnitude as the second current, corresponding to the ambient temperature due to block of light to be incident; and a buffer unit outputting a light sensing signal corresponding to current having the same magnitude as the first current by subtracting the third current generated in the temperature compensating unit from the second current generated in the photo sensing unit.

Abstract: A method of making a semiconductor device includes providing an insulating layer containing a plurality of openings, forming a first semiconductor layer in the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the first semiconductor layer, such that first conductivity type second portions of the first semiconductor layer remain in lower portions of the plurality of openings in the insulating layer, and upper portions of the plurality of openings in the insulating layer remain unfilled. The method also includes forming a second semiconductor layer in the upper portions of the plurality of openings in the insulating layer and over the insulating layer, and removing a first portion of the second semiconductor layer located over the insulating layer.

Abstract: In a semiconductor-device fabrication method, a plurality of recessed portions are first formed in the principal surface of a substrate. Then, a through hole, passing through the substrate in the front-to-back direction of the substrate, is formed under a portion of the bottom of each recessed portion in the substrate. Subsequently, a plurality of semiconductor elements in the form of chips are spread in a liquid, and the semiconductor-element-spread liquid is poured over the principal surface of the substrate, while passing the liquid through the through holes, so that the semiconductor elements fit into the recessed portions in a self-aligned manner. In this way, the semiconductor elements are disposed into the recessed portions in the substrate in a self-aligned manner.

Abstract: A semi-conducting device has at least one layer doped with a doping agent and a layer of another type deposited on the doped layer in a single reaction chamber. An operation for avoiding the contamination of the other layer by the doping agent separates the steps of depositing each of the layers.

Abstract: The invention relates to a monolithically integrated vertical pin photodiode which is produced according to BiCMOS technology and comprises a planar surface facing the light and a rear face and anode connections located across p areas on a top face of the photodiode. An i-zone of the pin photodiode is formed by combining a low doped first p-epitaxial layer, which has maximum thickness and doping concentration, placed upon a particularly high doped p substrate, with a low doped second n? epitaxial layer that borders the first layer, and n+ cathode of the pin photodiode being integrated into the second layer. The p areas delimit the second n epitaxial layer in a latent direction while another anode connecting area of the pin diode is provided on the rear face in addition to the anode connection.

Abstract: An arrangement of pillar shaped p-i-n diodes having a high aspect ration are formed on a semiconductor substrate. Each device is formed by an intrinsic or lightly doped region (i-region) positioned between a P+ region and an N+ region at each end of the pillar. The arrangement of pillar p-i-n diodes is embedded in an optical transparent medium. For a given surface area, more light energy is absorbed by the pillar arrangement of p-i-n diodes than by conventional planar p-i-n diodes. The pillar p-i-n diodes are preferably configured in an array formation to enable photons reflected from one pillar p-i-n diode to be captured and absorbed by another p-i-n diode adjacent to the first one, thereby optimizing the efficiency of energy conversion.

Abstract: An input signal comprising electronic carriers is injected into an impact ionization device with a high electric field whereupon the electronic carriers are accelerated toward an electron collector or hole sink and subsequently ionize additional electrons and holes that accelerated toward the electron collector and hole sink respectively. When properly biased an avalanche effect may occur that is proportional to the current injected into the impact ionization device via the input electrode. As a result, the input signal is amplified to provide an amplified signal. The described amplifier may be integrated with an input device such as a photodiode, and a transimpedance output amplifier onto a common substrate resulting in high performance high density sensor arrays and the like.

Abstract: Semiconductor devices and fabrication methods thereof. A first dielectric layer with a first conductor line along a first direction is disposed on a semiconductor substrate, wherein the top surface of the first conductor line is lower than the top surface of the first dielectric layer. A second dielectric layer comprising an opening corresponding to the first diode element is disposed on the first dielectric layer. A semiconductor diode component comprises a first diode element disposed on the first conductor line, wherein the top surface of the first diode element is level with the top surface of the first dielectric layer; and a second diode element and a third diode element are filled in the opening.

Abstract: A series-shunt switch is provided. The switch includes a PIN diode having an input electrical terminal, an output electrical terminal and a thermal terminal. The thermal terminal is configured to provide continuity of diode thermal ground with respect to a circuit thermal ground node.

Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.