Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

Abstract: Provided are semiconductor low-K Si die wire bonding packages with package stress control and fabrication methods for such packages. The packages include molding interface material applied onto the low-K Si die. In general, the molding interface material is selectively applied onto the low-K Si die surface in order to minimize to safe levels the package stress experienced by the low-K Si die. Selective application includes defining various combinatorial patterns of coated and non-coated regions. In addition, selective application may also include a general application of molding interface material to create a stress buffer zone. The results are packages with less stress experienced by the low-K Si die and so improved reliability (in compliance with industry specifications).

Abstract: A transient voltage suppressor includes a reverse bias transient voltage suppressor PN diode connected in series with a forward biased PIN diode, the series circuit formed by the PN diode and the PIN diode is connected between first and second terminals and in parallel with a reverse biased PIN diode.

Abstract: Embodiments of the invention generally relate to the field of semiconductor devices, and more specifically to fin-based junction diodes. A portion of a doped semiconductor fin may protrude through a first doped layer. An intrinsic layer may be disposed on the protruding semiconductor fin. A second semiconductor layer may be disposed on the intrinsic layer, thereby forming a PIN diode compatible with FinFET technology and having increased junction area.

Abstract: In deposited silicon, n-type dopants such as phosphorus and arsenic tend to seek the surface of the silicon, rising as the layer is deposited. When a second undoped or p-doped silicon layer is deposited on n-doped silicon with no n-type dopant provided, a first thickness of this second silicon layer nonetheless tends to include unwanted n-type dopant which has diffused up from lower levels. This surface-seeking behavior diminishes when germanium is alloyed with the silicon. In some devices, it may not be advantageous for the second layer to have significant germanium content. In the present invention, a first heavily n-doped semiconductor layer (preferably at least 10 at % germanium) is deposited, followed by a silicon-germanium capping layer with little or no n-type dopant, followed by a layer with little or no n-type dopant and less than 10 at % germanium. The germanium in the first layer and the capping layer minimizes diffusion of n-type dopant into the germanium-poor layer above.

Abstract: A horizontal germanium silicon heterostructure photodetector comprising a horizontal germanium p-i-n diode disposed over a horizontal parasitic silicon p-i-n diode uses silicon contacts for electrically coupling to the germanium p-i-n through the p-type doped and n-type doped regions in the silicon p-i-n without requiring direct physical contact to germanium material. The current invention may be optically coupled to on-chip and/or off-chip optical waveguide through end-fire or evanescent coupling. In some cases, the doping of the germanium p-type doped and/or n-type doped region may be accomplished based on out-diffusion of dopants in the doped silicon material of the underlying parasitic silicon p-i-n during high temperature steps in the fabrication process such as, the germanium deposition step(s), cyclic annealing, contact annealing and/or dopant activation.

Abstract: A Si-based diode (10, 10?, 100) is formed by epitaxially depositing a Si-based diode structure on a silicon substrate. The Si-based diode structure includes a Si-based pn junction (16, 16?, 18, 18?, 30, 32, 160, 161) having a backward diode current-voltage characteristic in which the forward tunneling current is substantially smaller than the backward tunneling current at comparable voltage levels. In some embodiments, the Si-based pn junction includes at least one non-silicon or silicon alloy layer such as at least one SiGe layer (16, 16?, 160, 161). In some embodiments, at least one delta doping (30, 32) is disposed on the silicon substrate in or near the pn junction, that together with the Si-based pn junction define an electrical junction having the backward diode current-voltage characteristic. A large area detector array may include a plurality of such Si-based diodes (10, 10?, 100).

Abstract: A combination of a thin-film ?c-Si and a-Si:H containing diode structure characterized by an ultra-high current density that exceeds 1000 A/cm2, comprising: a substrate; a bottom metal layer disposed on the substrate; an n-layer of ?c-Si deposited the bottom metal layer; an i-layer of ?c-Si deposited on the n-layer; a buffer layer of a-Si:H deposited on the i-layer, a p-layer of ?c-Si deposited on the buffer layer; and a top metal layer deposited on the p-layer.

Abstract: A method of forming a multiple layer passivation film on a semiconductor device surface comprises placing a semiconductor device in a chemical vapor deposition reactor, introducing a nitrogen source into the reactor, introducing a carbon source into the reactor, depositing a layer of carbon nitrogen on the semiconductor device surface, introducing a silicon source into the reactor after the carbon source, and depositing a layer of silicon carbon nitrogen on the carbon nitrogen layer. A semiconductor device incorporating the multiple layer passivation film is also described.

Abstract: Semiconductor devices and fabrication methods thereof. A first dielectric layer with a first conductor line along a first direction is disposed on a semiconductor substrate, wherein the top surface of the first conductor line is lower than the top surface of the first dielectric layer. A second dielectric layer comprising an opening corresponding to the first diode element is disposed on the first dielectric layer. A semiconductor diode component comprises a first diode element disposed on the first conductor line, wherein the top surface of the first diode element is level with the top surface of the first dielectric layer; and a second diode element and a third diode element are filled in the opening.

Abstract: A semiconductor junction device includes a semiconductor substrate of a first conductivity type and a junction layer formed on the substrate which has a second conductivity type. A field reducing region of the first conductivity type surrounds a periphery of the junction layer and extends under a peripheral portion of the junction layer. An insulating layer is provided on the field reducing region and a metal layer overlies the junction layer and the insulating layer.

Abstract: The invention provides a semiconductor device having a pn diode that includes a p-type SiGe layer and a n-type Si layer junctioned to the p-type SiGe layer. A built-in potential of the pn diode can be reduced, and thus obtaining a diode characteristics with lower impedance compared to the conventional scheme. Further, by forming a bridge-rectifier circuit with the pn diode or the like, alternating-current voltages can efficiently be converted into direct-current voltages. Accordingly, the invention provides a semiconductor device and method of manufacturing the same that can flow a larger electrical current in the forward direction of a diode by improving the voltage-current characteristics of the diode.

Abstract: An over-voltage protection device includes a substrate including an upper surface and a lower surface; a first electrode provided on the upper surface of the substrate; a second electrode provided on the lower surface on the substrate; a first conductive layer overlying the lower surface of the substrate, the first conductive region being a conductive region of a first type; a plurality of first conductive regions provided proximate the upper surface of the substrate, the plurality of first conductive regions being conductive regions of the first type; and a plurality of second conductive region provided proximate the upper surface of the substrate, the plurality of second conductive region being conductive regions of a second type. The plurality of the first conductive regions are provided in an alternating manner with the plurality of second conductive regions. The first electrode is contacting the plurality of the first and second conductive regions.

Abstract: In one embodiment, an optoelectronic device is provided having a pin photo diode including a semi-insulating substrate or layer, with a patterned implant region of a first dopant type. The pin photo diode includes an upper layer having semiconductor material with a second dopant type. An intermediate layer is provided having a substantially intrinsic semiconductor material. An upper layer contact is provided having a portion with a generally circular interior facing edge. The implant region has a first portion having an outer periphery substantially nonoverlapping with the interior facing edge of the upper layer contact. The implant region includes a contact portion located beyond the upper layer contact. A connecting portion couples the first portion and the contact portion of the implant region. In one embodiment, the device includes a heterojunction bipolar transistor coupled to the pin photo diode.

Abstract: An integrated circuit device for converting an incident optical signal into an electrical signal comprises a semiconductor substrate, a well region formed inside the semiconductor substrate, a dielectric layer formed over the well region, and a layer of polysilicon for receiving the incident optical signal, formed over the dielectric layer, including a p-type portion, an n-type portion and an undoped portion disposed between the p-type and n-type portions, wherein the well region is biased to control the layer of polysilicon for providing the electrical signal.

Abstract: A high-density Germanium (Ge)-on-Insulator (GOI) photodiode array and corresponding fabrication method are provided. The method includes: forming an array of pixel driver nMOST devices, each device having a gate connected to a row line in a first orientation, a first source/drain (S/D) region, and a second S/D region connected to Vdd; forming a P-I-N Ge diode for each pixel as follows: forming a n+ region; forming an intrinsic Ge region overlying the n+ region; forming a p+ junction in the intrinsic Ge; and, isolating the P-I-N Ge diodes; and, forming an Indium Tin oxide (ITO) column in a second orientation, about orthogonal to the first orientation, overlying the P-I-N Ge diodes.

Abstract: A diode circuit includes a pin diode structure, wherein the n-semiconductor layer is a buried layer, on which the i-area is deposited by an epitaxy method, and wherein a p-semiconductor layer is introduced into the epitaxy layer. A contacting of the p-semiconductor layer and a contacting of the n-semiconductor layer are arranged on the same main surface of the semiconductor substrate so that an integration with an integrated capacitor, an integrated resistor and/or an integrated inductor is possible.

Abstract: A bi-directional low capacitance TVS using a PIN or NIP diode is disclosed. Bi-directional low capacitance TVS protection circuit (1000) consists of two pairs of TVS diodes (1001), (1003) and LC PIN or NIP diodes (1002), (1004). Diodes (1003) and (1004) are in parallel and in opposite direction from a first series of TVS and LC diode pair. This circuit provides transient protection in both directions for a bi-directional low capacitance TVS.

Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer.

Abstract: A high resistance region may be used to isolate the body of a first transistor from a body contact.

Abstract: A semiconductor device including a base layer of a first conductivity type having a first main surface and a second main surface opposite the first main surface, a first main electrode layer connected to the first main surface, control regions arranged inside grooves penetrating the first main electrode layer and reach inside the base layer, and a second main electrode layer of the first conductivity type and connected to the second main surface.

Abstract: Impurity concentration (Nd(X)) in an n-drift layer in a diode is at a maximum at a position at a distance Xp from an anode electrode in a direction from the anode electrode to a cathode electrode, and gradually decreases from the position toward each of the anode electrode and the cathode electrode. A ratio of the peak impurity concentration Np to an averaged impurity concentration Ndm in the n-drift layer is in the range of 1 to 5. This provides a diode and a manufacturing method thereof by which oscillations in voltage and current at reverse recovery are inhibited to achieve enhancement both in high speed and low-loss characteristics and in soft recovery characteristics.

Abstract: A device for protecting I/O lines using PIN or NIP low capacitance transient voltage suppressors and steering diodes are disclosed. In an exemplary embodiment, a two (2) terminal device with a unidirectional low capacitance TVS diode (1101) and an anti-parallel LC PIN or NIP diode (1102) is disclosed. To provide for a low capacitance TVS with a forward conducting low-voltage characteristic, the LC PIN or NIP diode is placed anti-parallel to the unidirectional low capacitance TVS. This LC PIN or NIP diode must also have a reverse blocking voltage greater than the avalanche breakdown p-n junction voltage (V(BR)) of the unidirectional TVS.

Abstract: The present invention includes a photodiode having a first p-type semiconductor layer and an n-type semiconductor layer coupled by a second p-type semiconductor layer. The second p-type semiconductor layer has graded doping along the path of the carriers. In particular, the doping is concentration graded from a high value near the anode to a lower p concentration towards the cathode. By grading the doping in this way, an increase in absorption is achieved, improving the responsivity of the device. Although this doping increases the capacitance relative to an intrinsic semiconductor of the same thickness, the pseudo electric field that is created by the graded doping gives the electrons a very high velocity which more than compensates for this increased capacitance.

Abstract: A method and a structure of a diode are provided. The diode is used in an electrostatic discharge protection circuit using TFT (Thin Film Transistor) fabrication technology. A semiconductor layer is formed on a substrate. A first region of a first carrier concentration is formed in the semiconductor layer. A second region of a second carrier concentration is formed in the semiconductor layer. An insulator is formed on the semiconductor layer. The insulator layer is etched to form at least a contact window. The contact window exposes a portion of an upper surface of the semiconductor layer. A metal layer is formed on the insulator layer. The metal layer fills up the contact window to contact the semiconductor layer.

Abstract: An optical semiconductor device includes: a photo detector section which includes: a first semiconductor layer of a first conductivity type formed on a surface of a semiconductor substrate of the first conductivity type, a second semiconductor layer of a second conductivity type formed on a surface of the first semiconductor layer, and an antireflection film formed on a surface of the second semiconductor layer and preventing reflection of incident light; and a circuit element section which includes: a circuit element formed on the second semiconductor layer on the semiconductor substrate, and a passivation film covering an uppermost electrode layer among electrode layers constituting the circuit element and formed out of a same material as a material of the antireflection film.

Abstract: Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.

Abstract: Unidirectional and bi-directional low capacitance transient voltage suppressors (“TVS”) and steering diodes are disclosed. In one embodiment, the TVS comprise TVS p-n junction diode element(s), (101) low-capacitance (“LC”) PIN or NIP diode element(s) (102), the TVS p-n junction diode element(s) (101) being placed in series with and in opposite polarity to the LC PIN or NIP diodes (102). In another embodiment, the steering diode comprise only LC PIN or NIP diode(s) (402, 403) arranged as steering diodes.

Abstract: An electric component comprising an assembly of two PIN diodes in series formed in a semiconductor substrate layer separated from a support layer by an insulating layer, the doped areas forming the electrodes of each diode having a depth equal to that of the substrate layer, the component including a first area of a first doping type surrounded with a second intrinsic area, itself surrounded with a third area of a second doping type, the third area being surrounded with a fourth area of the first doping type, the fourth area being surrounded with a fifth intrinsic area, itself surrounded with a sixth area of the second doping type, the third and fourth areas being covered and connected by a metal area, each of the first and sixth areas being connected to a contact pad on which rests a welding ball.

Abstract: A diode structure is provided. The diode structure comprises a first conductive type substrate, a second conductive type first well region, a first conductive type second well region, a second conductive type first doped region, a first conductive type second doped region and a second conductive type third doped region. The first well region is located within the substrate and the second well region is located within the first well region. The first doped region is located within the first well region and detached from the second well region but adjacent to the surface of the substrate. The second doped region and the third doped region are located within the second well region and adjacent to the surface of the substrate. The second doped region is located between the first doped region and the third doped region but detached from both the first doped region and the third doped region.

Abstract: A semiconductor structure for high frequency operation has a substrate with a doped well formed therein and a buffer layer made of a substrate material covers the well. The buffer layer is made of an undoped material and is disposed on a top side of the well for inhibiting an outdiffusion of a dopant from the well. At least a portion of the substrate is not covered by the buffer layer.

Abstract: A new method to form an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a semiconductor substrate. An intrinsic semiconductor layer is formed overlying the dielectric layer. The intrinsic semiconductor layer is patterned. A p+ region is formed in the intrinsic semiconductor layer. An n+ region is formed in the intrinsic semiconductor layer. The p+ region and said n+ region are laterally separated by an intrinsic region to thereby form a PIN diode device. A source region and a drain region are formed in the semiconductor substrate to thereby complete a MOSFET device. The PIN diode device is a gate electrode for the MOSFET device.

Abstract: The invention concerns a low-capacity vertical diode designed to be mounted by a front surface made in a semiconductor substrate (1), comprising a first zone projecting relative to the surface of the substrate including at least a semiconductor layer (3) doped with a type of conductivity opposite to that of the substrate, the upper surface of the semiconductor layer bearing a first solder bump (23). The diode comprises a second zone including on the substrate a thick strip conductor (16) bearing at least second solder bumps (24), said first and second solder bumps defining a plane parallel to the substrate plane.

Abstract: A semiconductor device that helps to prevent the occurrence of current localization in the vicinity of an electrode edge and improves the reverse-recovery withstanding capability. The semiconductor device according to the invention includes a first carrier lifetime region, in which the carrier lifetime is short, formed in such a configuration that the first carrier lifetime region extends across the edge area of an anode electrode projection, which projects the anode electrode vertically into a semiconductor substrate. The first carrier lifetime region also includes a vertical boundary area spreading nearly vertically between a heavily doped p-type anode layer and a lightly doped semiconductor layer. The first carrier lifetime region of the invention is formed by irradiating with a particle beam, such as a He2+ ion beam or a proton beam.

Abstract: The invention concerns a low-capacity vertical diode designed to be mounted by a front surface made in a semiconductor substrate (1), comprising a first zone projecting relative to the surface of the substrate including at least a semiconductor layer (3) doped with a type of conductivity opposite to that of the substrate, the upper surface of the semiconductor layer bearing a first solder bump (23). The diode comprises a second zone including on the substrate a thick strip conductor (16) bearing at least second solder bumps (24), said first and second solder bumps defining a plane parallel to the substrate plane.

Abstract: A single-electrode, push-pull semiconductor PIN Mach-Zehnder modulator (10) that includes first and second PIN devices (12, 14) on a substrate (16). Intrinsic layers (22, 28) of the devices (12, 14) are the active regions of two arms (50, 52) of a Mach-Zehnder interferometer. An outer electrode (38) is connected to the N layer (24) of the first PIN device (12) and a center electrode (40) is connected to the P layer (20) of the first PIN device (12). An outer electrode (42) is connected to the P layer (26) of the second PIN device (14) and the center electrode (40) is connected to the N layer (30) of the second PIN device (14). An RF modulation signal biases the PIN devices (12, 14) in opposite directions and causes the index refraction of the intrinsic layers (22, 28) to change in opposite directions to give a push-pull modulation effect.

Abstract: A heterojunction P-I-N diode switch comprises a first layer of doped semiconductor material of a first doping type, a second layer of doped semiconductor material of a second doping type and a substrate on which is disposed the first and second layers. An intrinsic layer of semiconductor material is disposed between the first layer and second layer. The semiconductor material composition of at least one of the first layer and second layer is sufficiently different from that of the intrinsic layer so as to form a heterojunction therebetween, creating an energy barrier in which injected carriers from the junction are confined by the barrier, effectively reducing the series resistance within the I region of the P-I-N diode and the insertion loss relative to that of homojunction P-I-N diodes.

Abstract: An optical semiconductor device includes: a photo detector section which includes: a first semiconductor layer of a first conductivity type formed on a surface of a semiconductor substrate of the first conductivity type, a second semiconductor layer of a second conductivity type formed on a surface of the first semiconductor layer, and an antireflection film formed on a surface of the second semiconductor layer and preventing reflection of incident light; and a circuit element section which includes: a circuit element formed on the second semiconductor layer on the semiconductor substrate, and a passivation film covering an uppermost electrode layer among electrode layers constituting the circuit element and formed out of a same material as a material of the antireflection film.

Abstract: A method and a structure of a diode are provided. The diode is used in an electrostatic discharge protection circuit using TFT (Thin Film Transistor) fabrication technology. A semiconductor layer is formed on a substrate. A first region of a first carrier concentration is formed in the semiconductor layer. A second region of a second carrier concentration is formed in the semiconductor layer. An insulator is formed on the semiconductor layer. The insulator layer is etched to form at least a contact window. The contact window exposes a portion of an upper surface of the semiconductor layer. A metal layer is formed on the insulator layer. The metal layer fills up the contact window to contact the semiconductor layer.

Abstract: An electric component comprising an assembly of two PIN diodes in series formed in a semiconductor substrate layer separated from a support layer by an insulating layer, the doped areas forming the electrodes of each diode having a depth equal to that of the substrate layer, the component comprising a first area of a first doping type surrounded with a second intrinsic area, itself surrounded with a third area of a second doping type, the third area being surrounded with a fourth area of the first doping type, the fourth area being surrounded with a fifth intrinsic area, itself surrounded with a sixth area of the second doping type, the third and fourth areas being covered and connected by a metal area, each of the first and sixth areas being connected to a contact pad on which rests a welding ball.

Abstract: An image sensor and method of manufacture therefor includes a substrate having pixel control circuitry. Dielectric layers on the substrate include interconnects in contact with the pixel control circuitry and with pixel electrodes. An intrinsic layer is over the pixel electrodes and has a gap provided between the pixel electrodes. An intrinsic-layer covering layer is over the intrinsic layer and a transparent contact layer over the intrinsic-layer covering and the interconnects. The intrinsic, intrinsic-layer covering, and transparent contact layer interact in different combinations to provide a pixel isolation system for the image sensor.

Abstract: A method for forming an integrated circuit is provided. A semiconductor film is formed onto a first substrate. A metal film is formed onto a second substrate. The second substrate is bonded with the metal film onto the thin film of the first substrate. A first layer of transistors is formed onto the film. The second substrate is removed at a temperature within a low temperature range. The semiconductor film is bonded with the first layer of transistors onto a second layer of transistors of a third substrate.

Abstract: An enhanced extended drift heterostructure (EEDH) photodiode and method of making provide enhanced electron response. The EEDH photodiode includes adjacent first and second light absorption layers, an ohmic anode contact interfaced to the first layer and a cathode contact interfaced to the second layer. The cathode contact includes either a Schottky cathode contact or an ohmic cathode contact and a contact layer. The EEDH photodiode optionally further includes one or more of a carrier block layer interfaced to the first layer, a graded characteristic in the first layer, and a collector layer interfaced to the second layer. The first layer has a doping concentration that is greater than doping concentrations of the second layer and the optional collector layer. The first and second layers have band gap energies that facilitate light absorption. The optional layers have band gap energies that are relatively nonconducive to light absorption.

Abstract: A semiconductor diode includes a first semiconductor layer including a dopant having a first conductivity type. A second semiconductor layer is adjacent the first semiconductor layer and includes a dopant having the first conductivity type and having a dopant concentration less than a dopant concentration of the first semiconductor layer. Adjacent the second semiconductor layer is a third semiconductor layer including a dopant having the first conductivity type and having a dopant concentration greater than the dopant concentration of the second semiconductor layer. A fourth semiconductor layer is adjacent the third semiconductor layer and includes a dopant of a second conductivity type. Respective contacts are connected to the first and fourth semiconductor layers.

Abstract: A waveguide photodiode includes an n-type cladding layer, an n-type light confining layer, an i-type light absorption layer, a p-type light confining layer, and a p-type cladding layer buried in an Fe—InP blocking layer on a semiconductor substrate. At least one of the p-type light confining layer and the p-type cladding layer contains a p-type impurity selected from Be, Mg, and C. An undoped layer is preferably located between the i-type light absorption layer and the p-type light confining layer.

Abstract: A structure and method for a voltage blocking device comprises a cathode region, a drift region positioned on the cathode region, a gate region positioned on the drift region, an anode region positioned on the gate region and a plurality of contacts positioned on each of the cathode region, the gate region, and the anode region, wherein the drift region comprises multiple epilayers having first doped type layers surrounding second doped type layers, wherein dopant concentrations of the first doped type layers are lower than dopant concentrations of the second doped type layers. The epilayers comprise at least one i-n-i layer and/or at least one i-p-i layer. Moreover, the multiple epilayers are operable to block voltages in the device.

Abstract: A diamond pn junction diode includes a p-type diamond thin-film layer formed on a substrate and an n-type diamond thin-film layer formed by forming a high-quality undoped diamond thin-film layer on the p-type diamond thin-film layer and ion-implanting an impurity into the high-quality undoped diamond thin-film layer, or alternatively includes an n-type diamond thin-film layer formed on a substrate and a p-type diamond thin-film layer formed by forming a high-quality undoped diamond thin-film layer on the n-type diamond thin-film layer and ion-implanting an impurity into the high-quality undoped diamond thin-film layer.

Abstract: A blue-violet-near-ultraviolet pin-photodiode with small dark current, high reliability and long lifetime. The pin-photodiode has a metallic n-electrode, a n-ZnSe single crystal substrate, an optionally added n-ZnSe buffer layer, an n-Zn1-xMgxSySe1-y layer, an i-Zn1-xMgxSySe1-y layer, a p-Zn1-xMgxSySe1-y layer, a p-(ZnTe/ZnSe)m SLE, a p-ZnTe contact layer, an optionally provided antireflection film and a metallic p-electrode. A blue-violet-near-ultraviolet avalanche photodiode with small dark current, high reliability and long lifetime. The avalanche photodiode has a metallic n-electrode, a n-ZnSe single crystal substrate, an optionally added n-ZnSe buffer layer, an n-Zn1-xMgxSySe1-y layer, an i-Zn1-xMgxSySe1-y layer, a p-Zn1-xMgxSySe1-y layer, a p-(ZnTe/ZnSe)m SLE, a p-ZnTe contact layer, an optionally provided antireflection film and a metallic p-electrode. Upper sides of the layered structure are etched into a mesa-shape and coated with insulating films.

Abstract: The invention relates to an integrated chip diode manufactured by forming two different typed semiconductors on the top and bottom of a wafer respectively and forming a plurality of diodes thereon, each diode comprises glass insulator encapsulated on sides thereof, two conductive metal layers formed on the surfaces of the semiconductors respectively, an insulation material coated on a portion of the surface of one conductive metal layer and a third conductive metal layer sintered on the glass insulator, such that the other conductive metal layer can be electrically connected to the insulation material on the one conductive metal layer via the third conductive metal layer. Thus, two independent soldered conductive terminals are formed at the same sides of the diodes and electrically connected to each of different typed semiconductors.

Abstract: A multi-layer Auger suppressed diode having at least two exclusion interfaces and at least two extraction interfaces. A specific embodiment has two composite contacts, each consisting of a heavily doped layer (3, 4) and a buffer layer (8, 9) of lower doped, high bandgap material sandwiched between the heavily doped layer and the active region (2) of the device.