With High Resistivity (e.g., "intrinsic") Layer Between P And N Layers (e.g., Pin Diode) Patents (Class 257/656)
  • Patent number: 7176546
    Abstract: A diode circuit includes a pin diode structure, wherein the n-semiconductor layer is a buried layer, on which the i-area is deposited by an epitaxy method, and wherein a p-semiconductor layer is introduced into the epitaxy layer. A contacting of the p-semiconductor layer and a contacting of the n-semiconductor layer are arranged on the same main surface of the semiconductor substrate so that an integration with an integrated capacitor, an integrated resistor and/or an integrated inductor is possible.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: February 13, 2007
    Assignee: Infineon Technologies AG
    Inventors: Carsten Ahrens, Wolfgang Hartung, Holger Heuermann, Reinhard Losehand, Josef-Paul Schaffer
  • Patent number: 7164568
    Abstract: A bi-directional low capacitance TVS using a PIN or NIP diode is disclosed. Bi-directional low capacitance TVS protection circuit (1000) consists of two pairs of TVS diodes (1001), (1003) and LC PIN or NIP diodes (1002), (1004). Diodes (1003) and (1004) are in parallel and in opposite direction from a first series of TVS and LC diode pair. This circuit provides transient protection in both directions for a bi-directional low capacitance TVS.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: January 16, 2007
    Assignee: Microsemi Corporation
    Inventor: Cecil Kent Walters
  • Patent number: 7138697
    Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Jack O. Chu, Gabriel K. Dehlinger, Alfred Grill, Steven J. Koester, Qiging Ouyang, Jeremy D. Schaub
  • Patent number: 7112867
    Abstract: A high resistance region may be used to isolate the body of a first transistor from a body contact.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: September 26, 2006
    Assignee: Intel Corporation
    Inventors: Ian Rippke, Stewart Taylor
  • Patent number: 7102207
    Abstract: A semiconductor device including a base layer of a first conductivity type having a first main surface and a second main surface opposite the first main surface, a first main electrode layer connected to the first main surface, control regions arranged inside grooves penetrating the first main electrode layer and reach inside the base layer, and a second main electrode layer of the first conductivity type and connected to the second main surface.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: September 5, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoki Inoue, Koichi Sugiyama, Hideaiki Ninomiya, Tsuneo Ogura
  • Patent number: 7091579
    Abstract: Impurity concentration (Nd(X)) in an n-drift layer in a diode is at a maximum at a position at a distance Xp from an anode electrode in a direction from the anode electrode to a cathode electrode, and gradually decreases from the position toward each of the anode electrode and the cathode electrode. A ratio of the peak impurity concentration Np to an averaged impurity concentration Ndm in the n-drift layer is in the range of 1 to 5. This provides a diode and a manufacturing method thereof by which oscillations in voltage and current at reverse recovery are inhibited to achieve enhancement both in high speed and low-loss characteristics and in soft recovery characteristics.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: August 15, 2006
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Michio Nemoto
  • Patent number: 7084486
    Abstract: A device for protecting I/O lines using PIN or NIP low capacitance transient voltage suppressors and steering diodes are disclosed. In an exemplary embodiment, a two (2) terminal device with a unidirectional low capacitance TVS diode (1101) and an anti-parallel LC PIN or NIP diode (1102) is disclosed. To provide for a low capacitance TVS with a forward conducting low-voltage characteristic, the LC PIN or NIP diode is placed anti-parallel to the unidirectional low capacitance TVS. This LC PIN or NIP diode must also have a reverse blocking voltage greater than the avalanche breakdown p-n junction voltage (V(BR)) of the unidirectional TVS.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: August 1, 2006
    Assignee: Microsemi Corporation
    Inventor: Cecil Kent Walters
  • Patent number: 7078741
    Abstract: The present invention includes a photodiode having a first p-type semiconductor layer and an n-type semiconductor layer coupled by a second p-type semiconductor layer. The second p-type semiconductor layer has graded doping along the path of the carriers. In particular, the doping is concentration graded from a high value near the anode to a lower p concentration towards the cathode. By grading the doping in this way, an increase in absorption is achieved, improving the responsivity of the device. Although this doping increases the capacitance relative to an intrinsic semiconductor of the same thickness, the pseudo electric field that is created by the graded doping gives the electrons a very high velocity which more than compensates for this increased capacitance.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: July 18, 2006
    Assignee: Picometrix, Inc.
    Inventors: Cheng C. Ko, Barry Levine
  • Patent number: 7064418
    Abstract: A method and a structure of a diode are provided. The diode is used in an electrostatic discharge protection circuit using TFT (Thin Film Transistor) fabrication technology. A semiconductor layer is formed on a substrate. A first region of a first carrier concentration is formed in the semiconductor layer. A second region of a second carrier concentration is formed in the semiconductor layer. An insulator is formed on the semiconductor layer. The insulator layer is etched to form at least a contact window. The contact window exposes a portion of an upper surface of the semiconductor layer. A metal layer is formed on the insulator layer. The metal layer fills up the contact window to contact the semiconductor layer.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: June 20, 2006
    Assignee: Toppoly Optoelectronics Corp.
    Inventors: Ying-Hsin Li, Sheng-Chieh Yang, An Shih, Ming-Dou Ker, Tang-Kui Tseng, Chih-Kang Deng
  • Patent number: 7042059
    Abstract: An optical semiconductor device includes: a photo detector section which includes: a first semiconductor layer of a first conductivity type formed on a surface of a semiconductor substrate of the first conductivity type, a second semiconductor layer of a second conductivity type formed on a surface of the first semiconductor layer, and an antireflection film formed on a surface of the second semiconductor layer and preventing reflection of incident light; and a circuit element section which includes: a circuit element formed on the second semiconductor layer on the semiconductor substrate, and a passivation film covering an uppermost electrode layer among electrode layers constituting the circuit element and formed out of a same material as a material of the antireflection film.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: May 9, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yukiko Kashiura
  • Patent number: 7038248
    Abstract: Hetero-structure semiconductor devices having first and second-type semiconductor junctions are disclosed. The hetero-structures are incorporated into pillar and rail-stack memory circuits improving the forward-to-reverse current ratios thereof.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: May 2, 2006
    Assignee: SanDisk Corporation
    Inventor: Thomas H. Lee
  • Patent number: 7009831
    Abstract: Unidirectional and bi-directional low capacitance transient voltage suppressors (“TVS”) and steering diodes are disclosed. In one embodiment, the TVS comprise TVS p-n junction diode element(s), (101) low-capacitance (“LC”) PIN or NIP diode element(s) (102), the TVS p-n junction diode element(s) (101) being placed in series with and in opposite polarity to the LC PIN or NIP diodes (102). In another embodiment, the steering diode comprise only LC PIN or NIP diode(s) (402, 403) arranged as steering diodes.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: March 7, 2006
    Assignee: Microsemi Corporation
    Inventor: Cecil Kent Walters
  • Patent number: 7005725
    Abstract: An electric component comprising an assembly of two PIN diodes in series formed in a semiconductor substrate layer separated from a support layer by an insulating layer, the doped areas forming the electrodes of each diode having a depth equal to that of the substrate layer, the component including a first area of a first doping type surrounded with a second intrinsic area, itself surrounded with a third area of a second doping type, the third area being surrounded with a fourth area of the first doping type, the fourth area being surrounded with a fifth intrinsic area, itself surrounded with a sixth area of the second doping type, the third and fourth areas being covered and connected by a metal area, each of the first and sixth areas being connected to a contact pad on which rests a welding ball.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: February 28, 2006
    Assignee: STMicroelectronics S.A.
    Inventor: Patrick Poveda
  • Patent number: 6972476
    Abstract: A diode structure is provided. The diode structure comprises a first conductive type substrate, a second conductive type first well region, a first conductive type second well region, a second conductive type first doped region, a first conductive type second doped region and a second conductive type third doped region. The first well region is located within the substrate and the second well region is located within the first well region. The first doped region is located within the first well region and detached from the second well region but adjacent to the surface of the substrate. The second doped region and the third doped region are located within the second well region and adjacent to the surface of the substrate. The second doped region is located between the first doped region and the third doped region but detached from both the first doped region and the third doped region.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: December 6, 2005
    Assignee: United Microelectronics Corp.
    Inventors: Shiao-Shien Chen, Tung-Yang Chen, Tien-Hao Tang
  • Patent number: 6949812
    Abstract: A semiconductor structure for high frequency operation has a substrate with a doped well formed therein and a buffer layer made of a substrate material covers the well. The buffer layer is made of an undoped material and is disposed on a top side of the well for inhibiting an outdiffusion of a dopant from the well. At least a portion of the substrate is not covered by the buffer layer.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: September 27, 2005
    Assignee: Infineon Technologies AG
    Inventors: Reinhard Losehand, Hubert Werthmann
  • Patent number: 6936895
    Abstract: A new method to form an integrated circuit device is achieved. The method comprises forming a dielectric layer overlying a semiconductor substrate. An intrinsic semiconductor layer is formed overlying the dielectric layer. The intrinsic semiconductor layer is patterned. A p+ region is formed in the intrinsic semiconductor layer. An n+ region is formed in the intrinsic semiconductor layer. The p+ region and said n+ region are laterally separated by an intrinsic region to thereby form a PIN diode device. A source region and a drain region are formed in the semiconductor substrate to thereby complete a MOSFET device. The PIN diode device is a gate electrode for the MOSFET device.
    Type: Grant
    Filed: October 9, 2003
    Date of Patent: August 30, 2005
    Assignees: Chartered Semiconductor Manufacturing Ltd., Agilent Technologies, Inc.
    Inventors: Indrajit Manna, Keng Foo Lo, Pee Ya Tan, Raymond Filippi
  • Patent number: 6924546
    Abstract: The invention concerns a low-capacity vertical diode designed to be mounted by a front surface made in a semiconductor substrate (1), comprising a first zone projecting relative to the surface of the substrate including at least a semiconductor layer (3) doped with a type of conductivity opposite to that of the substrate, the upper surface of the semiconductor layer bearing a first solder bump (23). The diode comprises a second zone including on the substrate a thick strip conductor (16) bearing at least second solder bumps (24), said first and second solder bumps defining a plane parallel to the substrate plane.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: August 2, 2005
    Assignee: STMicroelectronics S.A.
    Inventors: Emmanuel Collard, Patrick Poveda
  • Patent number: 6870199
    Abstract: A semiconductor device that helps to prevent the occurrence of current localization in the vicinity of an electrode edge and improves the reverse-recovery withstanding capability. The semiconductor device according to the invention includes a first carrier lifetime region, in which the carrier lifetime is short, formed in such a configuration that the first carrier lifetime region extends across the edge area of an anode electrode projection, which projects the anode electrode vertically into a semiconductor substrate. The first carrier lifetime region also includes a vertical boundary area spreading nearly vertically between a heavily doped p-type anode layer and a lightly doped semiconductor layer. The first carrier lifetime region of the invention is formed by irradiating with a particle beam, such as a He2+ ion beam or a proton beam.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: March 22, 2005
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Ko Yoshikawa, Michio Nemoto, Takeshi Fujii
  • Publication number: 20040207050
    Abstract: The invention concerns a low-capacity vertical diode designed to be mounted by a front surface made in a semiconductor substrate (1), comprising a first zone projecting relative to the surface of the substrate including at least a semiconductor layer (3) doped with a type of conductivity opposite to that of the substrate, the upper surface of the semiconductor layer bearing a first solder bump (23). The diode comprises a second zone including on the substrate a thick strip conductor (16) bearing at least second solder bumps (24), said first and second solder bumps defining a plane parallel to the substrate plane.
    Type: Application
    Filed: March 10, 2004
    Publication date: October 21, 2004
    Inventors: Emmanuel Collard, Patrick Poveda
  • Publication number: 20040201079
    Abstract: A single-electrode, push-pull semiconductor PIN Mach-Zehnder modulator (10) that includes first and second PIN devices (12, 14) on a substrate (16). Intrinsic layers (22, 28) of the devices (12, 14) are the active regions of two arms (50, 52) of a Mach-Zehnder interferometer. An outer electrode (38) is connected to the N layer (24) of the first PIN device (12) and a center electrode (40) is connected to the P layer (20) of the first PIN device (12). An outer electrode (42) is connected to the P layer (26) of the second PIN device (14) and the center electrode (40) is connected to the N layer (30) of the second PIN device (14). An RF modulation signal biases the PIN devices (12, 14) in opposite directions and causes the index refraction of the intrinsic layers (22, 28) to change in opposite directions to give a push-pull modulation effect.
    Type: Application
    Filed: April 10, 2003
    Publication date: October 14, 2004
    Inventors: David C. Scott, Timothy A. Vang, Wenshen Wang, Elizabeth T. Kunkee
  • Patent number: 6794734
    Abstract: A heterojunction P-I-N diode switch comprises a first layer of doped semiconductor material of a first doping type, a second layer of doped semiconductor material of a second doping type and a substrate on which is disposed the first and second layers. An intrinsic layer of semiconductor material is disposed between the first layer and second layer. The semiconductor material composition of at least one of the first layer and second layer is sufficiently different from that of the intrinsic layer so as to form a heterojunction therebetween, creating an energy barrier in which injected carriers from the junction are confined by the barrier, effectively reducing the series resistance within the I region of the P-I-N diode and the insertion loss relative to that of homojunction P-I-N diodes.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: September 21, 2004
    Assignee: MIA-COM
    Inventors: David Russell Hoag, Timothy Edward Boles, James Joseph Brogle
  • Patent number: 6791153
    Abstract: An optical semiconductor device includes: a photo detector section which includes: a first semiconductor layer of a first conductivity type formed on a surface of a semiconductor substrate of the first conductivity type, a second semiconductor layer of a second conductivity type formed on a surface of the first semiconductor layer, and an antireflection film formed on a surface of the second semiconductor layer and preventing reflection of incident light; and a circuit element section which includes: a circuit element formed on the second semiconductor layer on the semiconductor substrate, and a passivation film covering an uppermost electrode layer among electrode layers constituting the circuit element and formed out of a same material as a material of the antireflection film.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: September 14, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yukiko Kashiura
  • Publication number: 20040164381
    Abstract: A method and a structure of a diode are provided. The diode is used in an electrostatic discharge protection circuit using TFT (Thin Film Transistor) fabrication technology. A semiconductor layer is formed on a substrate. A first region of a first carrier concentration is formed in the semiconductor layer. A second region of a second carrier concentration is formed in the semiconductor layer. An insulator is formed on the semiconductor layer. The insulator layer is etched to form at least a contact window. The contact window exposes a portion of an upper surface of the semiconductor layer. A metal layer is formed on the insulator layer. The metal layer fills up the contact window to contact the semiconductor layer.
    Type: Application
    Filed: February 20, 2004
    Publication date: August 26, 2004
    Inventors: Ying-Hsin Li, Sheng-Chieh Yang, An Shih, Ming-Dou Ker, Tang-Kui Tseng, Chih-Kang Deng
  • Publication number: 20040135235
    Abstract: An electric component comprising an assembly of two PIN diodes in series formed in a semiconductor substrate layer separated from a support layer by an insulating layer, the doped areas forming the electrodes of each diode having a depth equal to that of the substrate layer, the component comprising a first area of a first doping type surrounded with a second intrinsic area, itself surrounded with a third area of a second doping type, the third area being surrounded with a fourth area of the first doping type, the fourth area being surrounded with a fifth intrinsic area, itself surrounded with a sixth area of the second doping type, the third and fourth areas being covered and connected by a metal area, each of the first and sixth areas being connected to a contact pad on which rests a welding ball.
    Type: Application
    Filed: December 23, 2003
    Publication date: July 15, 2004
    Inventor: Patrick Poveda
  • Patent number: 6759262
    Abstract: An image sensor and method of manufacture therefor includes a substrate having pixel control circuitry. Dielectric layers on the substrate include interconnects in contact with the pixel control circuitry and with pixel electrodes. An intrinsic layer is over the pixel electrodes and has a gap provided between the pixel electrodes. An intrinsic-layer covering layer is over the intrinsic layer and a transparent contact layer over the intrinsic-layer covering and the interconnects. The intrinsic, intrinsic-layer covering, and transparent contact layer interact in different combinations to provide a pixel isolation system for the image sensor.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: July 6, 2004
    Assignee: Agilent Technologies, Inc.
    Inventors: Jeremy A. Theil, Dietrich W. Vook, Homayoon Haddad
  • Patent number: 6744116
    Abstract: A method for forming an integrated circuit is provided. A semiconductor film is formed onto a first substrate. A metal film is formed onto a second substrate. The second substrate is bonded with the metal film onto the thin film of the first substrate. A first layer of transistors is formed onto the film. The second substrate is removed at a temperature within a low temperature range. The semiconductor film is bonded with the first layer of transistors onto a second layer of transistors of a third substrate.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: June 1, 2004
    Assignee: Intel Corporation
    Inventor: Brian S. Doyle
  • Patent number: 6740908
    Abstract: An enhanced extended drift heterostructure (EEDH) photodiode and method of making provide enhanced electron response. The EEDH photodiode includes adjacent first and second light absorption layers, an ohmic anode contact interfaced to the first layer and a cathode contact interfaced to the second layer. The cathode contact includes either a Schottky cathode contact or an ohmic cathode contact and a contact layer. The EEDH photodiode optionally further includes one or more of a carrier block layer interfaced to the first layer, a graded characteristic in the first layer, and a collector layer interfaced to the second layer. The first layer has a doping concentration that is greater than doping concentrations of the second layer and the optional collector layer. The first and second layers have band gap energies that facilitate light absorption. The optional layers have band gap energies that are relatively nonconducive to light absorption.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: May 25, 2004
    Assignee: Agilent Technologies, Inc.
    Inventor: Kirk S. Giboney
  • Patent number: 6737731
    Abstract: A semiconductor diode includes a first semiconductor layer including a dopant having a first conductivity type. A second semiconductor layer is adjacent the first semiconductor layer and includes a dopant having the first conductivity type and having a dopant concentration less than a dopant concentration of the first semiconductor layer. Adjacent the second semiconductor layer is a third semiconductor layer including a dopant having the first conductivity type and having a dopant concentration greater than the dopant concentration of the second semiconductor layer. A fourth semiconductor layer is adjacent the third semiconductor layer and includes a dopant of a second conductivity type. Respective contacts are connected to the first and fourth semiconductor layers.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: May 18, 2004
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Praveen Muraleedharan Shenoy
  • Patent number: 6734519
    Abstract: A waveguide photodiode includes an n-type cladding layer, an n-type light confining layer, an i-type light absorption layer, a p-type light confining layer, and a p-type cladding layer buried in an Fe—InP blocking layer on a semiconductor substrate. At least one of the p-type light confining layer and the p-type cladding layer contains a p-type impurity selected from Be, Mg, and C. An undoped layer is preferably located between the i-type light absorption layer and the p-type light confining layer.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: May 11, 2004
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Masaharu Nakaji, Eitaro Ishimura
  • Patent number: 6734462
    Abstract: A structure and method for a voltage blocking device comprises a cathode region, a drift region positioned on the cathode region, a gate region positioned on the drift region, an anode region positioned on the gate region and a plurality of contacts positioned on each of the cathode region, the gate region, and the anode region, wherein the drift region comprises multiple epilayers having first doped type layers surrounding second doped type layers, wherein dopant concentrations of the first doped type layers are lower than dopant concentrations of the second doped type layers. The epilayers comprise at least one i-n-i layer and/or at least one i-p-i layer. Moreover, the multiple epilayers are operable to block voltages in the device.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: May 11, 2004
    Assignee: The United States of America as represented by the Secretary of the Army
    Inventor: Pankaj B. Shah
  • Patent number: 6727171
    Abstract: A diamond pn junction diode includes a p-type diamond thin-film layer formed on a substrate and an n-type diamond thin-film layer formed by forming a high-quality undoped diamond thin-film layer on the p-type diamond thin-film layer and ion-implanting an impurity into the high-quality undoped diamond thin-film layer, or alternatively includes an n-type diamond thin-film layer formed on a substrate and a p-type diamond thin-film layer formed by forming a high-quality undoped diamond thin-film layer on the n-type diamond thin-film layer and ion-implanting an impurity into the high-quality undoped diamond thin-film layer.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: April 27, 2004
    Inventors: Daisuke Takeuchi, Hideyuki Watanabe, Hideyo Okushi, Masataka Hasegawa, Masahiko Ogura, Naoto Kobayashi, Koji Kajimura, Sadanori Yamanaka
  • Patent number: 6724018
    Abstract: A blue-violet-near-ultraviolet pin-photodiode with small dark current, high reliability and long lifetime. The pin-photodiode has a metallic n-electrode, a n-ZnSe single crystal substrate, an optionally added n-ZnSe buffer layer, an n-Zn1-xMgxSySe1-y layer, an i-Zn1-xMgxSySe1-y layer, a p-Zn1-xMgxSySe1-y layer, a p-(ZnTe/ZnSe)m SLE, a p-ZnTe contact layer, an optionally provided antireflection film and a metallic p-electrode. A blue-violet-near-ultraviolet avalanche photodiode with small dark current, high reliability and long lifetime. The avalanche photodiode has a metallic n-electrode, a n-ZnSe single crystal substrate, an optionally added n-ZnSe buffer layer, an n-Zn1-xMgxSySe1-y layer, an i-Zn1-xMgxSySe1-y layer, a p-Zn1-xMgxSySe1-y layer, a p-(ZnTe/ZnSe)m SLE, a p-ZnTe contact layer, an optionally provided antireflection film and a metallic p-electrode. Upper sides of the layered structure are etched into a mesa-shape and coated with insulating films.
    Type: Grant
    Filed: August 27, 2002
    Date of Patent: April 20, 2004
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Koshi Ando, Takao Nakamura
  • Patent number: 6717237
    Abstract: The invention relates to an integrated chip diode manufactured by forming two different typed semiconductors on the top and bottom of a wafer respectively and forming a plurality of diodes thereon, each diode comprises glass insulator encapsulated on sides thereof, two conductive metal layers formed on the surfaces of the semiconductors respectively, an insulation material coated on a portion of the surface of one conductive metal layer and a third conductive metal layer sintered on the glass insulator, such that the other conductive metal layer can be electrically connected to the insulation material on the one conductive metal layer via the third conductive metal layer. Thus, two independent soldered conductive terminals are formed at the same sides of the diodes and electrically connected to each of different typed semiconductors.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: April 6, 2004
    Inventors: Chun-Hua Chen, Hsiao-Ping Chu
  • Patent number: 6700180
    Abstract: A semiconductor diode has a low bandgap layer (10) and an intermediate region (4) with a plurality of field relief regions (6, 8) extending between the low bandgap layer (10) and a first region (2) of opposite conductivity type. The field relief regions deplete the intermediate region in the off state of the diode.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: March 2, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Eddie Huang
  • Patent number: 6696705
    Abstract: A power semiconductor component having a mesa edge termination is described. The component has a semiconductor body with first and second surfaces. An inner zone of a first conductivity type is disposed in the semiconductor body. A first zone is disposed in the semiconductor body and is connected to the inner zone. An edge area outside of the first zone has areas etched out. A second zone of a second conductivity type is disposed in the semiconductor body and is connected to the inner zone, and a boundary area between the second zone and the inner zone defines a pn junction. A field stop zone is adjacent the first surface in the edge area. The field stop zone is formed of the first conductivity type and is embedded in the semiconductor body, and the field stop zone is connected to the first zone and to the inner zone.
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: February 24, 2004
    Assignee: Eupec Europaeische Gesellschaft fuer Leistungshalbleiter mbH & Co. KG
    Inventors: Reiner Barthelmess, Gerhard Schmidt
  • Patent number: 6690085
    Abstract: A semiconductor device has a first-conductivity-type semiconductor region, second-conductivity-type semiconductor region, and a high-resistance region. The first-conductivity-type semiconductor region is formed on a first-conductivity-type semiconductor body and has an electric resistance higher than that of the first-conductivity-type semiconductor body. The second-conductivity-type semiconductor region is formed on the first-conductivity-type semiconductor region. The high-resistance region is in contact with the first-conductivity-type and second-conductivity-type semiconductor regions and extends from the upper surface of the second-conductivity-type semiconductor region in the direction of the first-conductivity-type semiconductor body.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: February 10, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akio Nakagawa, Yusuke Kawaguchi
  • Patent number: 6677626
    Abstract: This invention achieves a high inverse voltage of a super-junction semiconductor device, which has a drift layer composed of a parallel pn layer that conducts electricity in the ON state and is depleted in the OFF state. An n− high resistance region is formed at the periphery of a drift layer composed of a parallel pn layer of n drift regions and p partition regions. The impurity density ND of the n− high resistance region is 5.62×1017×VDSS−1.36(cm−3) or less. VDSS denotes the withstand voltage (V). An n low resistance region is arranged adjacent to the n− high resistance region.
    Type: Grant
    Filed: November 10, 1999
    Date of Patent: January 13, 2004
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Youichi Shindou, Yasushi Miyasaka, Tatsuhiko Fujihira, Manabu Takei
  • Patent number: 6674152
    Abstract: A bipolar p-i-n diode has a first (1) and second (5) region of opposite conductivity type and an intermediate drift region (3) between the first and second regions. Trenched field relief regions (14) are arranged to deplete the intermediate drift region (3) when the diode is reverse biased, so permitting a higher doping (12) to be used for the intermediate drift region (3) for a given breakdown voltage. This improves both the turn-on and turn-off characteristics of the diode.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: January 6, 2004
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Eddie Huang
  • Patent number: 6649993
    Abstract: An active pixel sensor having a transparent conductor that directly contacts a conductive element in an interconnection structure to electrically connect the transparent conductor to a pixel sensor bias voltage is provided. The active pixel sensor includes a semiconductor substrate, the interconnection layer, which is formed over the substrate, and a pixel interconnection layer formed over the interconnection layer. Photo sensors that include a pixel electrode, an I-layer, and may include a P-layer are formed over the pixel interconnection layer. The transparent conductor is formed over the photo sensors and the conductive element exposed on the surface of the interconnection layer.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: November 18, 2003
    Assignee: Agilent Technologies, Inc.
    Inventor: Jeremy A. Theil
  • Patent number: 6635899
    Abstract: In a semiconductor element comprising microcrystalline semiconductor, a semiconductor junction is provided within a microcrystal grain. Further, in a semiconductor element comprising microcrystalline semiconductor, providing microcrystal grains of different grain diameters as a mixture to form a semiconductor layer. Thereby, discontinuity of a semiconductor junction is improved to improve the characteristics, durability, and heat resisting properties of a semiconductor element. Distortion in a semiconductor layer is also reduced.
    Type: Grant
    Filed: April 23, 2001
    Date of Patent: October 21, 2003
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keishi Saito, Masafumi Sano
  • Publication number: 20030193077
    Abstract: A device isolation region surrounds first and second device regions of a semiconductor substrate and a patterned deep-trench isolation region is embedded through the device isolation region into the substrate. First and second bipolar transistors are respectively formed in the device regions. Each transistor has a collector region and a base region in the substrate, and an emitter embedded in an insulation layer above the base region. Space savings, low collector resistance and low collector-substrate capacitance are achieved by embedding a collector trench contact into boundary portions of the deep-trench and device isolation regions deeper into the substrate to establish an electrical contact with the corrector region. With a single photoetching process, the insulation layer is etched to create openings for the collector trenches simultaneously with openings for the emitters and base regions.
    Type: Application
    Filed: April 11, 2003
    Publication date: October 16, 2003
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Hiroki Fujii
  • Patent number: 6624494
    Abstract: A power semiconductor device and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material into a portion of the epitaxial layer adjacent to and beneath the bottom of the trench. The dopant is diffused to form a first doped layer in the epitaxial layer and the barrier material is removed from at least the bottom of the trench. The trench is etched through the first doped layer and a filler material is deposited in the trench to substantially fill the trench, thus completing the voltage sustaining region.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: September 23, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Richard A. Blanchard, Jean-Michel Guillot
  • Patent number: 6617670
    Abstract: A surface PIN (SPIN) device and a method of fabricating such a SPIN device. The SPIN device, when activated, confines carrier injection to a small volume near the surface of the device such that the device is sufficiently conductive to simulate a planar conductor. The SPIN device comprises a P+ region and an N+ region formed in an intrinsic (I) layer. The P+ and N+ regions are separated by a lateral length of intrinsic material of length L. The length L is approximately the carrier diffusion length. When DC bias is applied across the N+ and P+ regions carriers are injected into the intrinsic region at a density exceeding 1018 carriers per cubic cm. The intrinsic region is sufficiently thin to confine the carriers near the surface of the intrinsic region. As such, in the “on” state, the SPIN device simulates a conductive material. In the “off” state, the SPIN device is no longer conductive.
    Type: Grant
    Filed: March 20, 2001
    Date of Patent: September 9, 2003
    Assignee: Sarnoff Corporation
    Inventors: Gordon C. Taylor, Arye Rosen, Aly E. Fathy, Pradyumna K. Swain, Stewart M. Perlow
  • Patent number: 6603153
    Abstract: A soft recovery diode is made by first implanting helium into the die to a location below the P/N junction and the implant annealed. An E-beam radiation process then is applied to the entire wafer and is also annealed. The diode then has very soft recovery characteristics without requiring heavy metal doping.
    Type: Grant
    Filed: May 21, 2001
    Date of Patent: August 5, 2003
    Assignee: International Rectifier Corporation
    Inventors: Richard Francis, Chiu Ng
  • Patent number: 6583443
    Abstract: A light emitting epi-layer structure which contains a temporality light absorption substrate on one side, the other side thereof can be adhered to a light absorption free transparent substrate in terms of a transparent adhesive layer which is light absorption free too. After that, the light absorption substrate portion is removed by means of an etching process. The resulted light emitting diode has significant improvement in light emitting efficiency. Moreover, the transparent conductive layer is a low resistance and high transparency layer. The current flow can thus be distributed evenly than conventional one.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: June 24, 2003
    Assignee: United Epitaxy Co., Ltd.
    Inventors: Chih-Sung Chang, Kuang-Neng Yang, Tzer-Perng Chen
  • Publication number: 20030111704
    Abstract: An image sensor and method of manufacture therefor includes a substrate having pixel control circuitry. Dielectric layers on the substrate include interconnects in contact with the pixel control circuitry and with pixel electrodes. An intrinsic layer is over the pixel electrodes and has a gap provided between the pixel electrodes. An intrinsic-layer covering layer is over the intrinsic layer and a transparent contact layer over the intrinsic-layer covering and the interconnects. The intrinsic, intrinsic-layer covering, and transparent contact layer interact in different combinations to provide a pixel isolation system for the image sensor.
    Type: Application
    Filed: December 18, 2001
    Publication date: June 19, 2003
    Inventors: Jeremy A. Theil, Dietrich W. Vook, Homayoon Haddad
  • Publication number: 20030102534
    Abstract: A semiconductor diode has a low bandgap layer (10) and an intermediate region (4) with a plurality of field relief regions (6, 8) extending between the low bandgap layer (10) and a first region (2) of opposite conductivity type. The field relief regions deplete the intermediate region in the off state of the diode.
    Type: Application
    Filed: November 26, 2002
    Publication date: June 5, 2003
    Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.
    Inventor: Eddie Huang
  • Patent number: 6559481
    Abstract: A semiconductor device such as an IGBT, for realizing measurement precision for forward voltage effect characteristics using a relatively small current. It includes a second conductivity type of first anode region formed to partially constitute the upper surface of a first conductivity type of semiconductor substrate and having an anode electrode formed on its upper surface, a second anode region formed within said first anode region, and an anode electrode formed on said second anode region. The second anode region is electrically isolated from the first anode region, and the anode electrode formed on the upper surface of the second anode region is independent of the anode electrode formed on the upper surface of the first anode region. In such semiconductor device having said second anode region, even though a small force current, measurement can be performed at a current density which is equal to or close to a rated current.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: May 6, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kazushige Matsuo, Eisuke Suekawa, Kouichi Mochizuki
  • Patent number: 6538299
    Abstract: A semiconductor device (and method for forming the device) includes a silicon-on-insulator (SOI) wafer formed on a substrate surface. An isolation trench in the wafer surface surrounds alternating p-type trenches and n-type trenches and electrically isolates the device from the substrate, thereby allowing the device to be effectively utilized as a differential detector in an optoelectronic circuit.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: March 25, 2003
    Assignee: International Business Machines Corporation
    Inventors: Young H. Kwark, Dan Moy, Mark B. Ritter, Dennis L. Rogers, Jeffrey J. Welser
  • Patent number: RE38582
    Abstract: A multi-layer Auger suppressed diode having at least two exclusion interfaces and at least two extraction interfaces. A specific embodiment has two composite contacts, each consisting of a heavily doped layer (3, 4) and a buffer layer (8, 9) of lower doped, high bandgap material sandwiched between the heavily doped layer and the active region (2) of the device.
    Type: Grant
    Filed: June 26, 2002
    Date of Patent: September 14, 2004
    Assignee: QinetiQ Limited
    Inventor: Anthony M. White