Abstract: A method and apparatus for decoupling conductive portions of a microelectronic device package. In one embodiment, the package can include a microelectronic substrate and a conductive member positioned at least proximate to the microelectronic substrate. The conductive member can have first and second neighboring conductive portions with at least a part of the first conductive portions spaced apart from a part of the neighboring second conductive portion to define an intermediate region between the first and second conductive portions. Each conductive portion has a bond region electrically coupled to the microelectronic substrate. A dielectric material is positioned adjacent to the first and second conductive portions in the intermediate region and has a dielectric constant of less than about 3.5.

Abstract: An electronic component includes a first component and a second component, each having a surface that includes a plurality of exposed contacts separated by an insulating material. A sandwich layer is disposed between the surface of the first component and the surface of the second component. The surface of the first component is then attached to the surface of the second component with the sandwich layer therebetween. The sandwich layer forms conductive areas between contacts of the first component and contacts of the second component and forms an insulator between the conductive areas.

Abstract: A routing element for use in a semiconductor device assembly includes a substrate that carries conductive traces that provide either additional electrical paths or shorter electrical paths than those provided by a carrier substrate of the semiconductor device assembly. The conductive traces may be carried upon a single surface of the routing element substrate, be carried internally by the routing element substrate, or include externally and internally carried portions. The routing element may also include a contact pad positioned at each end of each conductive trace thereof to facilitate electrical connection of each conductive trace to a corresponding terminal of the substrate or to a corresponding bond pad of a semiconductor device of the multichip module. Multichip modules are also disclosed, as are methods for designing the routing element and methods in which the routing element is used.

Abstract: A semiconductor device includes: an insulating tape having a device hole and a plurality of holes; a plurality of leads formed on one surface of the tape and extending at one end into the device hole and at the other end into the holes; a semiconductor chip having a plurality of electrodes on a main surface thereof, being connected with the leads extending into the device hole; an encapsulant formed of an insulating resin, the leads and a predetermined portion of the tape; bump electrodes provided on one surface of the leads; slits provided in the tape between the encapsulant and the bump electrodes and extending along a column of the bump electrodes; and a warp prevention reinforcement made of an insulating film and formed over the tape; wherein the semiconductor chip and the bump electrodes are connected to one and the same surface side of the leads.

Abstract: A semiconductor chip package may include a substrate, which may have bonding pads formed thereon. A semiconductor chip mounted on the substrate may have chip pads, and electrical connections for connecting the chip pads of the semiconductor chip to the substrate bonding pads. The semiconductor chip and the electrical connections on the substrate may be encapsulated, and a board attached to a portion of a surface of the substrate may not be encapsulated.

Abstract: In the semiconductor device of the present invention, there are provided output terminals on two sides perpendicular to one of four sides which is nearest output outer leads of a liquid crystal driver chip mounted to a flexible substrate. The wires extending from the inner leads connected to the output terminals to the output outer leads do not need to travel around a liquid crystal driver chip. The flexible substrate can be scaled down. Yields can be increased.

Abstract: The present disclosure suggests various microelectronic component assembly designs and methods for manufacturing microelectronic component assemblies. In one particular implementation, a microelectronic component assembly includes a microelectronic component, a substrate, and at least one bond wire. The substrate has a reduced-thickness base adjacent terminals of the microelectronic component and a body having a contact surface spaced farther from the microelectronic component than a bond pad surface of the base. The bond wire couples the microelectronic component to a bond pad carried by the bond pad surface and has a maximum height outwardly from the microelectronic component that is no greater than the height of the contact surface from the microelectronic component.

Abstract: A heated glass panel assembly according to one embodiment of the invention may include a substrate having an electro-conductive film provided thereon. A conductor is positioned in contact with the electro-conductive film. A resilient material is positioned in contact with the conductor so that at least a portion of the conductor is located between the resilient material and the electro-conductive film. A retainer is positioned in contact with the resilient material so that at least a portion of the resilient material and at least a portion of the conductor are located between the retainer and the electro-conductive film. The retainer applies a compressive pressure to the resilient material which transfers at least a portion of the compressive pressure to the conductor to hold the conductor in contact with the electro-conductive film.

Abstract: A semiconductor chip includes: a semiconductor substrate; a penetrating electrode which is formed through the semiconductor substrate from a first surface to a second surface of the semiconductor substrate and has a projection which projects from the second surface; an insulating layer formed over an entire surface of the second surface. The insulating layer includes a first insulating section formed in a region around the projection and a second insulating section other than the first insulating section. The second insulating section is formed to be thinner than a thickest area of the first insulating section.

Abstract: Packaging and encapsulation methods include use of a tape substrate with a mold gate that includes an aperture and a support element that extends over at least a portion of the aperture. The tape substrate may be part of a strip. A semiconductor device is secured and electrically connected to the tape substrate. The resulting assembly is placed into a cavity of a mold, and encapsulant is introduced into the cavity through the mold gate of the tape substrate. Once the encapsulant has sufficiently hardened, the package assembly may be removed from the mold, and a sprue of residual encapsulant removed therefrom. If the package assembly is carried by a strip that carries other package assemblies, it may be removed from the strip.

Abstract: An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as its modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established by considering the relative density in opposing conductive build-up layers above and below the core region.

Abstract: According to the present invention, a semiconductor package includes a semiconductor chip; a base member on which the semiconductor chip is mounted; a plurality of leads formed on the base member, the leads including inner ends electrically connected to the semiconductor chip and outer ends; and an index for identifying locations of specific leads.

Abstract: A wiring board comprising: a plate core having a first main surface and a second main surface; conductor layers including a conductor line; dielectric layers laminated alternately with said conductor layers on at least one of said first and second main surfaces; via conductors as defined herein; a signal through-hole as defined herein; a signal through-hole conductor as defined herein; a first path end pad as defined herein; a second path end pad as defined herein; a shield through-hole as defined herein; and a shield through-hole conductor as defined herein; wherein: a signal transmission path is formed as defined herein; at least one of said conductor layers is disposed on each of said first and second main surface sides; said surface conductor on said first main surface side and said conductor line form a strip line, a microstrip line, or a coplanar waveguide with constant characteristic impedance Z0; an inner surface of said shield through-hole is covered with said shield through-hole conductor; and an in

Abstract: The present invention provides an indexed support substrate. The support substrate comprises at least one set of indexing features that are distinguishable from one another and from the surrounding substrate. The support substrate also comprises a set of useful domains. The indexing features are positioned on the substrate in such a way as to correspond to the useful domains in an identifying fashion.

Abstract: A tape circuit substrate and semiconductor apparatus employing the same, and a method for forming a tape circuit substrate may reduce or eliminate electromagnetic interference (EMI) and provide a substrate or apparatus which can supply a more stable power supply voltage. The tape circuit substrate may include an insulation film and a wiring pattern formed on the insulation film to define an electronic device-mounting region and including a ground electrode. The tape circuit substrate may include a ground electrode pattern formed at the electronic device-mounting region so as to be insulated from the wiring pattern, except where the ground electrode pattern is connected to the ground electrode.

Abstract: A semiconductor device has an improved mounting reliability and has external terminals formed by exposing portions of leads from a back surface of a resin sealing member. End portions on one side of the leads are fixed to a back surface of a semiconductor chip, and portions of the leads positioned outside the semiconductor chip are connected with electrodes formed on the semiconductor chip through wires.

Abstract: In one aspect, the invention provides a semiconductor device that comprises a semiconductor device packaging substrate core. A first interconnect structure is located within a mold region and on a die side of the substrate core and has a first conductive metal density associated therewith. A second interconnect structure is located within the mold region and on a solder joint side of the substrate core and has a second conductive metal density associated therewith, wherein the second conductive metal density within the mold region is about equal to or less than the first conductive metal density within the mold region.

Abstract: A microsystem-on-a-chip comprises a bottom wafer of normal thickness and a series of thinned wafers can be stacked on the bottom wafer, glued and electrically interconnected. The interconnection layer comprises a compliant dielectric material, an interconnect structure, and can include embedded passives. The stacked wafer technology provides a heterogeneously integrated, ultra-miniaturized, higher performing, robust and cost-effective microsystem package. The highly integrated microsystem package, comprising electronics, sensors, optics, and MEMS, can be miniaturized both in volume and footprint to the size of a bottle-cap or less.

Abstract: When a two-division structure heat treatment jig for semiconductor substrate that includes a silicon first jig that comes into direct contact with a semiconductor substrate that is heat treated and supports the semiconductor substrate, and a second jig (holder) that holds the first jig and is mounted on a heat treatment boat is adopted as a heat treatment boat of a vertical heat treatment furnace, the stress concentrated during the heat treatment on a particular portion of the semiconductor substrate can be reduced; in the case of a semiconductor substrate large in the tare stress and having an outer shape of 300 mm being heat treated, or even in the case of the heat treatment being carried out under very high temperature conditions, the slips can be suppressed from occurring. The present invention can be widely applied as a stable heat treatment method of semiconductor substrates.

Abstract: An integrated circuit package-on-package stacking system is provided including, forming a leadframe interposer including: forming a leadframe; forming a molded base on the leadframe; and singulating the leadframe interposer from the leadframe.

Abstract: Provided is a semiconductor package accomplishing a fan-out structure through wire bonding in which a pad of a semiconductor chip is connected to a printed circuit board through wire bonding. A semiconductor package can be produced without a molding process and can be easily stacked on another semiconductor package while the appearance cracks and the warpage defects can be prevented.

Abstract: Multiple DIMM circuits or instantiations are presented in a single module. In some embodiments, memory integrated circuits (preferably CSPs) and accompanying AMBs, or accompanying memory registers, are arranged in two ranks in two fields on each side of a flexible circuit. The flexible circuit has expansion contacts disposed along one side. The flexible circuit is disposed about a supporting substrate or board to place one complete DIMM circuit or instantiation on each side of the constructed module. In alternative but also preferred embodiments, the ICs on the side of the flexible circuit closest to the substrate are disposed, at least partially, in what are, in a preferred embodiment, windows, pockets, or cutaway areas in the substrate. Other embodiments may only populate one side of the flexible circuit or may only remove enough substrate material to reduce but not eliminate the entire substrate contribution to overall profile.

Abstract: In an integrated circuit design, flex tape is used to provide signal ingress/egress to/from the integrated circuit design. Various architectures for the signal ingress/egress via flex tape is provided. In one embodiment, coaxial design is provided. In another embodiment, a coplanar waveguide design is provided.

Abstract: A method for manufacturing a semiconductor device is provided including: providing a reinforcing member on one surface of a wiring substrate that has a first region where a semiconductor chip is mounted and a second region around the first region, and has terminals extending from the first region to the second region formed on another surface thereof in a manner that the reinforcing member overlaps the terminals and a part thereof protrudes from the first region to the second region; cutting the terminals along a boundary between the first region and the second region; and continuously cutting the reinforcing member from an inboard side thereof to an outboard side along the boundary between the first region and the second region.

Abstract: Substrate for electrical devices and methods of manufacturing such substrate are disclosed. An embodiment for the substrate comprised of an insulator and a plurality of conductive elements, wherein the insulator having a recess. The conductive elements embedded in the insulator. The conductive elements extend from the insulator surface to the recess. There are two portions of the conductive elements for electrical connection respectively, wherein a portion of conductive element may protrude the insulator surface for electrical connection. In this manner, solder balls are not needed. Moreover, the substrate of the present invention may also comprise an adhesive mean, which is between the conductive elements and the insulator. In addition, the substrate may further comprise a submember such as a chip, heat spreader etc., and the present invention may be capable of affording a thinner electrical device thickness, enhanced reliability, and a decreased cost in production.

Abstract: In a liquid crystal driver package (1a) of one embodiment of the present invention, a film base member (2) is connected to a liquid crystal driver (3) through an interposer substrate (4a). Film base member connecting terminals (13) of the interposer substrate (4a) are connected to terminals of on-film wires (5 and 6) of the film base member (2) with an anisotropic conductive adhesive. An insulating film (7) is formed at an edge section of the interposer substrate (4a) and a periphery section of the edge section. This arrangement prevents the on-film wires (5 and 6) from coming into direct contact with the interposer substrate (4a). Therefore, it becomes possible to provide an IC chip (liquid crystal driver) package in which short circuit does not occur between the on-film wires adjacent to each other.

Abstract: A semiconductor device includes a semiconductor chip, an insulating base film and first projecting electrodes. The first projecting electrodes are formed in a single row on one face of the semiconductor chip along the edge of the semiconductor chip. This face of the semiconductor chip faces a semiconductor chip mounting face of the base film. The semiconductor device also includes second projecting electrodes formed in a single row outside the row of first projecting electrodes. The height of the second projecting electrodes is smaller than the first projecting electrodes. The semiconductor device also includes first inner leads formed on the semiconductor chip mounting face of the base film. The first inner lead extend to the first projecting electrodes. The semiconductor device also includes an insulating film formed between the first inner leads and the semiconductor chip. The semiconductor device also includes second inner leads formed on the insulating film.

Abstract: A printed-wiring board having a multiplayer structure including a plurality of insulating layers and a plurality of conducting layers includes a signal pattern provided in at least one of outermost layers of the conducting layers which includes a plurality of pad portions which are provided in positions opposite to a plurality of signal terminals of a connector component arranged in a predetermined form and perform electrical connection, reinforcing portions which are provided to extend from the pad portions respectively in a lengthwise direction, and land portions to perform the electrical connection to another layer of the conducting layers, and a solder resist provided on the outermost layer of the conducting layers to cover the reinforcing portion and having an opening portion to expose the pad portion.

Abstract: A surface mounted package for semiconductor die has a lead frame with a first and elongated die pad which receives three MOSgated die spaced along its length; second, third and fourth die pads laterally spaced from the first die pad and in a row parallel to the first die pad and receiving respective MOSgated die. A central wire bond receiving pad is disposed between the first pad and the spaced second, third and fourth pads. Wire bonds then connect the die into a three phase inverter circuit. Pin connectors extend through a plastic housing covering the top of the lead frame and are connectable, with the die pads, to the surface of a PCB.

Abstract: A tape carrier of the present invention includes an insulating tape and a wiring pattern formed on the insulating tape. The wiring pattern includes a connecting section via which the wiring pattern is connected to a bump electrode. The connecting section is provided at a part of an overlap part of the wiring pattern, which overlap part overlaps a semiconductor device when the semiconductor device is mounted on the wiring pattern. The connecting section of the wiring pattern is smaller in wiring width than the remaining part of the overlap part, which remaining part is other than the connecting section.

Abstract: A substrate (1) is formed from a non-electrically conducting material and is for mounting a semiconductor chip (10). The substrate has a semiconductor chip mounting portion (6). A number of first electrically conducting contact portions (5) are formed on the surface of the material and associated with the mounting portion (6). A second electrically conducting contact portion (3) is formed on the surface of the material, and the second electrically conducting contact portion (3) is adapted to be coupled to testing equipment. A number of electrically conducting paths (4) are formed on the surface of the material. The conducting paths (4) electrically connect the second electrically conducting contact portion (3) to a minority of the first electrically conducting contact portions (5).

Abstract: A chip-mounted film package includes a base film, an effective film package defined on the base film by a cutting line, a driving chip mounted on the effective film package, a plurality of input pads arranged on an input area of the effective film package and connected to the driving chip, and a plurality of output pads arranged on an output area of the effective film package and connected to the driving chip, wherein the output area includes at least one extended portion that protrudes from a side of the effective film package in a horizontal direction of the base film.

Abstract: A support structure for a semiconductor device with peripherally disposed contacts includes a support substrate and at least one conductive column protruding from the support substrate. The at least one conductive column is configured to contact an outer connector on a peripheral edge of a semiconductor device that may be carried by the support structure. Optionally, the at least one conductive column may engage a feature of (e.g., a recess in) the peripherally disposed outer connector. The at least one conductive column may facilitate alignment of one or more semiconductor devices with the support substrate alignment of semiconductor devices relative to one another, or electrical connection between multiple semiconductor devices of other components.

Abstract: A mounting structure of an electronic device capable of properly enhancing a bonding strength between an insulating substrate and the electronic device is provided. An electrode and an earth electrode having a surrounding shape are formed on an insulating substrate. In addition, a non-metal area exposing a surface of the insulating substrate is provided in the surrounding shape. An earth terminal is provided on a position opposed to the non-metal area on a back surface of an electronic device. The non-metal area and the earth terminal are bonded to each other by a solder adhesive including solder particles and a resin as major components. The solder particles are agglomerated on the earth terminal, then a solder layer is formed, and the earth terminal and the non-metal area are bonded to each other by the resin layer. Accordingly, a bonding strength between the electronic device and the insulating substrate are properly enhanced.

Abstract: An electronics assembly is provided including a circuit board substrate having a top surface and a bottom surface and a plurality of thermal conductive vias extending from the top surface to the bottom surface. At least one electronics package is mounted to the top surface of the substrate. A heat sink device is in thermal communication with the bottom surface of the substrate. Thermal conductive vias are in thermal communication to pass thermal energy from the at least one electronics package to the heat sink. At least some of the thermal conductive vias are formed extending from the top surface to the bottom surface of the substrate at an angle.

Abstract: A semiconductor chip package mounting structure may mount a semiconductor chip package on a module board by implementing a flexible circuit board. The semiconductor chip package may be electrically connected to a first surface of the flexible circuit board and the module board may be electrically connected to a second surface of the flexible circuit board.

Abstract: An insulating substrate includes a metal base as a base member, an insulating layer which is a room temperature, aerosol deposited shock solidification film formed on the metal base, and a circuit pattern which is a cold sprayed thermal spray coating formed on the insulating layer. A semiconductor device incorporates the insulating substrate, and thereby has improved heat radiation characteristics.

Abstract: A semiconductor device includes at least one semiconductor constructing body provided on one side of a base member, and having a semiconductor substrate and a plurality of external connecting electrodes provided on the semiconductor substrate. An insulating layer is provided on the one side of the base member around the semiconductor constructing body. An adhesion increasing film is formed between the insulating layer, and at least one of the semiconductor constructing body and the base member around the semiconductor constructing body, for preventing peeling between the insulating layer and the at least one of the semiconductor constructing body and base member.

Abstract: A liquid crystal display includes driver integrated circuits for applying a video signal to data lines, output pins and at least one dummy output pin are arranged within each data driver integrated circuit, and a switching pin is arranged within each data driver integrated circuit for controlling whether or not the dummy output pin outputs a signal.

Abstract: An integrated circuit package includes a substrate having a central axis dividing the substrate into an upper half and a lower half and an integrated circuit coupled to the substrate. A layer is provided within the substrate in the lower half thereof that is configured to resist warpage of the integrated circuit package, the layer provided a distance from the central axis.

Abstract: A semiconductor package includes a flip chip mounted on a plurality of leads and encapsulated by a molding compound. The upper surfaces of the leads includes a plurality of bump-bonding regions at the fan-in ends of the leads, and the lower surfaces of the leads include a plurality of outer connecting regions at the fan-out ends of the leads. A plurality of indentations are formed at the upper surfaces of the leads and adjacent to the corresponding bump-bonding regions so as to avoid solder contamination on the leads. After molding, the indentations are filled with the molding compound. Preferably, the indentations have a reversed “?”-shaped profile to prevent bumps of the flip chip from excessively wetting over the other portions of the leads to firmly fix the fan-in ends of the leads.

Abstract: The present invention relates to an IC substrate provided with over voltage protection functions and thus, a plurality of over voltage protection devices are provided on a single substrate to protect an IC chip directly. According to the present invention, there is no need to install protection devices at respective I/O ports on a printed circuit board to prevent the IC devices from damage by surge pulses. Therefore, the costs to design circuits are reduced, the limited space is efficiently utilized, and unit costs to install respective protection devices are lowered down.

Abstract: Integrated circuit device packages and substrates for making the packages are disclosed. One embodiment of a substrate includes a planar sheet of polyimide having a first surface, an opposite second surface, and apertures between the first and second surfaces. A planar metal die pad and planar metal are attached to the second surface of the polyimide sheet. The apertures in the polyimide sheet are juxtaposed to the leads. A package made using the substrate includes an integrated circuit device mounted above the first surface of the polyimide sheet opposite the die pad. Bond wires are connected between the integrated circuit device and the leads through the apertures in the polyimide sheet. An encapsulant material covers the first surface of the polyimide sheet, the integrated circuit device, the bone wires, and the apertures. The die pad and leads are exposed at an exterior surface of the package.

Abstract: A wiring board includes: a flexible insulating base 1; a plurality of conductive wirings 2 arranged on the flexible insulating base 1; protruding electrodes 3 provided respectively at an end portion of the same side of each of the conductive wirings; external terminals 4, 5 formed respectively at the other end portions of each of the conductive wirings; metal plating layers applied on the conductive wirings, the protruding electrodes and the external terminals; and solder resist layers 7 formed respectively by coating the conductive wirings in regions between the end portions at which the protruding electrodes are provided and the external terminals. In the regions where the solder resist layers are formed, no metal plating layers are formed on the conductive wirings, and the surfaces of the conductive wirings to be contacted with the flexible insulating base are rougher than the surfaces not to be contacted with the flexible insulating base.

Abstract: A method of forming a mold, concludes: winding a tape around peripheral surfaces of a first molding die and a second molding die to assemble a mold; forming on the tape an injection port for injecting a resin material for forming a plastic lens into the mold; and forming a tab by cutting out a part of the tape non-circularly.

Abstract: A double encapsulated semiconductor package and manufacturing methods of forming the same are provided. Embodiments of the semiconductor package include a complex chip having normal and random pads formed on its active surface, the complex chip being attached to a first surface of a wiring substrate. First and second windows are formed in the wiring substrate to respectively expose the normal and random pads, and to allow bonding wires to be connected to the normal and random pads with the wiring substrate. A first resin encapsulation portion is formed by a molding method in the first window and a second resin encapsulation portion is formed by a potting method in the second window.

Abstract: Under the present invention, a semiconductor chip is electrically connected to a substrate (e.g., organic, ceramic, etc.) by an interposer structure. The interposer structure comprises an elastomeric, compliant material that includes metallurgic through connections having a predetermined shape. In a typical embodiment, the metallurgical through connections electrically connect an under bump metallization of the semiconductor chip to a top surface metallization of the substrate. By utilizing the interposer structure in accordance with the present invention, the problems associated with previous semiconductor module designs are alleviated.

Abstract: A method of manufacturing a data carrier from a support strip includes an overmoulding step, in which at least one support element of the support strip is overmoulded so as to obtain a data carrier body, and a microcircuit-connecting step, in which a microcircuit is electrically connected to the wiring pads of the data carrier body so as to obtain the data carrier.

Abstract: A buffer layer is formed on a substrate and then electronic devices are packed on the buffer layer in the present invention, and problems of lower hermeticity and complex process in the conventional arts can be avoided. Therefore, the present invention provides a packaging structure and method with a better hermeticity and a simpler process. Especially, due to the buffer layer, the planarization for flip-chip bonding can be improved and reduce negative effects of the packing process.

Abstract: A semiconductor package is disclosed with a recess (51) for an integrated circuit die (52). The recess is made by bending or deforming all layers of a package substrate, and therefore the recess contains circuitry to connect to the integrated circuit die. The integrated circuit die is electrically connected to the package substrate by either wirebonds (53a), TAB or die solder balls (53b). The package substrate (50), a single sided printed wiring board, has a thick metal core (100) and one or more thin build up layers.