Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.

Abstract: Pad structures and methods for forming such pad structures are provided. For the pad structure, the first conductive material layer has a first hardness over about 200 kg/mm2. The second conductive material layer is over the first conductive material layer and has a second hardness over about 80 kg/mm2. For the method of forming the pad structure, a plurality of first conductive material layers is formed within each of a plurality of openings of a substrate. The substrate has a plurality of openings therein. The first conductive material layers are formed within each of the openings of the substrate. The first conductive material layers substantially have a round top surface. The second conductive material layers are formed and substantially conformal over the first conductive material layers. The second conductive material layers cover a major portion of the round top surface of the first conductive material layers.

Abstract: A module having a semiconductor chip with a first contact element on a first main surface and a second contact element on a second main surface is disclosed. The semiconductor chip is arranged on a carrier. An insulating layer and a wiring layer cover the second main surface and the carrier.

Abstract: An integrated circuit package-on-package stacking system includes a leadframe interposer including: a leadframe having a lead; a molded base on a portion of the lead for only supporting the lead; and the leadframe interposer singulated from the leadframe, wherein the lead is bent to support a stack-up height.

Abstract: A semiconductor package includes a semiconductor device having a first main surface and a second main surface, a first electrode plate provided on the first main surface, a second electrode plate provided on the second main surface, and a wiring substrate provided between the semiconductor device and the first electrode plate, in which a plurality of opening portions in the side surface of a protruding portion provided on the first electrode plate are engaged respectively with a plurality of engaging portions which face the opening portions and which are provided on the inner side surface of an intrusion opening portion in the wiring substrate into which the protruding portion is intruded.

Abstract: A semiconductor apparatus of the present invention includes: (i) a wire substrate having an insulating substrate in which a plurality of wire patterns are provided, (ii) a semiconductor element installed on the wire substrate with the insulating resin interposed therebetween, and a plurality of connecting terminals provided in the semiconductor element are electrically connected to connecting terminals of the wire patterns, respectively. In the semiconductor apparatus, the insulating substrate has mark patterns for alignment of the connecting terminals of the semiconductor element and the connecting terminals of the wire patterns, and an entire upper face of each of the mark patterns is covered with the insulating resin.

Abstract: An apparatus, method, and system for providing a stress absorption layer for integrated circuits includes a stiffening layer adapted to limit flexing. A compliance layer is physically associated with the stiffening layer, with the compliance layer adapted to absorb stress caused by mismatched thermal properties between two materials. A thru hole passes through both the stiffening layer and the compliance layer, with the thru hole being adapted to receive a solder joint. The stress absorption layer contacts both a semiconductor package and a substrate. The solder joint disposed in the thru hole connects the semiconductor package to the substrate.

Abstract: A method for structured application of a laminatable intermediate layer (9) to a substrate (1) for a semiconductor module, wherein a separating layer is indirectly or directly applied to the substrate (1) over a large surface, the intermediate layer (9) is applied to the substrate (1), including the separating layer(s), by lamination, over a large surface, the intermediate layer (9) is opened in places on the substrate (1), where recesses are provided for the intermediate layer (9), and the separating layer (8) is removed in these places.

Abstract: A display including a display panel, a circuit board and a tape carrier package structure is provided. The circuit board is disposed at the display panel. The tape carrier package structure includes a substrate having an opening, a plurality of leads, a chip, and a blocking bar. The substrate is between the display panel and the circuit board. A plurality of leads, each having an inner lead and outer lead, are disposed around the opening on the substrate. A portion of the outer leads is electrically connected to the display panel, and another portion is electrically connected to the circuit board. The chip has a plurality of contact points, and is disposed at the opening of the substrate. The contact points are electrically connected to the inner leads. Moreover, the blocking bar is disposed on the substrate between the chip and the display panel.

Abstract: A wiring board includes a substrate made of an insulation material and wired by a conductive material. A plurality of electrodes is formed on a surface of the substrate. A non-Au electrode not having an Au surface layer and an Au electrode having the Au surface layer are formed as the electrodes.

Abstract: A TCP-type semiconductor device has: a base film; a semiconductor chip mounted on the base film; and a plurality of leads formed on the base film. Each lead has: a first terminal portion including a first end that is one end of the each lead and connected to the semiconductor chip; and a second terminal portion including a second end that is the other end of the each lead and located on the opposite side of the first terminal portion. I a terminal region including the second terminal portion of the each lead, the plurality of leads are parallel to each other along a first direction, the plurality of leads include a first lead and a second lead that are adjacent to each other, and the first lead and the second lead are different in a position of the second end in the first direction.

Abstract: A multilayered wiring substrate is constructed by stacking wiring layers 105, 108, 110, 112 and insulating layers 104, 106, 107, 109 in predetermined number, with at least one of the wiring layers being formed as a reinforcing wiring layer 103 whose thickness is 35 to 150 ?m arranged in one layer or plural layers. Also, the thickness of the reinforcing wiring layer is larger than that of the other wiring layers.

Abstract: A driver module structure includes a flexible circuit board (2) provided with a wiring pattern (7), a semiconductor device mounted on the flexible circuit board (2), and an electrically conductive heat-radiating member (4) joined to the semiconductor device. The wiring pattern (7) includes a ground wiring pattern (8). The flexible circuit board (2) has a cavity (9) that exposes a portion of the ground wiring pattern (8). The exposed portion of the ground wiring pattern (8) and the heat-radiating member (4) are connected to establish electrical continuity via a member (11) that is fitted into the cavity (9).

Abstract: A land grid array module is provided that includes a land grid array interface. The interface includes a substrate having a mating face. A contact pad is provided on the mating face of the substrate. The contact pad has an exposed surface with a depression that is configured to restrain transverse movement of a mating contact tip when the mating contact tip is loaded against the contact pad. The substrate layer may include a via having a diameter such that the depression is formed in the contact pad when the contact pad is plated over the via. The depression may also be stamped in the exposed surface of the contact pad. Alternatively, the depression may be surrounded by a raised conductive perimeter that is configured to retain the mating contact tip.

Abstract: A tape carrier includes: a base film with insulating property; a wiring pattern provided on the base film within a product region, the product region being demarcated by a cutting line so as to divide the tape carrier into individual products by cutting along the tape carrier along the cut line; and a solder resist provided on the base film so as to cover the wiring pattern. The solder resist protrudes outward from within the product region.

Abstract: An insulative substrate includes a plurality of flexible retaining clips and a plurality of alignment and retaining pins. A metal leadframe includes a plurality of leads. Each lead terminates in a spring contact beam portion. The leadframe is attached to the substrate (for example, by fitting a hole in each lead over a corresponding alignment and retaining pin and then thermally deforming the pin to hold the lead in place). An integrated circuit is press-fit down through the retaining clips such that pads on the face side of the integrated circuit contact and compress the spring contact beams of the leads. After the press-fit step, the retaining clips hold the integrated circuit in place. The resulting assembly is encapsulated. In a cutting and bending step, the leads are singulated and formed to have a desired shape. The resulting low-cost package involves no wire-bonding and no flip-chip bond bump forming steps.

Abstract: A Chip on Board (COB) package which can reduce the manufacturing costs by using a general PCB as a substrate, increase a heat radiation effect from a light source, thereby realizing a high quality light source at low costs, and a manufacturing method thereof. The COB package includes a board-like substrate with a circuit printed on a surface thereof, the substrate having a through hole. The package also includes a light source positioned in the through hole and including a submount and a dome structure made of resin, covering and fixing the light source to the substrate. The invention allows a good heat radiation effect by using the general PCB as the substrate, enabling manufacture of a high quality COB package at low costs. This in turn improves emission efficiency of the light source, ultimately realizing a high quality light source.

Abstract: An electronic apparatus includes metal wiring plates placed together in the same plane to provide a wiring circuit, electronic devices mounted to the wiring plates through a solder, a case having a base portion and columnar portions extending from the base portion. The wiring plates are fixed to the columnar portions such that the wiring circuit is spaced from the base portion. The wiring plates have an enough thickness to resist a large current for operating the electronic devices and to release heat generated by the electronic devices. The wiring circuit is spaced from the base portion of the case so that the heat generated by the electronic devices is released in the space efficiently. The electronic devices are soldered to the wiring plates at once in a thermal reflow process.

Abstract: A semiconductor package without a chip carrier includes an insulating structure having an opening; an electroplated die pad provided in the opening; a chip attached to the electroplated die pad by a thermally conductive adhesive; a plurality of electrical contacts formed around the electroplated die pad, wherein at least one of the electrical contacts is provided on a top surface of the insulating structure, and the chip is electrically connected to the electrical contacts; and an encapsulant for encapsulating the chip, the insulating structure and the electrical contacts, wherein bottom surfaces of the insulating structure, the electroplated die pad and the electrical contacts, except the at least one electrical contact provided on the top surface of the insulating structure, are exposed from the encapsulant and are flush with a bottom surface of the encapsulant. A fabrication method of the semiconductor package is also provided.

Abstract: A tape carrier of the present invention includes an insulating tape and a wiring pattern formed on the insulating tape. The wiring pattern includes a connecting section via which the wiring pattern is connected to a bump electrode. The connecting section is provided at a part of an overlap part of the wiring pattern, which overlap part overlaps a semiconductor device when the semiconductor device is mounted on the wiring pattern. The connecting section of the wiring pattern is smaller in wiring width than the remaining part of the overlap part, which remaining part is other than the connecting section.

Abstract: A semiconductor device in which chips are resin-molded, including: frames having front and back surfaces and die pads; power chips mounted on the surfaces of the die pads; an insulation resin sheet having a first and a second surfaces which are opposed against each other, the resin sheet being disposed such that the back surfaces of the die pads contact the first surface of the resin sheet; and a mold resin applied on the first surface of the resin sheet so as to seal up the power chips. The thermal conductivity of the resin sheet is larger than that of the mold resin.

Abstract: A semiconductor device which includes a radiating plate, a wiring patterned layer on the radiating plate via an insulating layer, at least one semiconductor chip mounted on the wiring patterned layer. The semiconductor chip has a surface electrode. The semiconductor device further includes a conductive lead plate electrically connected with the surface electrode of the semiconductor chip, and a resin package of thermoplastic resin having anisotropic linear expansion coefficient varying based upon directions. The resin package covers the wiring patterned layer, the semiconductor chip, the conductive lead plate, and at least a portion of the radiating plate. The conductive lead plate extends in a direction which provides the resin package with the maximum linear expansion coefficient. In the semiconductor device so structured, the warpage of the resin package is reduced both in longitudinal and transverse directions.

Abstract: A leadframe-based semiconductor package is revealed, primarily comprising a chip, a plurality of leads of a leadframe, a multi-layer tape, and an encapsulant. The multi-layer tape is attached to the chip and includes an adhesive layer disposed on a dielectric core layer. The internal leads of the leads are partially embedded in the adhesive layer in a manner not to directly contact the dielectric core layer. A bonding interface with a U-shaped profile is formed between the adhesive layer and each internal lead to increase the adhesions of the leads so that the internal leads will not be shifted nor delaminated during molding processes. The concentrated stresses exerted on the internal leads disposed at the corners of the packages will be released and reduced.

Abstract: A semiconductor device according to the present invention includes a base tape (film carrier tape); a semiconductor chip mounted on the base tape; conducting leads formed on the base tape to be connected to the semiconductor chip; input terminals and output terminals connected to the conducting leads; and a protecting layer formed to cover the conducting leads completely. The base tape is provided at its side edges with roller-contact regions, where carrier rollers are to be in contact with. No holes and no unevenness area is formed on the roller-contact regions.

Abstract: A coupling substrate for semiconductor components includes a patterned metal layer on a topside of an insulating carrier. Metal tracks project beyond the insulating carrier, the metal tracks being angled away at the lateral edges of the carrier in the direction of the underside of the carrier and projecting beyond the underside of the carrier. The metal tracks have a metal coating, thereby enlarging each cross section such that the metal tracks form dimensionally stable, flat, conductor external contacts of the coupling substrate.

Abstract: Provided are an inlet for an electronic tag comprising an insulating film, antennas each made of a conductor layer and formed over one surface of the insulating film, a slit formed in a portion of each of the antennas and having one end extending toward the outer edge of the antenna, a semiconductor chip electrically connected with each of the antennas via a plurality of bump electrodes, and a resin for sealing the semiconductor chip therewith; and a manufacturing process of the inlet. By the present invention, formation of a thin and highly-reliable inlet for a non-contact type electronic tag can be actualized.

Abstract: A semiconductor device including: a semiconductor substrate in which an integrated circuit is formed; an insulating layer formed on the semiconductor substrate and having a first surface and a second surface which is higher than the first surface; a first electrode formed to avoid the second surface and electrically connected to the inside of the semiconductor substrate; and a second electrode formed on the second surface and electrically connected to the inside of the semiconductor substrate.

Abstract: A manufacturing process of a leadframe-based BGA package is disclosed. A leadless leadframe with an upper layer and a lower layer is provided for the package. The upper layer includes a plurality of ball pads, and the lower layer includes a plurality of sacrificial pads aligning and connecting with the ball pads. A plurality of leads are formed in either the upper layer or the lower layer to interconnect the ball pads or the sacrificial pads. An encapsulant is formed to embed the ball pads after chip attachment and electrical connections. During manufacturing process, a half-etching process is performed after encapsulation to remove the sacrificial pads to make the ball pads electrically isolated and exposed from the encapsulant for solder ball placement where the soldering areas of the ball pads are defined without the need of solder mask(s) to solve the problem of solder bleeding of the solder balls on the leads or the undesired spots during reflow. Moreover, mold flash can easily be detected and removed.

Abstract: Substrates having integrated rigid and flexible regions and methods of fabricating such substrates are disclosed. The substrates may advantageously be used for mounting semiconductor chips used in flexible microelectronic assemblies.

Abstract: An electronic component such as a semiconductor device is provided which is capable of preventing wiring breakage in a stress concentration region of surface layer wiring lines. In a semiconductor device provided with a support ball (5), no ordinary wiring line is formed in a region (7(A)) in the vicinity of the support ball (5) and a region (7(B)) at the end of the semiconductor chip facing the support ball (5), which are the stress concentration regions of the package substrate (2). Instead, a wiring line (6(C)) is formed away from these regions or a wide wiring line is formed in these regions.

Abstract: Provided is a semiconductor package in which an adhesion force between an insulation metal substrate and a molding member is increased by removing a solder mask layer from the insulation metal substrate and a method of fabricating the semiconductor package. The semiconductor package includes an insulation metal substrate that includes a base member, an insulating layer disposed on the base member, and conductive patterns formed on the insulating layer. Semiconductor chips are arranged on the conductive patterns. Solder mask patterns are arranged on the conductive patterns to surround the semiconductor chips. Leads are electrically connected to the conductive patterns through wires. A sealing member is arranged on an upper surface and side surfaces of the substrate to cover portions of the leads, the wires, the semiconductor chips, and the solder mask patterns.

Abstract: A semiconductor device 1 is a semiconductor device of the BGA type, and includes a semiconductor chip 10, a resin layer 20, an insulating layer 30, and an external electrode pad 40. The resin layer 20 is constituted by a sealing resin 22 and an underfill resin 24, and covers the semiconductor chip 10. The insulating layer 30 is formed on the resin layer 20. The external electrode pad 40 is formed in the insulating layer 30. This external electrode pad 40 extends through the insulating layer 30. One surface S1 of the external electrode pad 40 is exposed in the surface of the insulating layer 30, and the other surface S2 is located in the resin layer 20. A concave portion 45 is formed in the surface S2 of the external electrode pad 40. The resin composing the resin layer 20 enters into the concave portion 45.

Abstract: A chip-scale or wafer-level-package, having passivation layers on substantially all surfaces thereof to form a hermetically sealed-package, is provided. The package may be formed by disposing a first passivation layer on the passive or backside surface of a semiconductor wafer. The semiconductor wafer may be attached to a flexible membrane and diced, such as by a wafer saw, to separate the semiconductor devices. Once diced, the flexible membrane may be stretched so as to laterally displace the individual semiconductor devices away from one another and substantially expose the side edges thereof. Once the side edges of the semiconductor devices are exposed, a passivation layer may be formed on the side edges and active surfaces of the devices. A portion of the passivation layer over the active surface of each semiconductor device may be removed so as to expose conductive elements formed therebeneath.

Abstract: To provide a tape carrier capable of suppressing the formation of wrinkles at a non-continuous portion of strength of the tape carrier and avoid the signal line breakage associated with bending operation. A driver IC is mounted on an insulation film tape, input terminal is arranged at one end and an output terminal is arranged at the other end of the insulation film tape, input signal lines and output signal lines are individually mounted between the driver IC and each terminal, and a resin applying region is arranged at a mounting portion of the driver IC. An independent dummy pattern without connecting destination to be electrically connected to is arranged near each end on the side not facing each terminal of the driver IC on the insulation film tape, and the respective end on the driver IC side of each dummy pattern is extended into the resin applying region.

Abstract: Output pads on an integrated circuit (IC) chip are arranged along a first longer side and are arranged along a second longer side with input pads. The output pads are connected to respective output patterns formed on top and bottom surfaces of a base film. All the output patterns may pass over the first longer side. Alternatively, the output patterns connected to the output pads at the second longer side may pass over a shorter side. These pattern structures establish an effective pad arrangement without increasing the size of a TAB package, yet allowing reduced the chip size.

Abstract: A device is provided in which a glass panel having beveled edge is flexibly connected to a TAB package. The outer lead portions of the TAB package include an end portion of first width connected to a connection pattern on the glass panel, a terminal portion having a second width greater than the first width, and a transition portion having a width that varies between the first and second widths. When the TAB package is connected the transition portion of the respective outer lead portions are disposed over the beveled edge of the glass panel.

Abstract: A semiconductor device with an inductor device is small, thin, and low-cost. A laminated inductor is adhered fixedly onto a supporting conductive plate by Ag paste, and a semiconductor chip is adhered fixedly onto the laminated inductor via an insulating DAF tape. One end of the supporting conductive plate and a terminal electrode of the semiconductor chip are connected by a metal wire, and a plurality of terminal electrodes of the semiconductor chip and a plurality of external lead-out terminals are connected respectively by laterally extending metal wires. The entire structure is then sealed by a resin mold. By employing a laminated inductor and forming the metal wires to extend laterally in this manner, the thickness of the semiconductor device with an inductor can be reduced.

Abstract: An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as it modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established be considering the reflective density in opposing conductive build-up layers above and below the core region.

Abstract: A power module includes a power semiconductor, a non-power semiconductor, one resin substrate, and a cooling device. The power semiconductor and the non-power semiconductor configure a power supply circuit for performing power conversion. Both the power semiconductor and the non-power semiconductor are mounted on the resin substrate. The cooling device is disposed in order to cool the power semiconductor.

Abstract: A universal substrate includes a plurality of inner pads and a plurality of outer pads. A plurality of bifurcate wirings and a plurality of fuses are formed on a surface of the substrate. The fuses are connected with the bifurcate wirings in series. By the bifurcate wirings and the fuses, each of the inner pads is electrically connected to all of the outer pads to provide optional electrical disconnections therebetween. Accordingly, the universal substrate can provide for various chips with different serial arrangements of bonding pads without replacing or manufacturing another kind of substrate.

Abstract: A primary side circuit and a secondary side circuit are provided on first and second semiconductor substrates, respectively. A first capacitive insulator on the first substrate electrically insulates and isolates between the primary and secondary side circuits while permitting signal transmission between these circuits. A second capacitive insulator on the second semiconductor substrate electrically isolates the primary and secondary side circuit while permitting signal transmission therebetween. First and second frames are provided for input and output of signals to and from the primary and secondary side circuits. External electrodes of the first and second capacitive insulators are connected together by a third lead frame via a conductive adhesive body including more than one solder ball. The first and second substrates and the lead frames are sealed by a dielectric resin.

Abstract: There is provided a mounting substrate on which a semiconductor chip is mounted using a flip chip bonding, having a plurality of connection pads which are connected to the semiconductor chip, and an insulation layer formed in such a manner as to cover the connection pads partially, wherein the insulation layer includes a first insulation layer which is formed in such a manner as to correspond to a center of the semiconductor chip and a second insulation layer which is formed in such a manner as to surround the first insulation layer, and wherein the plurality of connection pads include first connection pads which are partially covered by the first insulation layer and second connection pads which are partially covered by the second insulation layer.

Abstract: A method for manufacturing a semiconductor device is provided including: providing a reinforcing member on one surface of a wiring substrate that has a first region where a semiconductor chip is mounted and a second region around the first region, and has terminals extending from the first region to the second region formed on another surface thereof, in a manner that the reinforcing member overlaps the terminals and a part thereof protrudes from the first region to the second region; punching through from a surface side having the terminals in the wiring substrate, thereby cutting the terminals along a boundary between the first region and the second region; and punching through from the surface side having the reinforcing member in the wiring substrate, thereby continuously cutting the reinforcing member from an inboard side thereof to an outboard side along the boundary between the first region and the second region.

Abstract: A driver module structure includes a flexible circuit board (2) provided with a wiring pattern (7), a semiconductor device mounted on the flexible circuit board (2), and an electrically conductive heat-radiating member (4) joined to the semiconductor device. The wiring pattern (7) includes a ground wiring pattern (8). The flexible circuit board (2) has a cavity (9) that exposes a portion of the ground wiring pattern (8). The exposed portion of the ground wiring pattern (8) and the heat-radiating member (4) are connected to establish electrical continuity via a member (11) that is fitted into the cavity (9).

Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

Abstract: A semiconductor device includes a semiconductor chip, an insulating base film and first projecting electrodes. The first projecting electrodes are formed in a single row on one face of the semiconductor chip along the edge of the semiconductor chip. This face of the semiconductor chip faces a semiconductor chip mounting face of the base film. The semiconductor device also includes second projecting electrodes formed in a single row outside the row of first projecting electrodes. The height of the second projecting electrodes is smaller than the first projecting electrodes. The semiconductor device also includes first inner leads formed on the semiconductor chip mounting face of the base film. The first inner lead extend to the first projecting electrodes. The semiconductor device also includes an insulating film formed between the first inner leads and the semiconductor chip. The semiconductor device also includes second inner leads formed on the insulating film.

Abstract: An integrated circuit device structure and a process for fabricating the structure wherein the power bus interconnect structure is formed in the aluminum pad or contact layer. An interconnect structure for interconnecting underlying levels of interconnect can also be formed in the aluminum pad layer.

Abstract: An integrated circuit package-on-package stacking method includes forming a leadframe interposer including: forming a leadframe having a lead; forming a molded base only supporting the lead; and singulating the leadframe interposer from the leadframe.

Abstract: In some embodiments, flexible joint methodology to attach a die on an organic substrate is presented. In this regard, an integrated circuit chip package substrate is introduced having an organic substrate, an interposer coupled with a surface of the organic substrate, the interposer having cavities to accept bumps of a die, and a flexible tape layer coupled with a surface of the interposer, the flexible tape layer to couple with bumps of the die. Other embodiments are also disclosed and claimed.

Abstract: Provided is a semiconductor package accomplishing a fan-out structure through wire bonding in which a pad of a semiconductor chip is connected to a printed circuit board through wire bonding. A semiconductor package can be produced without a molding process and can be easily stacked on another semiconductor package while the appearance cracks and the warpage defects can be prevented.