Abstract: A semiconductor device includes a wiring board having a wiring pattern, a semiconductor chip that has an integrated circuit and is mounted on a first surface of the wiring board to electrically connect with the wiring pattern, a spacer that is disposed on a second surface of the wiring board and has inside thereof an electronic component that is electrically connected with the wiring pattern and an external terminal that is disposed on the second surface and electrically connected with the wiring pattern.

Abstract: An assembly of microelectronic devices and method for forming an assembly of microelectronic devices. In one embodiment, the method includes positioning a first packaged microelectronic device adjacent to a support member having support member circuitry, with the first packaged microelectronic device having a first microelectronic die at least partially encased in a first encapsulant to define a first package configuration. The method can further include electrically connecting the first packaged microelectronic device to a first portion of the support member circuitry and positioning at least proximate to the first packaged microelectronic device a second packaged microelectronic device having a second microelectronic die at least partially encased in a second encapsulant to define a second package configuration different than the first package configuration. The first packaged microelectronic device can be positioned between the support member and the second packaged microelectronic device.

Abstract: A semiconductor device including: a semiconductor substrate in which an integrated circuit is formed; an insulating layer formed on the semiconductor substrate and having a first surface and a second surface which is higher than the first surface; a first electrode formed to avoid the second surface and electrically connected to the inside of the semiconductor substrate; and a second electrode formed on the second surface and electrically connected to the inside of the semiconductor substrate.

Abstract: A semiconductor device formed by an automated wire bonding system. The semiconductor device comprises a lead frame having a plurality of lead fingers and a die paddle, and a semiconductor die mounted to the die paddle. The die paddle comprises a plurality of eyepoint features that extend from the die. The die comprises a first plurality of bonding pads and the lead fingers comprise a second plurality of bonding pads. The first and second bonding pads are interconnected by a plurality of connecting wires which are installed by the automated wire bonding system. The wire bonding system obtains an image of the lead frame and identifies the eyepoint features of the die paddle within the image so as to more accurately determine the positions of the second wire bonding pads of the lead frame with respect to the wire bonding system.

Abstract: A bump-less chip package is provided. The bump-less chip package includes a chip, an interconnection structure and a panel-shaped component. The panel-shaped component has a plurality of electrical terminals on a first surface thereof. The back surface of the chip is disposed on the first surface of the panel-shaped component, and the chip has a plurality of first pads on the active surface thereof away from the panel-shaped component. The interconnection structure is disposed on the first surface of the panel-shaped component and the active surface of the chip. The first pads of the chip may electrically connect with the electrical terminals of the panel-shaped component through the interconnection structure. Furthermore, the interconnection structure has a plurality of second pads on the surface away from the chip.

Abstract: A multilayer wiring board (X1) comprises a core portion (100) and out-core wiring portion (30). The core portion (100) comprises a carbon fiber reinforced portion (10) composed of a carbon fiber material (11) and resin composition (12), and an in-core wiring portion (20) which has a laminated structure of at least one insulating layer (21) containing a glass fiber material (21a) and a wiring pattern (22) composed of a conductor having an elastic modulus of 10 to 40 GPa and which is bonded to the carbon fiber reinforced portion (10). The out-core wiring portion (30) has a laminated structure of at least one insulating layer (31) and a wiring pattern (32) and is bonded to the core portion (100) at the in-core wiring portion (20).

Abstract: A semiconductor chip mounting substrate having a semiconductor bare chip and a substrate electrically connected to the semiconductor bare chip by wire bonding is provided. Here, a protective film is provided on the surface of the semiconductor bare chip and is disposed so as to expose all or a part of a bonding wire.

Abstract: A tape package in which a test pad is formed on a reverse surface is provided. The test pad is disposed on a reverse surface of a base film through a through hole of the base film. Accordingly, shapes of the test pads are standardized so that a universal probe card can be used. A pitch between the test pads is wide so that the accuracy in an electric test of the tape package is increased. A total length of the tape package is reduced.

Abstract: A device for and method of packaging electronic components (1) using injection-molding. For this purpose, a multiplicity of components (1) are arranged in predetermined positions on a first side (2) of a leadframe (3). The leadframe (3) has interconnects (5) with contact terminal areas (6) for connecting to contact areas (7) of the electronic components (1) and contact vias (8) to external contacts on a second side (10) of the leadframe (3). In this case, the leadframe (3) includes a ceramic substrate (11) with a first side (2) having edge regions (12) configured with a ductile, annular metal layer (13).

Abstract: A semiconductor device has an, improved mounting reliability and has external terminals formed by exposing portions of leads from a back surface of a resin sealing member. End portions on one side of the leads are fixed to a back surface of a semiconductor chip, and portions of the leads positioned outside the semiconductor chip are connected with electrodes formed on the semiconductor chip through wires.

Abstract: An electronic circuit device comprises: a semiconductor element having a first surface and a second surface, with the first and second surfaces being on first and second sides of the semiconductor element, respectively, and facing in opposite directions; a first electrode on the first surface; a second electrode on the second surface; a first circuit board electrically connected to the first electrode via a metallic plate such that the metallic plate and the semiconductor element are on the first circuit board; a second circuit board on the second side of the semiconductor element, the second circuit board having a control circuit for the semiconductor element; and a metallic wire for directly electrically interconnecting the second electrode and the second circuit board.

Abstract: A semiconductor package and a method for fabricating the same are proposed. A substrate having a first circuit layer, a second circuit layer, and a core layer formed between the first and second circuit layers is provided. At least one second opening is formed on the second circuit layer. At least one first opening is formed on the first circuit layer corresponding to the second opening. A plurality of finger holes corresponding to bond fingers on the first circuit layer are formed in the core layer. A through opening is formed in the core layer and communicates with the first and second openings. At least one chip is mounted on the first circuit layer and covers the first opening, with its active surface being exposed to the first opening. An encapsulant is formed to fill the first and second openings and the through opening and encapsulate the chip.

Abstract: In a composite device of the laminate type having a laminate structure of a composite ceramic layer and a dielectric ceramic layer, the composite ceramic layer including a layer portion having the same composition as the dielectric ceramic layer and a plurality of particle portions formed on the surface of the layer portion. The particle portions are made from magnetic ceramic material. This prevents the ceramic layers of the device from cracking and separating when fired.

Abstract: A multi-layer printed circuit board (PCB) includes a first wire layer, a middle layer above the first wire layer, a second wire layer above the middle layer, and a slanting via formed in the middle layer and the second wire layer. The manufacturing method includes the steps of providing a first wire layer and forming a first wiring on the first wire layer, forming a middle layer on the first wire layer, forming a second wire layer on the middle layer, forming a slanting via in the middle layer and the second wire layer wherein the direction of the slanting via is not orthogonal to the first and the second wire layers, forming a second wiring on the second wire layer by an etching method, and forming an electroplated layer in the via to connect the first wiring and the second wiring.

Abstract: The present invention provides a light emitting module, comprising: a plurality of thin plate-shaped conductors (2) spaced apart from each other in a first direction; at least one light source (4) connected between at least one pair of adjoining ones of said conductors; and at least one insulating joint member (4) for mechanically joining said plurality of conductors, wherein said at least one insulating joint member exposes both sides of at least a portion of said conductors where said light source is mounted.

Abstract: An integrated circuit is formed on a non-planar substrate. The integrated circuit is formed over a plurality of layers. Chemical or physical changes in the microstructure of the substrate cause the bending of the substrate, in one or more propagation directions.

Abstract: Provided is a semiconductor device which prevents displacement of a semiconductor element and a wiring pattern of a wiring substrate so as to ensure the connection of the semiconductor element and the wiring pattern. The semiconductor device of the present invention includes a semiconductor element and a wiring substrate which is provided with a film substrate and a wiring pattern which is formed on the film substrate, the semiconductor element is connected to the wiring pattern, and the semiconductor element and the wiring substrate are sealed with a resin. A metallic film, made of material having a smaller coefficient of linear thermal expansion than the film substrate, is formed in a region where the wiring pattern is not formed on at least one surface of the film substrate.

Abstract: A tape automated bonding (TAB) structure which includes a flex tape having a conductive lead pattern formed thereon. The conductive lead pattern includes a plurality of leads configured to form an inner lead bond (ILB) portion of the TAB structure. At least one of the plurality of leads is internally routed and has a contact exposed interior to the ILB portion of the TAB structure.

Abstract: In a method for manufacturing a semiconductor device by processing of a wafer level, in the case of forming the semiconductor device at the wafer level, on the basis of inspection results on individual semiconductor chips constituting a semiconductor wafer, a treatment for forming a circuit including a rewiring pattern is performed with respect to a semiconductor chip judged as a conforming product and a treatment in which a rewiring pattern is not formed in order to avoid having adverse influence on a semiconductor device of a conforming product or an inspection apparatus in an inspection of a formed semiconductor device after forming the semiconductor device is performed with respect to a semiconductor chip judged as a nonconforming product.

Abstract: A tape circuit substrate comprises a base film made of an insulating material, and a wiring pattern layer which is formed on the base film and has first leads that are connected to electrode pads arranged near a periphery of a semiconductor chip and second leads that are connected to electrode pads arranged near the center of the semiconductor chip. The semiconductor chip package comprises a semiconductor chip electrically bonded to the tape circuit substrate through chip bumps. In such a case, each of the leads is configured such that a tip end thereof to be bonded to the electrode pad has a width larger than that of a body portion thereof. According to the present invention, since the interval between the lead and the electrode pad can be made even narrower, a fine pitch semiconductor device can be realized.

Abstract: Provided is a method of producing a semiconductor package including at least two rows of leads in which the leads of each row separately connecting a semiconductor chip to an external substrate. The method includes: forming a lead frame, the lead frame including a die pad and a plurality of leads arranged about the die pad; attaching an adhesive tape to a surface of the lead frame covering at least substantially the die pad and the plurality of leads; removing portions of the leads and the adhesive tape disposed in a dividing region and thereby separating at least some of the plurality of leads to form multiple rows of leads; and mounting a semiconductor chip on the die pad, electrically connecting the semiconductor chip with the lead frame, and molding the lead frame and the semiconductor chip to provide a semiconductor package. The adhesive tape attached at undesirable locations of the lead frame is preferably removed after provision of the semiconductor package.

Abstract: The present invention provides a COF flexible printed wiring board whose insulating layer is not melt-adhered to a heating tool, to thereby enhance reliability and productivity of a semiconductor chip mounting line, and also provides a method of producing the COF flexible printed wiring board. The COF flexible printed wiring board contains an insulating layer, a wiring pattern, on which a semiconductor chip being mounted, formed of a conductor layer provided on at least one side of the insulating layer and a releasing layer, wherein the releasing layer is formed from a releasing agent containing at least one species selected from a silane compound and silica sol and is provided on a surface of the insulating layer, which is opposite to the mounting side of the semiconductor chip.

Abstract: A method of fabricating a chip-scale or wafer-level package having passivation layers on substantially all surfaces thereof to form a hermetically sealed package. The package may be formed by disposing a first passivation layer on the passive or backside surface of a semiconductor wafer. The semiconductor wafer may be attached to a flexible membrane and diced, such as by a wafer saw, to separate the semiconductor devices. Once diced, the flexible membrane may be stretched so as to laterally displace the individual semiconductor devices away from one another and substantially expose the side edges thereof. Once the side edges of the semiconductor devices are exposed, a passivation layer may be formed on the side edges and active surfaces of the devices. A portion of the passivation layer over the active surface of each semiconductor device may be removed so as to expose conductive elements formed therebeneath.

Abstract: A method and apparatus for making reliable miniature semiconductor packages having a reduced height and footprint is provided. The package includes a semiconductor chip having an active surface and a non-active surface and one or more contacts positioned adjacent the semiconductor chip. Electrical connections are formed between the contacts and the semiconductor chip. An adhesive tape provided adjacent the non-active surface of the semiconductor chip and the one or more contacts positioned adjacent the semiconductor chip. An adhesive material provided between the non-active surface of the chip and the adhesive tape.

Abstract: A lead frame comprises a lead frame body having cut-away portions cut away from the side surfaces of the lead frame body, a die pad for securing a semiconductor chip, bonding electrodes surrounding the die pad, external electrodes for allowing the lead frame to be mounted, wiring for surface treatment extending on the lead frame body with its end being located at a portion of each of the side surfaces of the lead frame body, the portion being opposed to the cut-away portions. The bonding electrode and the wiring for surface treatment, as well as the external electrode and the wiring for surface treatment, are electrically connected, respectively. Even when the lead frame is electrostatically charged by friction with a transfer unit, the semiconductor chip on the lead frame avoids electrostatic damage.

Abstract: An area array type semiconductor package includes a plurality of conductive media such as solder bumps or solder balls, attached to respective bond pads of a chip. The conductive media act as external output terminals. The chip is attached to a lead frame by a thermal conductive adhesive, and a predetermined area of the lead frame and the semiconductor chip are packaged with a molding resin. Leads of the lead frame are then trimmed and formed so that the lead frame, to which the semiconductor chip is adhered, acts as a heat sink. This allows the package to be used for a high-powered semiconductor device which radiates a high temperature heat. Also, because conductive media such as solder bumps or solder balls can be used to directly connect bond pads of the chip to conductive regions of a circuit board, a size of the semiconductor package can be minimized, the arrangement of the bonding pads on the chip can be easily planned, and electrical characteristics of the semiconductor package can be improved.

Abstract: A semiconductor chip is mounted on the substrate so that the first group of electrodes faces the first group of leads and the second group of electrodes faces the second group of leads. The first group of leads extends in a direction away from the second group of electrodes. Each of the second group of leads extends so as to pass between the first group of electrodes and is formed to be bent in the region between first and second straight lines.

Abstract: When bonding inner leads of a flexible film wiring board to electrode pads of a semiconductor element substrate, by absorbing a stress generated due to a difference in thermal expansion coefficient between the flexible film wiring board and the semiconductor element substrate during cooling after heat-bonding, by a through-hole or recessed groove portion formed in the inner leads, it is possible to prevent peeling off of a bonding portion and improve the reliability.

Abstract: An electro-optical device includes: a first substrate having an end edge; a second substrate that has an edge crossing the end edge and a plurality of first wiring lines crossing the end edge, the second substrate having flexibility and being connected to the first substrate so as to overlap the end edge; and first reinforcing members provided on the second substrate so as to cross the end edge, in a region between the plurality of first wiring lines and a portion where the end edge and the edge cross each other.

Abstract: A semiconductor device is provided, the semiconductor device including a semiconductor chip having a first metal heat-conductive medium in the inside thereof, a substrate having a second metal heat-conductive medium thermally connected to the first metal heat-conductive medium, and a temperature control device of which at least a part is disposed on the substrate, thermally connected to the second metal heat-conductive medium, and configured to control the temperature within the semiconductor chip.

Abstract: To provide a semiconductor device capable of corresponding to an applied bending stress by flexibly changing its shape, and to provide a semiconductor device module, a manufacturing method of the semiconductor device, and a manufacturing method of the semiconductor device module. In a silicon substrate whose front surface is provided with an element forming layer having an element forming region where a semiconductor element is formed, a groove is formed in a portion of the rear surface of the silicon substrate corresponding to a region of the element forming layer where a semiconductor element is not formed.

Abstract: Provided are an inlet for an electronic tag comprising an insulating film, antennas each made of a conductor layer and formed over one surface of the insulating film, a slit formed in a portion of each of the antennas and having one end extending toward the outer edge of the antenna, a semiconductor chip electrically connected with each of the antennas via a plurality of bump electrodes, and a resin for sealing the semiconductor chip therewith; and a manufacturing process of the inlet. By the present invention, formation of a thin and highly-reliable inlet for a non-contact type electronic tag can be actualized.

Abstract: A chip carrier for manufacturing a chip module (18), with a substrate and connection leads arranged on the substrate has connection leads designed like stripes and extending parallel over the substrate. The connection leads are electrically conductive connection strands (12, 13) placed on the substrate. The substrate is formed by a carrier film (11).

Abstract: A board-on-chip (BOC) semiconductor package includes a multisegmented, longitudinally slotted interposer substrate through which an elongate row of die bond pads is accessed for electrical attachment, as by wire bonding, to conductive traces on the opposite side of the interposer substrate. One or more reinforcements in the form of crosspieces or bridges span and segment intermediate portions of the substrate slot to resist bending stresses acting in the slot region proximate the centerline of the interposer substrate tending to crack or delaminate a polymer wire bond mold cap filling and covering the slot and the wire bonds. Various interposer substrate configurations are also disclosed, as are methods of fabrication.

Abstract: An embedded redistribution interposer is disclosed for providing footprint compatible chip package migration in which a die designed to be mounted into chip package is originally implemented using a first type of silicon platform and is subsequently redesigned for a second type of silicon platform, resulting in a redesigned die being a different size than the original die and no longer compatible for mounting in the chip package. According to the present invention, the embedded redistribution interposer includes a substrate having a plurality of bond pads on a top side thereof, wherein the redesigned die is mounted to the top of the interposer substrate, and the bottom of the interposer substrate is mounted to the substrate of the chip package. The redesigned die is connected to the redistribution interposer via a first set of electrical connections coupled between the die and the interposer bond pads.

Abstract: A supporting frame is used to solidly bridge to the two metallic contacts of a surface mount diode chip. Any bending or twisting stress between the two contacts is borne by the supporting frame instead of the diode chip. Otherwise the stress may damage the diode chip.

Abstract: A primary side circuit and a secondary side circuit are provided on first and second semiconductor substrates, respectively. A first capacitive insulator on the first substrate electrically insulates and isolates between the primary and secondary side circuits while permitting signal transmission between these circuits. A second capacitive insulator on the second semiconductor substrate electrically isolates the primary and secondary side circuit while permitting signal transmission therebetween. First and second frames are provided for input and output of signals to and from the primary and secondary side circuits. External electrodes of the first and second capacitive insulators are connected together by a third lead frame via a conductive adhesive body including more than one solder ball. The first and second substrates and the lead frames are sealed by a dielectric resin.

Abstract: A method for protecting intermediate conductive elements, such as bond wires, of semiconductor device assemblies, includes sequentially fabricating one or more material layers of one or more protective structures to be associated with the intermediate conductive elements. After a first layer is formed, each subsequent layer is superimposed upon, contiguous with, and mutually adhered to an underlying layer of the protective structure.

Abstract: A method of forming a semiconductor package is provided. The method includes forming a leadframe wherein the conductors or leads of the leadframe extend from a first end to a second end such that a portion of each lead exhibits a generally arcuate shape. The first end may be coupled with a printed circuit board and the second end may be coupled with a semiconductor die. The generally arcuately shaped portion of the leads may include a portion which exhibits a constant radius. The generally arcuately shaped portion may also be formed from a plurality of conductor segments including, for example, at least one generally arcuately shaped segment. The semiconductor die and at least a portion of the leads may be encapsulated with an insulating material.

Abstract: Stress balanced semiconductor device packages, a method of forming, and a method of modifying a mold segment for use in the method are disclosed. A semiconductor die is attached to one side of a substrate having discrete conductive elements such as a ball grid array (BGA) on the opposing side thereof. An envelope of encapsulant material is disposed over the semiconductor die on one side of the substrate while a stress balancing structure comprising at least one stem member and at least one transversely extending branch member formed of encapsulant material is disposed over the opposing side of the substrate in an arrangement which does not interfere with the discrete conductive elements. The envelope and the stress balancing structure may be simultaneously formed.

Abstract: In a chip package (10, 10?, 110, 210), first and second electrical power buses (14, 14?, 16, 16?, 114, 116, 214, 216) are each formed of an electrical conductor having a chip bonding portion (20, 22, 120, 122, 220, 222) and a lead portion (26, 26?, 28, 28?, 126, 128, 226, 228) extending away from the chip bonding portion. The chip bonding portions of the first and second electrical power buses have edges (32, 34, 132, 134, 232, 234) spaced apart from one another to define an extended electrical isolation gap (40, 140, 240). A plurality of chips (42, 44, 46, 142, 143, 144, 145, 146, 147, 148, 242) straddle the extended electrical isolation gap and are electrically connected with the first and second electrical power buses to receive electrical power from the first and second electrical power buses.

Abstract: A microelectronic substrate including at least one microelectronic device disposed within an opening in a microelectronic substrate core, wherein an encapsulation material is disposed within portions of the opening not occupied by the microelectronic devices, or a plurality microelectronic devices encapsulated without the microelectronic substrate core. At least one conductive via extended through the substrate, which allows electrical communication between opposing sides of the substrate. Interconnection layers of dielectric materials and conductive traces are then fabricated on the microelectronic device, the encapsulation material, and the microelectronic substrate core (if present) to form the microelectronic substrate.

Abstract: Two dice may be provided within a single package so that one pin and associated leadfinger may be coupled to bond pads on different dice. This may mean that two different bond pads on different dice are coupled, for example by wirebonding, to the same leadfinger. An adhesive tape may be secured so as to bridge the two dice. One or more conductive traces are formed on the upper side of the adhesive tape and adhesive is provided on the other side to secure the tape to the two dice. As a result, wire bonds may be made from a pad on one die to a trace and then from the opposite side of the trace to a leadfinger. At the same time, a wire bond may be made from a pad on the other die to the same leadfinger. In another embodiment, an adhesive tape with a conductive trace on it may be used as a wire bond bridge to join spaced bond pads on a single chip.

Abstract: A method of establishing an electric connection between electric terminals of a semiconductor component as part of an electric module and additional parts of the electric module by using a punched grid having internal terminal ends and external terminal ends that are electrically connected to the internal terminal ends by metal strip conductors, the semiconductor component and the punched grid are joined so that at least two electric terminals of the semiconductor component are positioned on corresponding internal terminal ends so that a slip-proof mounting of the semiconductor component on the two internal terminal ends is then possible, this mechanical mounting at the same time establishing an electric connection between the electric terminals of the semiconductor component and the internal terminal ends, whereby a metal strip grid, e.g.

Abstract: An electrical package and manufacturing method thereof is provided. A high stiffness, high electrical conductivity, low coefficient of thermal expansion and high thermal conductivity support substrate is used as an initial layer for building the package. A multilayer interconnection structure is formed over the support substrate. Thereafter, a plurality of openings is formed over the support substrate. The openings expose a plurality of bonding pads on a bottom surface of the multi-layer interconnection structure. An electronic device is set up over the multi-layer interconnection structure. Contacts are formed inside the opening over the bonding pads.

Abstract: A semiconductor package includes a semiconductor chip provided with a plurality of electric terminals and a plurality of electrically conductive members electrically connected with the electric terminals. Connection terminals that are spherical in shape and made of solder are electrically connected with the electrically conductive members. A sealing member is used for sealing the semiconductor chip and the electrically conductive members, and for covering the connection terminals so as to allow a part thereof to be exposed. The electrically conductive members are provided with bonding promoters and are connected with the respective spherical connection terminals at the respective bonding promoters.

Abstract: A multilayer printed circuit board (PCB) includes a substrate; a ground layer having edges which define a gap portion, the ground layer being provided on a bottom face of the substrate; and at least two signal traces and provided on a top face of the substrate so as to straddle the gap portion and so as to be substantially parallel to each other. The multilayer PCB also includes at least one ground trace provided between the at least two signal traces and on the top face of the substrate so as to straddle the gap portion.

Abstract: A semiconductor device includes a heat sink adjacent to a die. A dam is positioned at the peripheral edges of the heat sink. During a transfer molding process, the dam serves two purposes. First, the dam prevents damage to the mold. Second, the dam prevents encapsulant packaging compound material from flowing onto the heat sink. The dam may be a gasket. The dam may also be a burr created by, for example, stamping the bottom of the heat sink. The dam may include copper, polyamides, and leadlock tape. The dam may be permanently connected to the heat sink for removal following packaging. The dam may be removed mechanically, through the use of heat, or during an electrolytic deflash cycle.

Abstract: A semiconductor device includes a substrate on which are formed a first group and a second group of leads; and a semiconductor chip having a first group and a second group of electrodes, the first group and a second group of electrodes being arranged respectively on both sides of a region between first and second straight lines, the first and second straight lines being parallel to each other. The semiconductor chip is mounted on the substrate so that the first group of electrodes faces the first group of leads and the second group of electrodes faces the second group of leads. Each of the second group of leads has a bent portion, the bent portion being formed so that a contour of an inner side of each bend of the bent portion draws a curve.

Abstract: A mold gate of a tape substrate includes an aperture formed in the flexible dielectric film of the tape substrate and a support element which is carried by a surface of the flexible dielectric film, is substantially coplanar with conductive traces carried by the flexible dielectric film, and may be formed from the same material as the conductive traces. The aperture of the mold gate may be formed by die cutting or etching processes. The support element of the mold gate may be fabricated by patterning a conductive film and formed at substantially the same time as the conductive traces of the tape substrate are formed. Packaging methods and degating methods that include use of the tape substrate are also within the scope of the present invention.