Abstract: In accordance with the present invention, there is provided a semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and including at least two slots formed therein and extending along respective ones of a pair of the peripheral edge segments thereof. The semiconductor package further comprises a plurality of first leads which are segregated into at least two sets disposed within respective ones of the slots included in the die paddle. In addition to the first leads, the semiconductor package includes a plurality of second leads which are also segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die paddle in spaced relation thereto. Electrically connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of each of the first and second leads.

Abstract: A leadless leadframe with an improved die pad for mold locking includes a die pad and a plurality of leads. The leads are arranged around the die pad. A plurality of indentations, such as side semi-vias, are formed on the sidewall of the die pad for filling a package body of the semiconductor package so as to enhance the horizontal mold locking capability of the die pad.

Abstract: A leadframe includes: a frame rail; a die pad, disposed inside the frame rail, for mounting a semiconductor chip thereon; and a plurality of internal inner leads, which are disposed to surround the die pad and each of which has a convex portion on the bottom thereof. The frame rail and the internal inner leads are retained by a lead retaining member on their upper and/or lower surface(s).

Abstract: A semiconductor package includes a semiconductor chip having a major surface and first pads formed on the major surface. The semiconductor package also includes a package substrate having (a) opposite first and second major surfaces, (b) a side surface extending between the first and second major surfaces, (c) a pad forming region adjacent to and along the side surface, (d) second pads formed on the pad forming region, (e) external electrodes formed on the first major surface of the package substrate, wherein the second major surface of the package substrate is fixed to the major surface of the semiconductor chip, and wherein the external electrodes are electrically connected to the second pads. The semiconductor package further includes bonding wires electrically connecting the first pads to the second pads and a sealing material covering the bonding wires and first and second pads.

Abstract: A method and apparatus for aligning a semiconductor device with a corresponding landing site on a carrier substrate. At least two apertures are formed in a semiconductor device, the apertures passing from a first major surface to a second, opposing major surface of the semiconductor device. Corresponding alignment features are provided on the carrier substrate at the landing site to which the semiconductor device is to be mounted. The alignment features are aligned with the corresponding apertures to effect alignment of the semiconductor device. The alignment features may include apertures corresponding in size, shape and arrangement to the semiconductor device apertures. Alignment pins may be placed through the at least two apertures to assist with alignment.

Abstract: A semiconductor module includes a circuit substrate composed of a wiring pattern, an electrical insulating layer and a thermal radiation board, and in use is fixed to an external thermal radiation member, in which the electrical insulating layer is composed of a thermal conductive mixture containing 70-95 wt % of an inorganic filler and 5-30 wt % of a thermosetting resin. A warping degree of the circuit substrate with respect to the external thermal radiation member is at most 1/500 of a length of the substrate, and the circuit substrate warps to protrude toward the thermal radiation board as the temperature rises. Accordingly, the thermal radiation property does not deteriorate even when the temperature rises in use. At a time of fixing the circuit substrate to the external thermal radiation member, the thermal resistance is kept to be a sufficiently low level.

Abstract: The invention is a leadframe/stabilizer (35) for use with semiconductor devices. Stabilizer (35) is for stabilizing the space between of lead frame leads (36–39) and improving the lead to lead spacing and to improve lead tip planarity. Stabilizer (35) extends partially along the length of and on each side of said lead frame leads (36–39) and include a die pad mount (40), integral with and forming a part of said stabilizer 35.

Abstract: A semiconductor package is disclosed that bonds a semiconductor chip to a leadframe using a flip chip technology. An exemplary semiconductor package includes a semiconductor chip having a plurality of input-output pads at an active surface thereof. A plurality of leads are superimposed by the bond pads and active surface of the semiconductor chip. The leads have at least one exposed surface at a bottom surface of the package body. A plurality of conductive connecting means electrically connect the input-output pads of the chip to the leads. A package body is formed over the semiconductor chip and the conductive connecting means. The bottom surface portions of the leads are exposed to the outside.

Abstract: A semiconductor component for electrical coupling to a substrate (230) includes: a semiconductor chip (110); a non-leaded leadframe (120) including a plurality of electrical contacts (130) located around a periphery (111) of the semiconductor chip; a first electrical conductor (140) electrically coupling together the semiconductor chip and the non-leaded leadframe; and a mold compound (210) disposed around the semiconductor chip, the first electrical conductor, and the plurality of electrical contacts. At least one electrical contact of the plurality of electrical contacts includes: a first surface (310) having a first surface area for electrically coupling to the semiconductor chip; and a second surface (320) opposite the first surface and having a second surface area for electrically coupling to the substrate, where the second surface area is larger than the first surface area.

Abstract: The present invention integrates an inductor into a semiconductor package by integrally forming inductive segments in the leadframe. The inductive segments may be connected directly to a lead of the leadframe, or indirectly to a lead or a bond pad on a semiconductor die via wirebonds to form an inductor. The inductance value for the resultant inductor is typically controlled by the point of contact for the wirebonds or the leads about the inductive segment. The inductance values may also be controlled by the shape and size of the inductive segments. The leadframe may be formed to support multiple inductive segments, and one or more configurations, including those using one or more die flags to support a like number of semiconductor die.

Abstract: A surface mount package for a multi-chip device has a leadframe formed with first and second die pads and leadouts from the respective die pads. An environmentally responsive sensor chip is secured to the first die pad and an environmentally isolated chip is secured to the second die pad. The chips are electrically coupled through the lead frame. A body formed with an over molded portion encases the isolated chip and an open molded portion formed with a recess receives the environmentally sensitive chip. An apertured cover is secured in the recess to form a protective covering over the sensor chip and for allowing communication of the sensor chip externally of the package.

Abstract: A semiconductor package comprising a die pad defining opposed top and bottom surfaces and a peripheral edge. Attached to the peripheral edge of the die pad is a plurality of support feet which extend downwardly relative to the bottom surface thereof. A plurality of leads extend at least partially about the peripheral edge of the die pad in spaced relation thereto. Attached to the top surface of the die pad is a semiconductor die which is electrically connected to at least one of the leads. A package body encapsulates the die pad, the support feet, the leads and the semiconductor die such that at least portions of the leads are exposed in the package body.

Abstract: A method of manufacturing a semiconductor device involves mounting a semiconductor chip, formed on top with a main electrode and a subelectrode smaller in area than the main electrode, on a die pad of an external lead frame through a first bonding material, mounting an inner lead frame in which plural inner leads for connecting the main electrode and the subelectrode on the chip to corresponding connecting pads of the external lead frame are joined together by a tie bar on the chip and the external lead frame through a second bonding material, heating the first and second bonding materials simultaneously for electrically connecting and fixing the chip to the die pad and the inner leads to the electrodes on the chip and the connecting pads of the external lead frame, and cutting the tie bar to separate the inner lead frame into the plural inner leads.

Abstract: A leadframe (20) for a semiconductor device includes a first leadframe portion (12) having a perimeter that defines a cavity (16) and a plurality of leads (14) extending inwardly from the perimeter and a first thickness. A second leadframe portion (18) is attached to the first leadframe portion (16). The second leadframe portion (18) has a die paddle (20) received within the cavity (16) of the first leadframe portion (12). The second leadframe portion (18) has a second thickness that is greater than a thickness of the first leadframe portion (12). Such a dual gauge leadframe is suitable especially for high power devices in which the die paddle acts as a heat sink.

Abstract: In accordance with the present invention, there is provided a memory card which is fabricated through the use of a leadframe comprising an outer dambar defining a central opening, and an inner dambar which is disposed within the central opening. The leadframe further includes a plurality of contacts which are disposed within the central opening and attached to the outer dambar. Disposed within the central opening is at least one die pad, with a plurality of conductive traces extending from respective ones of the contacts toward the die pad. At least one tie bar is attached to and extends between the die pad and each of the outer and inner dambars. The tie bar has at least two downsets formed therein such that the die pad, the outer dambar, and the inner dambar extend along respective ones of at least three spaced, generally parallel planes, the plane of the inner dambar being disposed between the planes of the die pad and the outer dambar.

Abstract: A resin-encapsulation semiconductor device of this invention includes a die pad for mounting a semiconductor element; a plurality of supporting leads; a semiconductor element; a plurality of leads disposed to have tips thereof opposing the die pad; metal wires; and an encapsulation resin for encapsulating the die pad excluding a bottom thereof, the leads excluding bottoms and outside edges thereof, connecting regions with the metal wires, the supporting leads and the semiconductor element. The outside edges of the leads are disposed on substantially the same plane as the side face of the encapsulation resin, and the tip of each lead has a thin portion where the thickness is reduced in an upper face thereof.

Abstract: A semiconductor device package and method of fabricating same. The package includes a lead frame having a die paddle and a plurality of lead fingers. A first semiconductor die exhibiting a first size is adhered to the die paddle and is electrically coupled with one or more of the plurality of lead fingers. A second semiconductor die exhibiting a second size, different from the first size, is also adhered to the die paddle and is electrically coupled with one or more of the plurality of lead fingers. The first semiconductor die and the second semiconductor die each exhibit circuitry which is substantially identical in function. In one embodiment the first semiconductor die may be adhered to a first side of the die paddle while the second semiconductor die is adhered to an opposing side of the die paddle.

Abstract: Upon the manufacture of a non-leaded type semiconductor device having an encapsulater, and a gate cured resin and air vent cured resins which remain as a result of the exposure of leads and tub-suspension leads to a mounting surface of the encapsulater and the formation of the encapsulater, a groove through which a resin flows, is not provided over the full circumference of a cavity defined in a mold die for forming the encapsulater. A gate and air vents are provided outside an area in which no groove is defined. The flow of the resin between the cavity and each of the gate and air vents is made through a gap or space defined between each of the adjacent leads and each tub-suspension lead. If the leads and the tub-suspension leads are cut at a groove-free place, then the occurrence of resin waste and a resin crack can be restrained because the gate cured resin and the air vent cured resins have their surfaces which are identical to the leads and the tub-suspension leads and flat.

Abstract: The invention relates to a carrier for supporting a substrate film during the chip-substrate assembly and bonding process. The carrier provides enhanced rigidity to the substrate film. The degree of rigidity and/or flexibility provided can be controlled by selection of the carrier dimensions, configuration and material choice. Advantages of embodiments of the carrier include easier handling, reduced probability of defective end products, and increased control in choosing the thinness of the substrate film. For example, the substrate film carrier can be used for lead-over-chip (LOC) assemblies and lead-under-chip (LUC) assemblies to create ball grid arrays (BGA), pin grid arrays (PGA), dual in-line packages (DIP), and the like.

Abstract: A lead frame structure includes: at least a die pad for mounting a semiconductor chip thereon; a plurality of suspension members mechanically connected with the die pad; and a plurality of supporting members. Each supporting member has a connection region mechanically connected with each of the plurality of suspension members for mechanically supporting the at least die pad via the plurality of suspension pins. The connection region of the supporting member has a penetrating opening portion which provides a mechanical flexibility to the connection region and which allows the connection region to be deformed toward the suspension member upon application of a tensile stress to the suspension member in a down-set process.

Abstract: A semiconductor chip mounting component includes a support structure adapted to engage a semiconductor chip. The support structure has a top surface, a bottom surface, and a gap extending through the support structure for defining first and second portions of the support structure on opposite sides of the gap. The support structure includes at least one elongated bus disposed alongside the gap, on the second portion of the support structure. The support structure includes a plurality of electrically conductive leads, each lead having a connection section extending across the gap, the connection section having a first end disposed on the first portion of the support structure, and a second end secured to the bus. Each lead includes a frangible section disposed between the first and second ends of the connection section, the frangible section having a cross-sectional area that is smaller than a cross-sectional area of the connection section. The gap is open at the bottom surface of the support structure.

Abstract: A lead frame strip for use in the manufacture of integrated circuit chip packages. The strip comprises at least one array defining a multiplicity of lead frames. The lead frames each include an outer frame defining a central opening having a die pad disposed therein. Attached to the outer frame and extending toward the die pad in spaced relation to each other are a plurality of leads. The outer frames are integrally connected to each other such that the lead frames are arranged in a matrix wherein the leads thereof extend in multiple rows and columns. The leads of the lead frames within each of the rows and columns are arranged in sets which are disposed in spaced relation to each other. A plurality of openings are formed within the strip between and in alignment with the leads of each of the lead frames within each of the rows and columns.

Abstract: In accordance with the present invention, there is provided a semiconductor package which includes a generally planar die paddle defining multiple peripheral edge segments and including at least two slots formed therein and extending along respective ones of a pair of the peripheral edge segments thereof. The semiconductor package further comprises a plurality of first leads which are segregated into at least two sets disposed within respective ones of the slots included in the die paddle. In addition to the first leads, the semiconductor package includes a plurality of second leads which are also segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die paddle in spaced relation thereto. Electrically connected to the top surface of the die paddle is at least one semiconductor die which is electrically connected to at least some of each of the first and second leads.

Abstract: In a leadframe for an LGA package, a lead member is pressed downward to form a land lead with a half-cut portion and a land portion. The land portion, whose bottom will be a land electrode, is inclined at a predetermined angle and the bottom of the land portion is made lower than that of a lead. Thus, in a resin molding process using a seal sheet, the land electrode is forced into, and strongly adhered to, the seal sheet when pressure is applied through dies, and no resin encapsulant reaches the land electrode. As a result, no resin bur will be left on the land electrode of the land lead.

Abstract: A leadframe-based semiconductor package is proposed for the packaging of a semiconductor device, such as a multi-media card (MMC) chipset. The proposed semiconductor package is characterized by the use of a leadframe, rather than BT substrate or film, as the chip carrier for MMC chipset. The leadframe includes a supporting bar; a chip-supporting structure arranged at a downset position in relation to the supporting bar; and a plurality of leads, each lead including an outer-lead portion and an inner-lead portion; wherein the outer-lead portion is levelly linked to the supporting bar, while the inner-lead portion is arranged beside the chip-supporting structure and linked to the outer-lead portion via an intermediate-lead portion. The leadframe can be either the type having die pad or the type having no die pad.

Abstract: A semiconductor package is disclosed that bonds a semiconductor chip to a leadframe using a flip chip technology. An exemplary semiconductor package includes a semiconductor chip having a plurality of input-output pads at an active surface thereof. A plurality of leads are superimposed by the bond pads and active surface of the semiconductor chip. The leads have at least one exposed surface at a bottom surface of the package body. A plurality of conductive connecting means electrically connect the input-output pads of the chip to the leads. A package body is formed over the semiconductor chip and the conductive connecting means. The bottom surface portions of the leads are exposed to the outside.

Abstract: A small footprint package for two or more semiconductor die includes first and second die, mounted on opposite respective surfaces of a lead frame pad in vertical alignment with one another. A conductive or insulation adhesive can be used. The die can be identical MOSgated devices connected in series, or can be one power die and a second IC die for the control of the power die.

Abstract: A semiconductor package comprising a leadframe which includes a die paddle having an opening formed therein. In addition to the die paddle, the leadframe includes a plurality of leads, at least one of which is disposed in spaced relation to the die paddle. The remaining leads are attached to the die paddle and extend therefrom. Electrically connected to the die paddle is the source terminal of a semiconductor die which also includes a gate terminal and a drain terminal. The gate terminal is itself electrically connected to the at least one of the leads disposed in spaced relation to the die paddle. A package body at least partially encapsulates the die paddle, the leads, and the semiconductor die such that portions of the leads and the drain terminal of the semiconductor die are exposed in the package body.

Abstract: An insert conductor that makes it possible to provide a brush holder that does not have wire portions unnecessarily to the outside and which permits reduced manufacturing cost. The insert conductor is equipped with: a conductor which has a wiring section composed of a plurality of wires, an outer frame surrounding the wiring section, and connections which connect the outer frame with the wiring section and which interconnect the wires, and a deformation preventer which is provided on the conductor to prevent the conductor from being deformed by the resin injection pressure applied during insert resin molding.

Abstract: Provided are a lead frame strip and a method of fabricating a semiconductor package using the same. The lead frame strip includes at least one lead frame panel in which a plurality of unit lead frames are arranged to be connected with one another in matrix forms, wherein each unit lead frame includes: a die pad to which a semiconductor chip is to be mounted; a tie bar, an end of which being connected to the die pad and processed to be downset; a plurality of leads positioned at the same level as another end of the tie bar and extended with a predetermined distance from the tie pad; a dam bar formed across the leads and united with the leads to support the leads, wherein a slot is formed along edges of the lead frame panel and functions as a buffer, and a connection bar is formed widthwise across the slot to support the lead frame panel.

Abstract: A lead frame comprises a plurality of frame assemblies. Each framework assembly includes a framework, a suspension lead, a die pad, a plurality of inner leads and outer leads, a first tie bar and a second tie bar, and a lead support. The plurality of framework assemblies are disposed alongside of one another in a direction perpendicular to a direction in which the plurality of outer leads extend. A distance between close-set outer leads in each two neighboring frameworks is substantially n times a pitch of the plurality of outer leads in each framework, wherein n is an integer.

Abstract: An improved lead frame structure for use in a semiconductor package, including: a plurality of leads; a paddle structure electrically isolated from the leads, the paddle structure including at least one lower paddle section having a first top surface to which a die may be attached, at least one mesa section disposed proximate the paddle section and having a second top surface disposed at a different elevation than the first top surface, the lower paddle section and the mesa section being joined by a wall section; and a plurality of tie bars attached to the paddle structure for supporting the paddle structure; whereby contact pads of a die attached to the first top surface may be electrically connected to the second top surface and to the leads prior to encapsulation thereof. A plurality of tie bars extends from opposite edges of the paddle structure, the tie bars providing for stabilizing the paddle structure during package fabrication.

Abstract: A semiconductor package includes a semiconductor chip which is mounted on a die pad which is smaller than the semiconductor chip, a die pad supporter which supports the die pad, the die pad supporter having a stress absorbing portion, the stress absorbing portion is disposed under the semiconductor chip.

Abstract: The present invention relates to a substrate strip with sides having flanges and recesses. The substrate strip is obtained by cutting a panel where a plurality of substrate strips can be arrayed. The substrate strip comprises a first side and a second side. The first side comprises a plurality of first flanges and a plurality of first recesses defined between the first flanges. The second side comprises a plurality of second flanges and a plurality of second recesses defined between the second flanges. The complementary shapes of the first side and the second side are suitable for arraying the two substrate strips most closely, and the most substrate strips can be cut from the panel. Accordingly, waste of the panel can be avoided. The cost of the panel is enormously slashed and the total cost of manufacture is reduced thereby.

Abstract: A surface-mount-enhanced lead frame and a method for fabricating a semiconductor package with the lead frame are proposed, wherein a dam bar structure between any two neighboring lead frames of a lead frame module plate is formed with an indentation and at least a solder metal layer is applied on the bottom surface of the lead frame and the indentation. A singulation process is performed along the indentation to separate the lead frame module plate mounted with semiconductor chips and package body into a plurality of packages. Therefore, the indentation and the solder metal layer applied thereon can provide solder paste improved wettability and increased solder surface, while the semiconductor package with the lead frame is mounted on an external device via a surface-mount-technology, so as to prevent problems of signal transmission owing to separation of solder joint from solder open.

Abstract: Disclosed are flex resistant die pads (18), leadframes (16), and high aspect ratio semiconductor packages (10) using the same. Methods for making devices (10, 16, and 18) according to the invention are also disclosed. Preferred embodiments of the invention are described in which tie bars (24) extending outward from the attachment region (20) of a die pad (18) are used to increase flex resistance of die pads (18), leadframes (16), and packages (10).

Abstract: An integrated circuit package and a process for forming the same. The package includes a semiconductor die with bond pads, a die attachment pad on which the semiconductor die is attached, and a substrate on which the die attachment pad is positioned. A non-conductive lead finger mounting ring is attached to the peripheral region of the substrate. Package leads are attached to the lead finger mounting ring, and are electrically coupled to the bond pads via bond wires. The bond wires are enclosed in an epoxy material having an approximately rounded top surface. The die, the die attachment pad, the substrate, the lead finger mounting ring, and the epoxy material are enclosed in a mold compound.

Abstract: A QFP exposed pad package which includes leads exposed within the bottom surface of the package body of the package in addition to those gull-wing leads protruding from the sides of the package body. Those leads exposed within the bottom surface of the package body are created through the utilization of a standard leadframe with additional lead features that are electrically isolated subsequent to a molding process through the use of a partial saw method.

Abstract: A semiconductor package comprising a substrate which includes a leadframe having a plurality of leads which each define opposed top and bottom surfaces and extends in spaced relation to each other such that gaps are defined therebetween. The substrate further comprises a compound layer which is filled within the gaps defined between the leads. The substrate includes a continuous, generally planar top surface collectively defined by the top surfaces of the leads and compound layer, and a continuous, generally planar bottom surface collectively defined by the bottom surfaces of the leads and compound layer. Attached to the top surface is a semiconductor die which is electrically connected to at least some of the leads.

Abstract: A semiconductor package includes a chip mounting pad having a peripheral edge. The package further includes a semiconductor chip attached to the chip mounting pad. The package further includes a plurality of leads. Each lead includes an inner end and an opposing distal end. Each inner end is disposed adjacent the peripheral edge in spaced relation thereto and vertically downset with respect to each respective distal end. The package further includes at least one isolated ring structure disposed along the peripheral edge between the peripheral edge and the inner ends of the leads in spaced relation thereto. The ring structure is electrically connected to the semiconductor chip and an inner end of at least one of the leads.

Abstract: A semiconductor package comprising a leadframe which includes a die paddle having an opening formed therein. In addition to the die paddle, the leadframe includes a plurality of leads, at least one of which is disposed in spaced relation to the die paddle. The remaining leads are attached to the die paddle and extend therefrom. Electrically connected to the die paddle is the source terminal of a semiconductor die which also includes a gate terminal and a drain terminal. The gate terminal is itself electrically connected to the at least one of the leads disposed in spaced relation to the die paddle. A package body at least partially encapsulates the die paddle, the leads, and the semiconductor die such that portions of the leads and the drain terminal of the semiconductor die are exposed in the package body.

Abstract: A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the bottom surface thereof which create regions of reduced thickness. A semiconductor chip bonded to the chip mounting board may be electrically connected to leads of the lead frame and to the ground ring via conductive wires. Those conductive wires extending to the ground ring are bonded to the top surface thereof at locations which are not aligned with the recesses within the bottom surface, i.e., those regions of the ground ring of maximum thickness.

Abstract: A semiconductor device including a leadframe and two stacked dies, a first of which is on a top surface of a leadframe while the second one is on a bottom surface of the leadframe. The drain region of the first die is coupled to a drain clip assembly that includes a drain clip that is in contact with a lead rail. The body of the semiconductor device includes a window or opening that exposes the drain region of the second die.

Abstract: Embodiments of the invention include an integrated circuit package and methods for its construction. An integrated circuit package of the invention includes a die attach pad and a plurality of lead pads. An integrated circuit die is mounted with the front side of the die attach pad and electrically connected to the plurality of lead pads. Additionally, the backside of the die attach pad includes a pattern of mesas formed thereon. Each of the mesas is configured such that they have a top surface area that is substantially the same size as the surface area of the lead pads. A contact layer of reflowable material is formed on the top surface of the mesas and the lead pads, forming an integrated circuit package with an improved contact layer.

Abstract: The present invention integrates an inductor into a semiconductor package by integrally forming inductive segments in the leadframe. The inductive segments may be connected directly to a lead of the leadframe, or indirectly to a lead or a bond pad on a semiconductor die via wirebonds to form an inductor. The inductance value for the resultant inductor is typically controlled by the point of contact for the wirebonds or the leads about the inductive segment. The inductance values may also be controlled by the shape and size of the inductive segments. The leadframe may be formed to support multiple inductive segments, and one or more configurations, including those using one or more die flags to support a like number of semiconductor die.

Abstract: A two-lead, surface-mounting, high-power micro-leadframe semiconductor package has the same outline, mounting, and electrical functionality as industry standard leadframe packages but provides a lower internal resistance, a higher package power rating, and costs less to produce. The novel package incorporates one of a rectangular array of “micro-leadframes” (“MLFs”), each having parallel and respectively coplanar upper and lower surfaces etched in a plate having a uniform thickness. Each micro-leadframe includes an I-shaped die pad having a head, a foot, and opposite sides. First and second leads are disposed at the foot of the die pad, each having a side aligned with one of the sides of the pad. The second lead has an right-angled wire-bonding pad next to the die pad. A portion of a lower surface of each of the die pad and the leads is exposed through a lower surface of an envelope of plastic molded on the package to define package input/output terminals.

Abstract: A leadframe configuration for a semiconductor device that has a die attach paddle with paddle support bars. In addition, clamp tabs extend outwardly from lesser supported locations of the paddle to underlie a conventional lead clamp. The clamp tabs are formed as an integral part of the paddle. Normal clamping during die attach and wire bonding operations prevents paddle movement and enhances integrity of the die bond and wire bonds.

Abstract: A permanent protective semiconductor die coating made from a polymer that is fully curable through exposure to ultra violet light. A mixture of polymer resin and a photoactive compound is applied to the die and then cured through exposure to ultraviolet light to form the protective coating. In one preferred embodiment, the polymer resin is a phenol-formaldehyde epoxy resin and the photoactive compound is CD1011 (marketed under the brand name SARTOMER□. The coating may be applied as a thin protective film, such as a passivation layer, or as a thicker encapsulant used for semiconductor device packages. Such film coatings exhibit reduced film shrinkage and lower film stresses while maintaining mechanical properties comparable to polyimide film coatings.

Abstract: A semiconductor device (200) having a substrate routed power supply voltage is disclosed. The semiconductor device (200) includes a relatively highly doped substrate (302) and an epitaxial layer (304) formed over the substrate (302). In one embodiment (200), a surrounding conductive structure (202) is formed on the peripheral edges of the semiconductor device (200) die. The surrounding conductive structure (202) is coupled to the substrate (302). In another embodiment, the back side of the die (404) is coupled to the conductive portion (402) of an integrated circuit package. The conductive portion (402) is coupled to a power supply voltage. In another embodiment (700), the surrounding conductive structure (702) is coupled to a power supply voltage by one or more bond pads (710) formed on, or coupled to, the surrounding conductive structure (702).

Abstract: An edge stiffener added to a lead-frame based circuit module provides protection of the peripheral flange of the circuit module during handling and manufacturing processes. The edge stiffener may be coupled to leads of the lead-frame for providing electrical contacts at the periphery of the circuit module or may be form widened portions of a tie bar that is connected to the lead frame by leads extending through gaps between the ends of the edge stiffener portions. Singulation of the circuit module will result in edge stiffener portions that are not coupled to the lead frame, but are secured within the encapsulant.