Abstract: The present invention provides a package stacking lead frame system comprising forming a lead frame interposer including a dual row of terminal leads positioned around a die attach pad, mounting a first die on the die attach pad, wherein the first die is connected to the dual row of terminal leads, molding a molding compound around the first die and the dual row of terminal leads and mounting a second integrated circuit package on the lead frame interposer, wherein the second integrated circuit package size is independent of the first die size.

Abstract: An optical navigation device includes an integrated package. The integrated package includes a planar leadframe, a light source die mounted on the leadframe, and a sensor die mounted on the leadframe to be coplanar with the light source die. The integrated package may be mounted at an angle or parallel to a navigation surface. The sensor die may be mounted at a distance from the light source die to detect specular or scattered reflection. The optical navigation device may be devoid of any optical element used to manipulate light generated by the light source die.

Abstract: A sensor package apparatus includes a lead frame substrate that supports one or more electrical components, which are connected to and located on the lead frame substrate. A plurality of wire bonds are also provided, which electrically connect the electrical components to the lead frame substrate, wherein the lead frame substrate is encapsulated by a thermoset plastic to protect the plurality of wire bonds and at least one electrical component, thereby providing a sensor package apparatus comprising the lead frame substrate, the electrical component(s), and the wire bonds, while eliminating a need for a Printed Circuit Board (PCB) or a ceramic substrate in place of the lead frame substrate as a part of the sensor package apparatus. A conductive epoxy can also be provided for maintaining a connection of the electrical component(s) to the lead frame substrate. The electrical components can constitute, for example, an IC chip and/or a sensing element (e.g., a magnetoresistive component) or sense die.

Abstract: A method (300) for fabricating a lead frame (100), comprising forming a plurality of external leads (122) in a lead frame material (108), plating a metal (222) on all surfaces of the lead frame material (108), and subsequently forming a plurality of internal leads (124) in the lead frame material (108). The lead frame material (108) may comprise of a portion of a contiguous metal sheeting (204) rolled upon a first coil (202), wherein the contiguous metal sheeting (204) is fed into an external lead stamping apparatus (206), thus forming the external leads (122), and rolled onto a second coil (215). The portion is fed into a plating apparatus and plated with the metal (222), and rolled onto a third coil (218) prior to forming the plurality of internal leads (124). The third coil (218) can be unrolled into an internal lead stamping apparatus (226), thus forming the internal leads (124) of a lead frame (100).

Abstract: A stacked package structure with leadframe having bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, in which the die pad is provided between the inner leads and is vertically distant from the inner leads; a bus bar being provided between the inner leads and the die pad; an offset chip-stacked structure stacked by a plurality of chips, the offset chip-stacked structure being fixedly connected to a first surface of the die pad and electrically connected to the inner leads; and an encapsulant covering the offset chip-stacked structure, the inner leads, the first surface of die pad, and the upper surface of bus bar, the second surface of die pad and the lower surface of bus bar being exposed and the outer leads extending out of the encapsulant.

Abstract: The present invention discloses a method for fabricating a quad flat non-leaded package. A lead frame is disposed on a lower mold equipped with a resilient film. The lead frame includes at least a package unit comprising a chip pedestal and a plurality of pins spatially disposed around the chip pedestal. An upper mold corresponding to the lower mold is provided over the lead frame for encapsulation. The upper mold is pressed to form a protrusion from a resilient film between the chip pedestal and the pins, and then the chip pedestal and the pins are encapsulated by a molding material. The resilient film is removed to form a QFN structure with the lead frame protruding from the molding material.

Abstract: An integrated circuit package having a die pad with a first face and a second face, a plurality of inner leads, and a plurality of sides between the first face and the second face. The plurality of inner leads is disposed substantially co-planer with and substantially around the die pad. The package also comprises a plurality of outer leads disposed substantially co-planar with and substantially around the plurality of inner leads and the die pad, so that the sides of each of the plurality of outer leads are offset from the sides of each of the plurality of inner leads. A first adhesive layer disposed on the first face of the die pad and a second adhesive layer disposed on the first faces of each of the plurality of inner leads. An IC chip is coupled to the first face of the die pad through the first adhesive layer and to the plurality of inner leads through the second adhesive layer. The package further comprises wires linking the inner leads and outer leads to the IC chip.

Abstract: The present invention provides a chip-stacked package structure with leadframe having multi-piece bus bar, comprising: a leadframe composed of a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, wherein the die pad is provided between the plurality of inner leads arranged in rows facing each other and is vertically distant from the plurality of inner leads; a chip-stacked structure formed with a plurality of chips stacked together and provided on the die pad, the plurality of chips and the plurality of inner leads arranged in rows facing each other being electrically connected with each other; and an encapsulant provided to cover the chip-stacked structure and the leadframe; wherein the leadframe comprises at least a bus bar provided between the plurality of inner leads arranged in rows facing each other and the die pad, the bus bar being formed by multiple pieces.

Abstract: A chip-stacked structure for packaging with lead-frame having bus bar formed with transfer pads is disclosed. The structure includes a lead-frame, an offset multi-chip-stacked structure, and an encapsulant. The lead frame includes a plurality of inner leads arranged in rows facing each other, a plurality of outer leads, and a die pad, the die pad being provided between the inner leads and being vertically distant from the inner leads. The offset multi-chip-stacked structure is set on the die pad and electrically connected with the inner leads. The encapsulant is used to cover the offset multi-chip-stacked structure and the lead frame. The lead frame also includes at least a bus bar provided between the inner leads and the die pad, and the bus bar is coated thereon with an insulation layer selectively formed with a plurality of metal pads.

Abstract: In one embodiment of the invention, a lead-frame is designed for use in IC packages such as those conforming to the TO 220 standard or other standards for power packages. The device areas of the lead-frame are arranged in columns, and each column is molded so as to expose a portion of the leads. The device areas can then be singulated by sawing, as in conventional QFN packages. In this manner, packages conforming to power package standards such as the TO 220 standard can be produced much quicker and cheaper than they can in conventional trim and forming methods.

Abstract: A semiconductor device which permits reduction in the number of pins and in size thereof is provided.

Abstract: A method for fabricating a large die package with a leadframe having leads and a paddle is provided. An interposer is attached onto the leadframe with the interposer extending over at least a portion of the paddle and at least a portion of the leads of the lead-frame. The interposer is insulated from the leads. A die is attached to the interposer.

Abstract: The present invention relates to a stress-free lead frame (1) for a semiconductor. The stress-free lead frame (1) is provided with a stress-relief means (15) and an interlocking means (16) at the outer periphery. The stress-relief means (15) is capable of accommodating expansion and compression while the interlocking means (16) take care of shock and vibration during handling to thereby eliminate delamination of the lead frame (10).

Abstract: An integrated circuit package system including an integrated circuit die and a lead frame with a trenched die pad. The integrated circuit die is mounted to the trenched die pad.

Abstract: A semiconductor device package comprising a semiconductor device and an electrically conductive lead frame at least partially covered by a molding compound. The electrically conductive lead frame includes a plurality of leads disposed proximate a perimeter of the package and a die pad disposed in a central region formed by the plurality of leads. The die pad includes a first die pad surface disposed at the first package face, and a second die pad surface opposite the first die pad surface. The semiconductor device is attached to a central region of the second die pad surface, and a portion of the second die pad surface extending outward from the die is roughened to improve adhesion of the die pad to the molding compound. In other aspects, grooves are disposed in the first and/or second die pad surfaces to further promote adhesion of the die pad and to prevent moisture from permeating into the vicinity of the semiconductor chip.

Abstract: Signal traces are patterned on a top surface of a substrate. A ground trace is patterned on the top surface of the substrate for at least one pair of the signal traces. A die paddle is patterned on the top surface of the substrate, and the die paddle is connected directly with the ground trace.

Abstract: A leadframe includes a die pad, a plurality of tie bars, a plurality of metal extrusions and a plurality of leads. The leads are arranged around the die pad. The tie bars are connected to the corners of the die pad, and the metal extrusions are connected to the sides of the die pad but separated from the tie bars. Each metal extrusion has a locking hole and a bonding surface, which is higher than the die pad. The metal extrusions are configured for improving ground connections by wire-bonding. When a bottom surface of the die pad is exposed from an encapsulant for a semiconductor package, the metal extrusions help to secure the die pad without stress transmission.

Abstract: A dense semiconductor flip-chip device assembly is provided with a heat sink/spreading/dissipating member that is formed as a paddle of a metallic paddle frame in a strip of paddle frames. Semiconductor dice are bonded to the paddles by, e.g., conventional semiconductor die attachment methods, enabling bump attachment and testing to be conducted before detachment from the paddle frame strip.

Abstract: A ground-enhanced semiconductor package and a lead frame used in the package are provided. The semiconductor package includes a lead frame having a die pad, a plurality of tie bars connected with and supporting the die pad, a plurality of leads surrounding the die pad, and a ground structure, wherein the ground structure comprises at least one of first ground portions connected to the tie bars, and/or at least one of second ground portions connected to the die pad, and wherein the first ground portions are separate from each other, and the second ground portions are separate from each other; at least one chip mounted on the die pad and electrically connected to the leads and the ground structure; and an encapsulation body for encapsulating the chip and the lead frame. The separately-arranged ground portions allow thermal stresses to be released from the ground structure without rendering deformation issues.

Abstract: An image reading apparatus (10) includes a photoelectric conversion element formation substrate (4) having a plurality of photoelectric conversion elements (2) on a reverse surface of an information reading surface, and a supporting substrate (1) bonded by an adhesive resin (5) to the photoelectric conversion element formation substrate (4) so that the supporting substrate (1) is integrated with the photoelectric conversion element formation substrate (4) and faces the plurality of photoelectric conversion elements (2) on the photoelectric conversion element formation substrate (4). With this arrangement, provided is a photoelectric conversion apparatus and manufacturing method of same in which (a) a process of bonding a micro glass sheet is not required and (b) a protrusion of an installation portion toward a surface of a document is eliminated.

Abstract: A connection arrangement for a micro lead frame plastic (MLP) package is provided that includes a paddle configured to be connected to a circuit board and a first ground pad and a second ground pad each connected to the paddle. The first and second ground pads together with the paddle are configured to provide continuity of ground between the circuit board and a chip mounted to the paddle.

Abstract: A method (300) for fabricating a lead frame (100), comprising forming a plurality of external leads (122) in a lead frame material (108), plating a metal (222) on all surfaces of the lead frame material (108), and subsequently forming a plurality of internal leads (124) in the lead frame material (108). The lead frame material (108) may comprise of a portion of a contiguous metal sheeting (204) rolled upon a first coil (202), wherein the contiguous metal sheeting (204) is fed into an external lead stamping apparatus (206), thus forming the external leads (122), and rolled onto a second coil (215). The portion is fed into a plating apparatus and plated with the metal (222), and rolled onto a third coil (218) prior to forming the plurality of internal leads (124). The third coil (218) can be unrolled into an internal lead stamping apparatus (226), thus forming the internal leads (124) of a lead frame (100).

Abstract: A semiconductor device comprises a semiconductor chip which is mounted on a stage. A plurality of leads are electrically connected with the semiconductor chip. A package encloses the semiconductor chip and a part of the plurality of leads. A first corner lead is provided in the stage and outwardly extends from at least one of vertex portions at four corners of the stage to an exterior of the package.

Abstract: A semiconductor device which permits reduction in the number of pins and in size thereof is provided.

Abstract: Provided is a method of producing a semiconductor package including at least two rows of leads in which the leads of each row separately connecting a semiconductor chip to an external substrate. The method includes: forming a lead frame, the lead frame including a die pad and a plurality of leads arranged about the die pad; attaching an adhesive tape to a surface of the lead frame covering at least substantially the die pad and the plurality of leads; removing portions of the leads and the adhesive tape disposed in a dividing region and thereby separating at least some of the plurality of leads to form multiple rows of leads; and mounting a semiconductor chip on the die pad, electrically connecting the semiconductor chip with the lead frame, and molding the lead frame and the semiconductor chip to provide a semiconductor package. The adhesive tape attached at undesirable locations of the lead frame is preferably removed after provision of the semiconductor package.

Abstract: A semiconductor package including a lead frame comprising a frame including both a ground ring and a chip mounting board located therein. Extending between the ground ring and the chip mounting board are a plurality of elongate slots or apertures. The ground ring is formed to include recesses within the bottom surface thereof which create regions of reduced thickness. A semiconductor chip bonded to the chip mounting board may be electrically connected to leads of the lead frame and to the ground ring via conductive wires. Those conductive wires extending to the ground ring are bonded to the top surface thereof at locations which are not aligned with the recesses within the bottom surface, i.e., those regions of the ground ring of maximum thickness.

Abstract: A surface mount package for a multi-chip device has a leadframe formed with first and second die pads and readouts from the respective die pads. An environmentally responsive sensor chip is secured to the first die pad and an environmentally isolated chip is secured to the second die pad. The chips are electrically coupled through the lead frame. A body formed with an over molded portion encases the isolated chip and an open molded portion formed with a recess receives the environmentally sensitive chip. An apertured cover is secured in the recess to form a protective covering over the sensor chip and for allowing communication of the sensor chip externally of the package.

Abstract: A lead frame is configured for use with a singulation apparatus that eliminates flash. A die pad is attached to sides of the frame by tie bars and peripheral portions. The peripheral portions have cutout sections defining openings that are bridged by lead frame segments. The apparatus applies a downward force to the lead frame segments and translates the downward force to a horizontal force applied to the tie bars. The singulation process confines movement of the lead frame metal to within the plane of the lead frame.

Abstract: A substrate strip with warpage-preventive linkage structure is proposed for a BGA (Ball Grid Array) application. The proposed substrate strip is composed of a series of substrates, each being used for the construction of an individual unit of a BGA package, and which is characterized by the provision of a warpage-preventive linkage structure, by which each substrate on the substrate strip is supported by means of no more than two tie bars, i.e., either by a two-point linkage structure or a one-point linkage structure, in contrast to the four-point linkage structure utilized by the prior art. During high-temperature fabrication steps when the substrate is subjected to thermal stresses, the substrate can freely expand toward the corners where no tie bars are provided; and consequently, it can be unwarped by the thermal stresses. This unwarped substrate allows the subsequently implanted ball grid array thereon to have high coplanarity.

Abstract: A semiconductor device includes: a semiconductor element; a die pad with the semiconductor element mounted thereon; a plurality of electrode terminals each having a connecting portion electrically connected with the semiconductor element; and a sealing resin for sealing the semiconductor element, the die pad and the electrode terminals so that a surface of each electrode terminal on an opposite side from a surface having the connecting portion is exposed as an external terminal surface. A recess having a planar shape of a circle is formed on the surface of each electrode terminal with the connecting portion, and the recess is arranged between an end portion of the electrode terminal exposed from an outer edge side face of the sealing resin and the connecting portion. While a function of the configuration for suppressing the peeling between the electrode terminal and the sealing resin can be maintained by mitigating an external force applied to the electrode terminal, the semiconductor device can be downsized.

Abstract: An inventive leadframe includes an outer frame, a die pad, and a plurality of leads each having land portions and connections. The land portions each have an upper surface serving as a bonding pad to be connected with a metal wiring, and a lowermost part serving as an external terminal. The connections are each devoid of its lower part so as to be thinner than the land portion, and are provided between the outer frame and the land portions, between the land portions associated with each other in each lead, and between the land portions and the die pad. Furthermore, the inventive leadframe is provided with no member that functions as a suspension lead for connecting the outer frame and the die pad to each other during plastic encapsulation.

Abstract: An area array type semiconductor package includes a plurality of conductive media such as solder bumps or solder balls, attached to respective bond pads of a chip. The conductive media act as external output terminals. The chip is attached to a lead frame by a thermal conductive adhesive, and a predetermined area of the lead frame and the semiconductor chip are packaged with a molding resin. Leads of the lead frame are then trimmed and formed so that the lead frame, to which the semiconductor chip is adhered, acts as a heat sink. This allows the package to be used for a high-powered semiconductor device which radiates a high temperature heat. Also, because conductive media such as solder bumps or solder balls can be used to directly connect bond pads of the chip to conductive regions of a circuit board, a size of the semiconductor package can be minimized, the arrangement of the bonding pads on the chip can be easily planned, and electrical characteristics of the semiconductor package can be improved.

Abstract: A semiconductor die mounted between an X-lead frame and a support structure without bonding wires or straps. A power enhancement mode junction field effect transistor (JFET) die having a top surface defining a drain, and a bottom surface having a first metalized region defining a source and a second metalized region defining a gate, is positioned on a support structure. An X-lead frame is bonded to the support structure such that electrical contact is made with an external lead. Angular projections from the X-lead frame make contact with the top surface of the JFET, hold the die in place on the support structure, and form electrical continuity between the JFET drain and the external lead. A construction on the surface of the support structure is positioned directly under the source region on the bottom of the JFET die and forms electrical continuity between the JFET source and a second external lead.

Abstract: An integrated circuit package having a die pad and a plurality of leads is disclosed. At least one of the plurality of leads has a recess formed in a first face thereof. The package also has an integrated circuit chip coupled to the die pad through an adhesive layer. A plurality of wires each link a first face of the integrated circuit chip to one of the plurality of leads. An encapsulant encloses the integrated circuit chip, the plurality of wires, the die pad, and a portion of each of the plurality of leads. The encapsulant forms a plurality of side walls which slant downward and outward. At least one of the side walls intersects with the first face of the at least one lead within the side walls of the recess formed therein.

Abstract: A leadframe for a semiconductor package is formed with an indentation on a bottom surface. A side of the indentation is used to form a mold-lock that assists in securing the leadframe to the encapsulation material of the semiconductor package.

Abstract: A lead-frame based substrate panel for use in semiconductor packaging is described. The substrate panel includes a lead-frame panel having at least one array of device areas. Each device area has a plurality of contacts. The lead-frame panel is filled with a dielectric material to form a relatively rigid substrate panel that can be used for packaging integrated circuits. The top surface of the dielectric material is typically substantially coplanar with the top surface of the lead-frame panel, and the bottom surface of the dielectric material is typically substantially coplanar with the bottom surface of the lead-frame panel.

Abstract: A semiconductor package comprising a substrate which includes a leadframe having a plurality of leads which each define opposed top and bottom surfaces and extends in spaced relation to each other such that gaps are defined therebetween. The substrate further comprises a compound layer which is filled within the gaps defined between the leads. The substrate includes a continuous, generally planar top surface collectively defined by the top surfaces of the leads and compound layer, and a continuous, generally planar bottom surface collectively defined by the bottom surfaces of the leads and compound layer. Attached to the top surface is a semiconductor die which is electrically connected to at least some of the leads.

Abstract: A semiconductor device assembly including a semiconductor device having a plurality of bond pads on the active surface thereof and a lead frame having a portion of the plurality of lead fingers of the lead frame located below the semiconductor device in a substantially horizontal plane and another portion of the plurality of lead fingers of the lead frame located substantially in the same horizontal plane as the active surface of the semiconductor device. Both pluralities of lead fingers of the lead frame having their ends being located substantially adjacent the peripheral sides of the semiconductor device, rather than at the ends thereof.

Abstract: A method of fabricating a memory card. The method comprises the initial step of providing a leadframe which has a dambar and a plurality of contacts, each of the contacts being attached to the dambar by at least one tie bar. A layer of tape is applied to the leadframe such that the tape covers at least portions of the top contact surfaces of the contacts, at least portions of the top tie bar surfaces of the tie bars, and at least a portion of the top dambar surface of the dambar. Thereafter, the tie bars are removed from the leadframe. At least one semiconductor die is then electrically connected to the leadframe, with a body thereafter being formed on the leadframe such that the semiconductor die and the tape are covered by the body and the bottom contact surfaces are exposed in an exterior surface thereof.

Abstract: Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant. A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrically connected to the tabs. An encapsulant is applied to the upper and side surfaces of the leadframe. Finally, the leadframe is cut in situ so that the die pad and tabs are severed from the frame, the sides of the package are formed, and the package is severed from the leadframe.

Abstract: A semiconductor package includes a semiconductor chip provided with a plurality of electric terminals and a plurality of electrically conductive members electrically connected with the electric terminals. Connection terminals that are spherical in shape and made of solder are electrically connected with the electrically conductive members. A sealing member is used for sealing the semiconductor chip and the electrically conductive members, and for covering the connection terminals so as to allow a part thereof to be exposed. The electrically conductive members are provided with bonding promoters and are connected with the respective spherical connection terminals at the respective bonding promoters.

Abstract: A leadframe for a semiconductor package includes signal and ground leads, a ground plane, and a frame paddle. Supports connect the signal and ground leads, ground plane, and frame paddle in at least two different layers. At least one force release and stress relief structure is incorporated into the leadframe to free the ground plane substantially from distortion and warpage resulting from residual mechanical stresses therein.

Abstract: An inventive leadframe includes an outer frame, a die pad, and a plurality of leads each having land portions and connections. The land portions each have an upper surface serving as a bonding pad to be connected with a metal wiring, and a lowermost part serving as an external terminal. The connections are each devoid of its lower part so as to be thinner than the land portion, and are provided between the outer frame and the land portions, between the land portions associated with each other in each lead, and between the land portions and the die pad. Furthermore, the inventive leadframe is provided with no member that functions as a suspension lead for connecting the outer frame and the die pad to each other during plastic encapsulation.

Abstract: A semiconductor package which includes a die pad that is exposed through the top surface of its molded housing, a semiconductor die having one power electrode electrically and mechanically connected to the underside of the die pad, and another power electrode electrically connected to a lead.

Abstract: Packages for an integrated circuit die and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, peripheral metal contacts, bond wires, and an encapsulant. The die pad and contacts are located at a lower surface of the package. The die pad and the contacts have side surfaces which include reentrant portions and asperities to engage the encapsulant. A method of making a package includes providing a metal leadframe having a die pad in a rectangular frame. Tabs extend from the frame toward the die pad. The die pad and tabs have side surfaces with reentrant portions and asperities. A die is attached to the die pad. The die is electrically connected to the tabs. An encapsulant is applied to the upper and side surfaces of the leadframe. Finally, the leadframe is cut in situ so that the die pad and tabs are severed from the frame, the sides of the package are formed, and the package is severed from the leadframe.

Abstract: A lead frame for use in solid state relays has a teardrop shaped frame. The frame has a small rounded portion connected to a large rounded portion. A power semiconductor is mounted in the large rounded portion. The teardrop shape eliminates sharp corners found in rectangular frames and allows heat to dissipate radially in all directions. More metal in close proximity to the power semiconductor, maintaining a lower aspect ratio of length to width, allows the semiconductor to run cooler at any given load. Several vent holes are located in the small rounded portion, which act as exhaust ports for the fumes generated in the heating stage of the solder re-flow, increasing solder coverage and improving reliability. The life of solder junctions utilizing the teardrop shaped lead frame which are subjected to temperature cycling while under load is increased, thus extending the life of the solid state relay.

Abstract: An ultra-thin semiconductor package includes a lead frame having a die pad and a plurality of leads surrounding the die pad. The die pad includes a chip attaching part to which a semiconductor chip is attached and a peripheral part integral with and surrounding the chip attaching part. The thickness of the chip attaching part is smaller than the thickness of the leads. The package device further includes bonding wires electrically connecting the chip to the leads, and a package body for encapsulating the semiconductor chip, bonding wires, die pad, and inner portions of the leads. A first thickness of the die pad is preferably between about 30–50% of a second thickness of the leads. An overall thickness of the package device is preferably equal to or less than 0.7 mm.

Abstract: A lead frame (201) for a packaged electronic device having split flag structures (205, 207) coupled by support structures (219). The support structures include bend portions (233) for providing stress relief between the flag structures during the manufacture and/or during the operation of a packaged electronic device (301). In one embodiment, the packaged electronic device includes an inertial sensor (515).

Abstract: Methods and apparatuses for providing leadless leadframes with dummy contact leads are disclosed. A leadframe is described that includes an enclosed frame having two lengthwise portions and two widthwise portions. The leadframe also includes a device area array with dummy contact leads formed on the peripheral edges of the device area array. Furthermore, dummy contact leads are positioned along a tie bar such that they are directly opposite corresponding contact leads. By cutting along the tie bar, dummy contact leads are separated from the device area array.

Abstract: The semiconductor integrated circuit device comprises a planar leadframe having lead segments arranged in alternating order into first and second pluralities, the segments having their inner tips near the chip mount pad and their outer tips remote from the mount pad. The outer tips have a solderable surface. All outer tips are bent away from the leadframe plane into the direction towards the intended attachment locations on an outside substrate such that the first segment plurality forms an angle of about 70±1° from the plane and the second segment plurality forms an angle of about 75±1° (see FIG. 4). Consequently, the outer tips create a staggered lead pattern suitable for solder attachment to an outside substrate.