With Bumps On Ends Of Lead Fingers To Connect To Semiconductor Patents (Class 257/673)
  • Patent number: 10706345
    Abstract: A micro radio frequency identification tag for use on articles in an equipment identification and tracking system includes a substrate, an RFID chip, a power storage means, an antenna, and a conductive means. The substrate has a pair of surfaces. The RFID chip and power storage means are operatively retained on one surface. The antenna is operatively retained on the other surface of the substrate and acts as a conductive layer. The conductive means extends between the surfaces of the substrate to operatively connect the antenna to the RFID chip and power storage means.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: July 7, 2020
    Inventor: Brian K. Blank
  • Patent number: 10700028
    Abstract: A multi-grooved interposer includes an interposer substrate containing multiple parallel grooves laterally extending along a first direction and laterally spaced among one another along a second direction, and multiple conductive strips. The multiple parallel grooves are recessed from front side surfaces of the multi-grooved interposer in a third direction toward a back side surface of the multi-grooved interposer. The multiple conductive strips continuously extend across recessed surfaces in the multiple parallel grooves and the front side surfaces along the second direction with an undulating surface profile to provide electrically conductive paths across the multiple parallel grooves. Each of the multiple parallel grooves is configured to receive an edge of a respective semiconductor chip.
    Type: Grant
    Filed: February 9, 2018
    Date of Patent: June 30, 2020
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Akio Nishida
  • Patent number: 10687419
    Abstract: A semiconductor package device includes a first dielectric layer, a first interconnection layer, a second interconnection layer, and a second dielectric layer. The first dielectric layer has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The first interconnection layer is within the first dielectric layer. The second interconnection layer is on the second surface of the first dielectric layer and extends from the second surface of the first dielectric layer into the first dielectric layer to electrically connect to the first interconnection layer. The second dielectric layer covers the second surface and the lateral surface of the first dielectric layer and the second interconnection layer.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: June 16, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming-Ze Lin, Chia Ching Chen, Yi Chuan Ding
  • Patent number: 10535644
    Abstract: A manufacturing method of a package on package structure includes the following steps. A first package is provided on a tape carrier, wherein the first package includes an encapsulated semiconductor device, a first redistribution structure disposed on a first side of the encapsulated semiconductor device, and a plurality of conductive bumps disposed on the first redistribution structure and attached to the tape carrier. A second package is mounted on the first package through a plurality of electrical terminals by a thermo-compression bonding process, which deforms the conductive bumps into a plurality of deformed conductive bumps. Each of the deformed conductive bumps comprises a base portion connecting the first redistribution structure and a tip portion connecting the base portion, and a curvature of the base portion is substantially smaller than a curvature of the tip portion.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsuan-Ting Kuo, Ching-Hua Hsieh, Cheng-Ting Chen, Hsiu-Jen Lin, Hao-Jan Pei, Yu-Peng Tsai, Chia-Lun Chang, Chih-Chiang Tsao, Philip Yu-shuan Chung
  • Patent number: 10512181
    Abstract: A power semiconductor device includes a first power semiconductor element, a second power semiconductor element, a first conductor plate, a second conductor plate, a third conductor plate, and a fourth conductor plate. The power semiconductor device also includes a DC positive terminal, a DC negative terminal, an AC terminal, and a sealing member that integrally seals the first conductor plate, the second conductor plate, the third conductor plate, and the fourth conductor plate. Each of the DC positive terminal, the DC negative terminal, and the AC terminal has a cut section formed by cutting a tie bar that integrally couples the DC positive terminal, the DC negative terminal, and the AC terminal.
    Type: Grant
    Filed: June 25, 2018
    Date of Patent: December 17, 2019
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Tokihito Suwa, Yujiro Kaneko, Yusuke Takagi, Shinichi Fujino, Takahiro Shimura
  • Patent number: 10475667
    Abstract: A semiconductor module is provided with a conductive member having one end, in a longitudinal direction, joined to an electrode of a semiconductor element that is mounted on an insulating substrate, the other end of the conductive member in the longitudinal direction being joined to a component different from the electrode. The conductive member is made up of a metal sheet, and has a bent portion at the one end and at the other end. The bent portion provided at the one end has a cut in a leading end portion, in the longitudinal direction, and an end joining section at which the cut is not present is joined to the electrode of the semiconductor element. As a result, a semiconductor module can be realized that allows combination of increased current capacity with improved reliability.
    Type: Grant
    Filed: November 6, 2014
    Date of Patent: November 12, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masakazu Tani, Yoshiyuki Deguchi, Kazuki Sakata
  • Patent number: 10446460
    Abstract: The semiconductor device includes a first insulating circuit substrate; a semiconductor chip including a plurality of control electrodes, disposed on the first insulating circuit substrate; a second insulating circuit substrate including a plurality of first through-holes in which conductive members are arranged on inner walls and/or an outer periphery of ends of the first through-holes, the second insulating circuit substrate being disposed above the semiconductor chips; and first pins inserted into the first through-holes and having at one end a columnar part connected to the control electrodes of the semiconductor chips, and having at another end a head part that is wider than an inner diameter of the first through-holes.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: October 15, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiromichi Gohara, Kohei Yamauchi, Shinji Tada, Tatsuo Nishizawa, Yoshitaka Nishimura
  • Patent number: 10437557
    Abstract: Apparatuses, systems, and methods related to determination of a match between data values stored by several arrays are described. A system using the data values may manage performance of functions, including automated functions critical for prevention of damage to a product, personnel safety, and/or reliable operation, based on whether the data values match. For instance, one apparatus described herein includes a plurality of arrays of memory cells formed on a single memory chip. The apparatus further includes comparator circuitry configured to compare data values stored by two arrays selected from the plurality to determine whether there is a match between the data values stored by the two arrays. The apparatus further includes an output component configured to output data values of one of the two arrays responsive to determination of the match between the data values stored by the two arrays.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: October 8, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Aaron P. Boehm
  • Patent number: 10366318
    Abstract: A micro radio frequency identification tag for use on articles in an equipment identification and tracking system includes a substrate, an RFID chip, a power storage means, an antenna, and a conductive means. The substrate has a pair of surfaces. The RFID chip and power storage means are operatively retained on one surface. The antenna is operatively retained on the other surface of the substrate and acts as a conductive layer. The conductive means extends between the surfaces of the substrate to operatively connect the antenna to the RFID chip and power storage means.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: July 30, 2019
    Inventor: Brian K. Blank
  • Patent number: 10332795
    Abstract: It is to provide a manufacturing method of a semiconductor device including the following steps of: preparing a semiconductor substrate having a silicon nitride film on the rear surface; forming an interlayer insulating film having a via hole on the main surface of the semiconductor substrate; and forming a via-fill selectively within the via hole. The method further includes the steps of: performing the wafer rear surface cleaning to expose the surface of the silicon nitride film formed on the rear surface of the semiconductor substrate; and thereafter, forming a photoresist film made of chemical amplification type resist on the interlayer insulating film and the via-fill over the main surface of the semiconductor substrate, in which the semiconductor substrate is stored in an atmosphere with the ammonium ion concentration of 1000 ?g/m3 and less.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: June 25, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Kiyoshi Maeshima, Kotaro Horikoshi, Katsuhiko Hotta, Toshiyuki Takahashi, Hironori Ochi, Kenichi Shoji
  • Patent number: 10249515
    Abstract: Electronic device package technology is disclosed. In one example, an electronic device package can include a substrate, an electronic component disposed on the substrate and electrically coupled to the substrate, and an underfill material disposed at least partially between the electronic component and the substrate. A lateral portion of the underfill material can comprises a lateral surface extending away from the substrate and a meniscus surface extending between the lateral surface and the electronic component.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: April 2, 2019
    Assignee: Intel Corporation
    Inventors: Jimin Yao, Eric Li, Shawna Liff
  • Patent number: 10204876
    Abstract: A device and fabrication techniques are described that employ wafer-level packaging techniques for fabricating semiconductor devices that include a pad defined contact. In implementations, the wafer-level package device that employs the techniques of the present disclosure includes a substrate, a passivation layer, a top metal contact pad, a thin film with a via formed therein, a redistribution layer structure configured to contact the top metal contact pad, and a dielectric layer on the thin film and the redistribution layer structure. In implementations, a process for fabricating the wafer-level package device that employs the techniques of the present disclosure includes processing a substrate, forming a passivation layer, depositing a top metal contact pad, forming a thin film with a via formed therein, forming a redistribution layer structure in the via formed in the thin film, and forming a dielectric layer on the thin film and the redistribution layer structure.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: February 12, 2019
    Assignee: MAXIM INTEGRATED PRODUCTS, INC.
    Inventors: Tiao Zhou, Ricky Agrawal, Abhishek Choudhury
  • Patent number: 10163820
    Abstract: A method may include providing a chip carrier having a chip supporting region to support a chip, and a chip contacting region having at least one contact pad, the chip carrier being thinner in the chip contacting region such that a first thickness of the chip carrier at the at least one contact pad is smaller than a second thickness of the chip carrier in the chip supporting region. A disposing of the chip, having at least one contact protrusion, over the chip carrier, such that the at least one contact protrusion is arranged over the at least one contact pad may be included. In addition, a pressing of the chip against the chip carrier such that the at least one contact protrusion extends at least partially into the chip contacting region and is electrically contacted to the at least one contact pad may be included.
    Type: Grant
    Filed: October 18, 2017
    Date of Patent: December 25, 2018
    Assignee: Infineon Technologies AG
    Inventors: Frank Pueschner, Jens Pohl
  • Patent number: 10163762
    Abstract: A semiconductor assembly includes a semiconductor die comprising lower and upper electrical contacts. A lead frame having a lower die pad is electrically and mechanically connected to the lower electrical contact of the die. An upper conductive member has a first portion electrically and mechanically connected to the upper electrical contact of the die. A lead terminal has a surface portion electrically and mechanically connected to a second portion of the conductive member. The surface portion of the lead terminal and/or the second portion of the conductive member has a series of grooves disposed therein. Packaging material encapsulates the semiconductor die, at least a portion of the lead frame, at least a portion of the upper conducive member and at least a portion of the lead terminal.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: December 25, 2018
    Assignee: VISHAY GENERAL SEMICONDUCTOR LLC
    Inventors: Hui-Ying Ding, Pengnian Wang, Tao Yu, Jun-Feng Liu, Jun-Kai Bai, Chih-Ping Peng
  • Patent number: 10134661
    Abstract: A semiconductor device comprises a first metal lead frame portion with a chip mounting surface, a second metal lead frame portion, and a semiconductor chip with a first surface facing and attached to the chip mounting surface of the first metal lead frame part and a second surface facing away from the chip mounting surface of the first metal lead frame part. A connector portion is electrical connected to the second metal lead frame portion and is attached to the second surface of the semiconductor chip. The connector portion covers the entirety of a planar area of the semiconductor chip when viewed along a direction orthogonal to second surface of the semiconductor chip.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: November 20, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Araki, Shinichi Kouyama, Kazumi Ootani
  • Patent number: 10128221
    Abstract: A package assembly and a method for manufacturing the same are disclosed. The package assembly includes a leadframe having at least two groups of leads and a plurality of electronic devices arranged in at least two levels. Each group of leads is electrically coupled to a respective level of electronic devices. The package assembly further includes an interconnect for coupling one or more leads of one group of leads to one or more leads of another group of leads. The package assembly results in increased packaging density, less usage of bonding wires in the package assembly, improves reliability, and prevents possible interference.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: November 13, 2018
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD.
    Inventors: Xiaochun Tan, Jiaming Ye
  • Patent number: 10115649
    Abstract: A semiconductor device encompasses a connecting base including a semiconductor substrate and a surface insulating-film on the semiconductor substrate, a passivation film covering the surface insulating-film and surface electrode on the surface insulating-film, establishing a groove that exposes a central part of the surface electrode, a barrier-metal film spanning from the bottom of the groove to an upper face of the passivation film, and micro-bumps arranged on the barrier-metal film located on the passivation film.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: October 30, 2018
    Assignee: TOHOKU-MICROTEC CO., LTD.
    Inventor: Makoto Motoyoshi
  • Patent number: 10068780
    Abstract: A semiconductor component includes a semiconductor chip including a first semiconductor body comprising silicon and a second semiconductor body attached to an upper side of the first semiconductor body and comprising a III-nitride, and a lead-frame connected with the first semiconductor body. A thickness ratio between a thickness of the semiconductor chip and a thickness of the lead-frame is smaller than 1.3 or larger than 1.9.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: September 4, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Prechtl, Oliver Haeberlen, Balamurugan Karunamurthy
  • Patent number: 10011098
    Abstract: A 4D device comprises a 2D multi-core logic and a 3D memory stack connected through the memory stack sidewall using a fine pitch T&J connection. The 3D memory in the stack is thinned from the original wafer thickness to no remaining Si. A tounge and groove device at the memory wafer top and bottom surfaces allows an accurate stack alignment. The memory stack also has micro-channels on the backside to allow fluid cooling. The memory stack is further diced at the fixed clock-cycle distance and is flipped on its side and re-assembled on to a template into a pseudo-wafer format. The top side wall of the assembly is polished and built with BEOL to fan-out and use the T&J fine pitch connection to join to the 2D logic wafer. The other side of the memory stack is polished, fanned-out, and bumped with C4 solder. The invention also comprises a process for manufacturing the device.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: July 3, 2018
    Assignee: International Business Machines Corporation
    Inventors: Roy R. Yu, Wilfried Haensch
  • Patent number: 10008462
    Abstract: A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: June 26, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-kyoung Seo, Tae-je Cho, Yong-hwan Kwon, Hyung-gil Baek, Hyun-soo Chung, Seung-kwan Ryu, Myeong-soon Park
  • Patent number: 9997645
    Abstract: A package for an optical sensor device has a double-molded structure in which a first resin molded portion and a second resin molded portion are integrated. The first resin molded portion has a structure in which peripheries of a die pad portion on which an optical sensor element is mounted and a part of each of a plurality of leads are molded with a resin so as to be integrated, the part of each of the plurality of leads being embedded in and completely surrounded by the first resin molded portion. The second resin molded portion is molded over at least a portion of the first resin molded portion to form an outer shape of the package and has embedded therein and completely surrounds a part of each of the plurality of leads. A glass substrate having a filter function is bonded to an upper surface of the resin molded portions to form a cavity in which is mounted the optical sensor element.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: June 12, 2018
    Assignee: SII Semiconductor Corporation
    Inventor: Koji Tsukagoshi
  • Patent number: 9997446
    Abstract: A semiconductor package includes a substrate, a rewiring layer, a plurality of semiconductor chip stack structures, and a second semiconductor chip. The rewiring layer is disposed on an upper surface of the substrate. The rewiring layer includes a concave portion. The semiconductor chip stack structures include a plurality of first semiconductor chips. The first semiconductor chips are disposed on the rewiring layer. The first semiconductor chips are spaced apart from each other in a horizontal direction. The second semiconductor chip is disposed within the concave portion. The second semiconductor chip is configured to electrically connect each of the plurality of semiconductor chip stack structures to each other.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: June 12, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ji-Hwang Kim, Jong-Bo Shim, Cha-Jea Jo, Won-Il Lee
  • Patent number: 9984996
    Abstract: The present invention discloses a three-dimensional package structure which can achieve a relatively high utilization of an internal space thereof, so that a size of electronic package structure can be reduced. The three-dimensional package structure comprises a first electronic component, a plurality of second electronic components and a plurality of conductive patterns. The first electronic component has a top surface and a bottom surface. The plurality of second electronic components are disposed over the top surface of the first electronic component. The plurality of conductive patterns are disposed over the plurality of second electronic components to electrically connect the plurality of second electronic components and the first electronic component.
    Type: Grant
    Filed: November 10, 2014
    Date of Patent: May 29, 2018
    Assignee: CYNTEC CO., LTD.
    Inventors: Bau-Ru Lu, Ming-Chia Wu, Shao Wei Lu
  • Patent number: 9984769
    Abstract: An error check and correction method of a 3D memory include a) storing check bits, which is used for error check and correction of an upper memory among the plurality of the memory layers, in one or more of spare cell arrays of a lower memory layer stacked below the upper memory layer and the upper memory layer; and b) performing error check and correction of the upper memory layer by using the stored check bits, wherein in the 3D memory, there are stacked a plurality of memory layers comprising a memory cell array with a matrix structure consisting of memory cells and a spare cell array with a matrix structure consisting of spare memory cells for replacing a fault memory cell, in which a fault occurs, and the 3D memory comprises a master layer for controlling the plurality of the memory layers.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 29, 2018
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Joon-sung Yang, Hyunseung Han
  • Patent number: 9966518
    Abstract: A package substrate includes: an insulating substrate, a first and a second soldering pads spacedly disposed on a first surface of the insulating substrate, a first and a second electrodes spacedly disposed on an opposite second surface of the insulting substrate. The first and the second soldering pads are electrically connected to the first and the second electrodes respectively. Moreover, a first and a second grooves are defined on the first surface of the insulating substrate, the first and the second grooves are spaced from each other and disposed between the first and the second soldering pads. The invention further provides a LED flip chip package structure including the package substrate, a LED flip chip and fluorescent glue. The invention adds the grooves in the spacing between the soldering pads as a buffer space for melted solder flowing during reflow soldering process and therefore can relieve short-circuit phenomenon.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: May 8, 2018
    Assignee: KAISTAR LIGHTING (XIAMEN) CO., LTD.
    Inventors: Yi Ching Su, Yung-Chih Chen, Steve Meng-Yuan Hong
  • Patent number: 9929113
    Abstract: A semiconductor device structure and a method for manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device structure (e.g., a sensor device structure), and method for manufacturing thereof, that comprises a three-dimensional package structure free of wire bonds, through silicon vias, and/or flip-chip bonding.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: March 27, 2018
    Assignee: AMKOR TECHNOLOGY, INC.
    Inventors: Jong Sik Paek, No Sun Park
  • Patent number: 9922916
    Abstract: Electronic assemblies and methods including the formation of interconnect structures are described. In one embodiment an apparatus includes semiconductor die and a first metal bump on the die, the first metal bump including a surface having a first part and a second part. The apparatus also includes a solder resistant coating covering the first part of the surface and leaving the second part of the surface uncovered. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: March 20, 2018
    Assignee: INTEL CORPORATION
    Inventors: Sanka Ganesan, Zhiguo Qian, Robert L. Sankman, Krishna Srinivasan, Zhaohui Zhu
  • Patent number: 9864943
    Abstract: A wireless communication device includes a wireless IC device, a multilayer substrate including a stack of a plurality of dielectric layers, a resonant circuit that is connected to the wireless IC device and that includes a capacitance element provided in the multilayer substrate and an inductance element provided outside the multilayer substrate, and a radiation conductor connected to the resonant circuit.
    Type: Grant
    Filed: September 16, 2014
    Date of Patent: January 9, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Yuya Dokai
  • Patent number: 9847279
    Abstract: The present invention relates to a structure of a composite lead frame generally having a die bonding layer and a solder layer and may further have an cohesive layer between the die bonding layer and the solder layer. The die bonding layer is made of flex substrate and the solder layer is made of traditional lead frame. Thus, the composite lead frame structure is suitable for the flip chip or wire bonding packaging process of LED and also suitable for semiconductor IC packaging process. It is good in electric and heat conductivity, and also with higher mechanical strength, resulting high pin counts and minimization of resulted IC.
    Type: Grant
    Filed: August 8, 2014
    Date of Patent: December 19, 2017
    Assignee: CHANG WAH TECHNOLOGY CO., LTD.
    Inventor: Chia-Neng Huang
  • Patent number: 9847235
    Abstract: A carrier substrate having a plurality of receptacles each for receiving and carrying a semiconductor chip is provided. Semiconductor chips are arranged in the receptacles, and metal is plated in the receptacles to form a metal structure on and in contact with the semiconductor chips. The carrier substrate is cut to form separate semiconductor devices.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: December 19, 2017
    Assignee: Infineon Technologies AG
    Inventors: Carsten von Koblinski, Ulrike Fastner, Andre Brockmeier, Peter Zorn
  • Patent number: 9829786
    Abstract: A phase shift mask blank includes a transparent substrate, a phase shift layer, a first hard mask layer and an opaque layer. The transparent substrate is disposed on the transparent substrate. The first hard mask layer is disposed on the phase shift layer. The phase shift layer has an etching selectivity with respect to the first hard mask layer. The opaque layer is disposed on the first hard mask layer.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: November 28, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Lang Chen, Tzung-Shiun Liu
  • Patent number: 9831159
    Abstract: In one implementation, a semiconductor package includes a control transistor and a sync transistor of a power converter switching stage attached over a first patterned conductive carrier, as well as a magnetic material situated over leads of the first patterned conductive carrier. The semiconductor package also includes a second patterned conductive carrier attached over the first patterned conductive carrier, the control and sync transistors, and the magnetic material. Leads of the second patterned conductive carrier overlie the magnetic material and are coupled to the leads of the first patterned conductive carrier so as to form windings of an output inductor for the power converter switching stage, the output inductor being integrated into the semiconductor package.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: November 28, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Eung San Cho, Darryl Galipeau, Danny Clavette
  • Patent number: 9818732
    Abstract: Chip-on-film packages and device assemblies including the same may be provided. The device assembly includes a film package including a semiconductor chip, a panel substrate connected to one end of the film package, a display panel disposed on the panel substrate, and a controlling part connected to another end of the film package. The film package includes a film substrate, a first wire disposed on a top surface of the film substrate, and a second wire disposed on a bottom surface of the film substrate.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: November 14, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Min Jung, Sang-Uk Han, KwanJai Lee, KyongSoon Cho, Jeong-Kyu Ha
  • Patent number: 9786521
    Abstract: A chip package method can include: forming bonding pins on a first region of a first surface of a carrier; forming an insulating layer on an inactive face of a chip, where the inactive face of the chip is opposite to an active face of the chip; pasting the chip on a second region of the first surface of the carrier by the insulating layer; electrically coupling electrodes on the active face of the chip to the bonding pins by conductive wires; forming an enclosure to cover the chip and the bonding pins by a molding process; and peeling away the carrier from the enclosure to expose the bonding pins and the insulating layer on a surface of the enclosure.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: October 10, 2017
    Assignee: Silergy Semiconductor Technology (Hangzhou) LTD
    Inventor: Xiaochun Tan
  • Patent number: 9761654
    Abstract: A display device includes a first substrate arranged with a plurality of pixels on a first surface, the plurality of pixels having a display element including a transistor, and a first wiring connected to the transistor, a through electrode arranged in a first contact hole reaching the first wiring from a second surface facing the first surface of the first substrate, a second wiring connected with the through electrode, a first insulation film arranged covering the second wiring on the second surface of the first substrate, and a terminal connected with a second wiring via a second contact hole arranged in the first insulation film.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: September 12, 2017
    Assignee: Japan Display Inc.
    Inventors: Kazuto Tsuruoka, Norio Oku
  • Patent number: 9711475
    Abstract: A method of forming a chip package includes providing a chip with a plurality of first bumps, wherein the plurality of first bumps has a first height. The method further includes providing a substrate with a plurality of second bumps, wherein the plurality of second bumps has a second height. The method further includes bonding the plurality of first bumps to the plurality of second bumps to form a first bump structure of the chip package, wherein the first bump structure has a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Cheng-Lin Huang
  • Patent number: 9705191
    Abstract: A device according to claim 6, characterised in that the interrupting zone is positioned outside the switch zone in which two wires (54, 56) of a circuit are so arranged as to cooperate with the switch are positioned.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: July 11, 2017
    Assignee: GEMALTO SA
    Inventors: Nizar Lahoui, Frédérick Seban, Jean-Christophe Fidalgo, Jean-Luc Meridiano
  • Patent number: 9653531
    Abstract: A method of manufacturing a package may include: providing a first device having a first redistribution layer (RDL) and an insulator layer disposed over the first RDL; and forming a first micro-bump line over the insulator layer of the first device. The first micro-bump line may extend laterally over a surface of the insulator layer facing away from the first RDL, and a first inductor of the package comprises the first RDL and the first micro-bump line.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Min-Chie Jeng, Hsien-Pin Hu, Tzuan-Horng Liu, Chin-Wei Kuo, Chung-Yu Lu, Yu-Ling Lin
  • Patent number: 9620439
    Abstract: A power package includes a heat tab extending from a die pad exposed on the underside of the package, which facilitates the removal of heat from the die to the PCB or other surface on which the package is mounted. The heat tab has a bottom surface coplanar with the flat bottom surface of the die pad and bottom surface of a lead. The lead includes a horizontal foot segment, a vertical columnar segment, and a horizontal cantilever segment facing the die pad. The heat tab may also have a foot. A die containing a power device is mounted on a top surface of the die pad and may be electrically connected to the lead using a bonding wire or clip. The die may be mounted on the die pad with an electrically conductive material, and the package may also include a lead that extends from the die pad and is thus electrically tied to the bottom of the die.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: April 11, 2017
    Assignee: Adventive IPBank
    Inventors: Richard K. Williams, Keng Hung Lin
  • Patent number: 9607941
    Abstract: A method for fabricating a conductive via structure is provided, which includes the steps of: forming in an encapsulant a plurality of openings penetrating therethrough; forming a dielectric layer on the encapsulant and in the openings of the encapsulant; forming a plurality of vias in the dielectric layer in the openings of the encapsulant; and forming a conductive material in the vias to thereby form conductive vias. Therefore, by filling the openings having rough wall surfaces with the dielectric layer so as to form the vias having even wall surfaces, the present invention improves the quality of the conductive vias.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: March 28, 2017
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Yan-Heng Chen, Chun-Tang Lin, Chieh-Yuan Chi, Mu-Hsuan Chan
  • Patent number: 9589936
    Abstract: Fanout wafer level packages (FOWLPs) and methods of formation are described. In an embodiment, a package includes a first routing layer, a first die on a top side of the first routing layer, and a first molding compound encapsulating the first die on the first routing layer. A first plurality of conductive pillars extends from a bottom side of the first routing layer. A second die is on a top side of a second routing layer, and the first plurality of conductive pillars is on the top side of the routing layer. A second molding compound encapsulates the first molding compound, the first routing layer, the first plurality of conductive pillars, and the second die on the second routing layer. In an embodiment, a plurality of conductive bumps (e.g. solder balls) extends from a bottom side of the second routing layer.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: March 7, 2017
    Assignee: Apple Inc.
    Inventors: Jun Zhai, Kunzhong Hu, Flynn P. Carson
  • Patent number: 9553226
    Abstract: A method for manufacturing a solar cell module includes a cell forming operation of forming a plurality of first and second electrodes on a back surface of a semiconductor substrate to form each a plurality of solar cells, and a tabbing operation including at least one of a connection operation of performing a thermal process to respectively connect a first conductive line and a second conductive line to the first electrodes and the second electrodes of each solar cell using a conductive adhesive and an optional string forming operation of performing a thermal process to connect the first conductive line included in one solar cell and the second conductive line included in other solar cell adjacent to the one solar cell to an interconnect. The tabbing operation includes at least two thermal processes each having a different maximum temperature.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: January 24, 2017
    Assignee: LG ELECTRONICS INC.
    Inventors: Bojoong Kim, Minpyo Kim, Daehee Jang, Hyeyoung Yang
  • Patent number: 9548533
    Abstract: A magnetic field focusing assembly includes a magnetic field generating device configured to generate a magnetic field, and a split ring resonator assembly configured to be magnetically coupled to the magnetic field generating device and configured to focus the magnetic field produced by the magnetic field generating device.
    Type: Grant
    Filed: November 30, 2015
    Date of Patent: January 17, 2017
    Assignee: DEKA Products Limited Partnership
    Inventor: David Blumberg, Jr.
  • Patent number: 9508673
    Abstract: A wire bonding method includes the following steps. First, a substrate including at least one metal finger is provided. Next, a first chip including at least one first boding pad is disposed on the substrate. Next, a metal ball bump is formed on the corresponding metal finger. Next, a first wire is formed from the metal ball bump toward the corresponding first boding pad. Next, a first free air ball is formed on the first wire by electronic flame-off process. Then, the first free air ball connected to the first wire is pressed on the corresponding first boding pad, such that the first wire is located between the first free air ball and the corresponding first boding pad.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: November 29, 2016
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Po-Chun Lin
  • Patent number: 9508632
    Abstract: A semiconductor structure includes a lead frame having a flag and a plurality of leads, a semiconductor die attached to a first major surface of the flag, and a plurality of re-routed lead fingers attached to the lead frame. The plurality of leads has a first pitch. The first end of each re-routed lead finger is attached to a lead of the plurality of leads. Each re-routed lead finger extends over the semiconductor die such that a second end of each re-routed lead finger is over and spaced apart from the flag of the lead frame. The second ends of the plurality of re-routed lead fingers has a second pitch different from the first pitch.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: November 29, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Navas Khan Oratti Kalandar, Nishant Lakhera, Varughese Mathew, Akhilesh K. Singh
  • Patent number: 9472538
    Abstract: Fixing a semiconductor element to a substrate, electrically connecting signal and main terminals to the semiconductor element, a terminal aggregate includes a frame portion, the signal terminal, the main terminal, which has a larger width than the signal terminal, and a dummy terminal, and forming a to-be-encapsulated body in which the substrate, the semiconductor element, and the terminal aggregate are integrated, mounting the to-be-encapsulated body on a lower mold half such that a plurality of blocks formed in the lower mold half are meshed with the signal, main, and dummy terminals with no space left therebetween after the mounting, placing a bottom surface of an upper mold half on top surfaces of the plurality of blocks, and top surfaces of the signal, main, and dummy terminals to form a cavity for the substrate and the semiconductor element, and performing molding by injecting mold resin into the cavity are included.
    Type: Grant
    Filed: July 4, 2013
    Date of Patent: October 18, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Seiichiro Inokuchi, Mitsunori Aiko, Shintaro Araki, Natsuki Tsuji
  • Patent number: 9474191
    Abstract: Each of a plurality of power semiconductor module includes a can-type cooling case that is formed with a plate spring portion that generates compressive stress in the semiconductor circuit unit, an adjustment portion that is deformed to adjust elastic deformation of the plate spring portion, and a sidewall portion to which the plate spring portion and the adjustment portion are joined.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: October 18, 2016
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Masato Higuma, Toshifumi Sagawa, Takahiro Shimura, Hideto Yoshinari
  • Patent number: 9337095
    Abstract: A method of manufacturing a leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The IC chip, the electrical contacts, and a portion of the metal leadframe are covered with an encapsulation compound, with portions of the electrical contacts exposed on a bottom surface of the encapsulation compound. The electrical contacts of the IC package having metal traces connecting bonding areas on a top surface thereof and contact areas on a bottom surface thereof, wherein at least some of the bonding areas are laterally disposed from the contact areas connected thereto.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: May 10, 2016
    Assignee: Kaixin, Inc.
    Inventor: Tung Lok Li
  • Patent number: 9324017
    Abstract: The invention relates to a chip module for an RFID system, in particular for an RFID-label, a coupling label for use in an RFID-label, an RFID-Inlay for an RFID-label, and an RFID label produced using an RFID inlay on a strip-shaped backing material (5, 8), in particular a backing film; an RFID chip (3) and a coupling antenna (4) that is electrically, in particular galvanically, connected to the RFID-chip (3), are arranged on the strip-shaped backing material.
    Type: Grant
    Filed: October 16, 2007
    Date of Patent: April 26, 2016
    Assignee: BIELOMATIKLEUZE GMBH & CO. KG
    Inventors: Martin Bohn, Harry Nitschko, Kai Schaffrath
  • Patent number: 9299631
    Abstract: According to example embodiments, a stack-type semiconductor package includes a lower semiconductor package, an upper semiconductor package, connection pads, and a metal layer pattern. The lower semiconductor package includes a lower semiconductor chip on a top surface of a lower package substrate, lower lands on the lower package substrate, and an encapsulant on the top surface of the lower package substrate. The encapsulant defines via holes that expose the lower lands. The upper semiconductor package is on the encapsulant. Upper solder balls are connected to a bottom surface of the upper semiconductor package. The connection pads are on the via holes and the encapsulant. The connection pads electrically connect the lower semiconductor package to the upper semiconductor package. The metal layer pattern is between the lower package substrate and the upper semiconductor package. The metal layer pattern surrounds the connection pads and is isolated from the connection pads.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: March 29, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ae-Nee Jang, Young-Lyong Kim