Abstract: The present invention relates to a structure of a composite lead frame generally having a die bonding layer and a solder layer and may further have an cohesive layer between the die bonding layer and the solder layer. The die bonding layer is made of flex substrate and the solder layer is made of traditional lead frame. Thus, the composite lead frame structure is suitable for the flip chip or wire bonding packaging process of LED and also suitable for semiconductor IC packaging process. It is good in electric and heat conductivity, and also with higher mechanical strength, resulting high pin counts and minimization of resulted IC.

Abstract: In one implementation, a semiconductor package includes a control transistor and a sync transistor of a power converter switching stage attached over a first patterned conductive carrier, as well as a magnetic material situated over leads of the first patterned conductive carrier. The semiconductor package also includes a second patterned conductive carrier attached over the first patterned conductive carrier, the control and sync transistors, and the magnetic material. Leads of the second patterned conductive carrier overlie the magnetic material and are coupled to the leads of the first patterned conductive carrier so as to form windings of an output inductor for the power converter switching stage, the output inductor being integrated into the semiconductor package.

Abstract: A phase shift mask blank includes a transparent substrate, a phase shift layer, a first hard mask layer and an opaque layer. The transparent substrate is disposed on the transparent substrate. The first hard mask layer is disposed on the phase shift layer. The phase shift layer has an etching selectivity with respect to the first hard mask layer. The opaque layer is disposed on the first hard mask layer.

Abstract: Chip-on-film packages and device assemblies including the same may be provided. The device assembly includes a film package including a semiconductor chip, a panel substrate connected to one end of the film package, a display panel disposed on the panel substrate, and a controlling part connected to another end of the film package. The film package includes a film substrate, a first wire disposed on a top surface of the film substrate, and a second wire disposed on a bottom surface of the film substrate.

Abstract: A chip package method can include: forming bonding pins on a first region of a first surface of a carrier; forming an insulating layer on an inactive face of a chip, where the inactive face of the chip is opposite to an active face of the chip; pasting the chip on a second region of the first surface of the carrier by the insulating layer; electrically coupling electrodes on the active face of the chip to the bonding pins by conductive wires; forming an enclosure to cover the chip and the bonding pins by a molding process; and peeling away the carrier from the enclosure to expose the bonding pins and the insulating layer on a surface of the enclosure.

Abstract: A display device includes a first substrate arranged with a plurality of pixels on a first surface, the plurality of pixels having a display element including a transistor, and a first wiring connected to the transistor, a through electrode arranged in a first contact hole reaching the first wiring from a second surface facing the first surface of the first substrate, a second wiring connected with the through electrode, a first insulation film arranged covering the second wiring on the second surface of the first substrate, and a terminal connected with a second wiring via a second contact hole arranged in the first insulation film.

Abstract: A method of forming a chip package includes providing a chip with a plurality of first bumps, wherein the plurality of first bumps has a first height. The method further includes providing a substrate with a plurality of second bumps, wherein the plurality of second bumps has a second height. The method further includes bonding the plurality of first bumps to the plurality of second bumps to form a first bump structure of the chip package, wherein the first bump structure has a standoff, wherein a ratio of a sum of the first height and the second height to the standoff is equal to or greater than about 0.6 and less than 1.

Abstract: A device according to claim 6, characterised in that the interrupting zone is positioned outside the switch zone in which two wires (54, 56) of a circuit are so arranged as to cooperate with the switch are positioned.

Abstract: A method of manufacturing a package may include: providing a first device having a first redistribution layer (RDL) and an insulator layer disposed over the first RDL; and forming a first micro-bump line over the insulator layer of the first device. The first micro-bump line may extend laterally over a surface of the insulator layer facing away from the first RDL, and a first inductor of the package comprises the first RDL and the first micro-bump line.

Abstract: A power package includes a heat tab extending from a die pad exposed on the underside of the package, which facilitates the removal of heat from the die to the PCB or other surface on which the package is mounted. The heat tab has a bottom surface coplanar with the flat bottom surface of the die pad and bottom surface of a lead. The lead includes a horizontal foot segment, a vertical columnar segment, and a horizontal cantilever segment facing the die pad. The heat tab may also have a foot. A die containing a power device is mounted on a top surface of the die pad and may be electrically connected to the lead using a bonding wire or clip. The die may be mounted on the die pad with an electrically conductive material, and the package may also include a lead that extends from the die pad and is thus electrically tied to the bottom of the die.

Abstract: A method for fabricating a conductive via structure is provided, which includes the steps of: forming in an encapsulant a plurality of openings penetrating therethrough; forming a dielectric layer on the encapsulant and in the openings of the encapsulant; forming a plurality of vias in the dielectric layer in the openings of the encapsulant; and forming a conductive material in the vias to thereby form conductive vias. Therefore, by filling the openings having rough wall surfaces with the dielectric layer so as to form the vias having even wall surfaces, the present invention improves the quality of the conductive vias.

Abstract: Fanout wafer level packages (FOWLPs) and methods of formation are described. In an embodiment, a package includes a first routing layer, a first die on a top side of the first routing layer, and a first molding compound encapsulating the first die on the first routing layer. A first plurality of conductive pillars extends from a bottom side of the first routing layer. A second die is on a top side of a second routing layer, and the first plurality of conductive pillars is on the top side of the routing layer. A second molding compound encapsulates the first molding compound, the first routing layer, the first plurality of conductive pillars, and the second die on the second routing layer. In an embodiment, a plurality of conductive bumps (e.g. solder balls) extends from a bottom side of the second routing layer.

Abstract: A method for manufacturing a solar cell module includes a cell forming operation of forming a plurality of first and second electrodes on a back surface of a semiconductor substrate to form each a plurality of solar cells, and a tabbing operation including at least one of a connection operation of performing a thermal process to respectively connect a first conductive line and a second conductive line to the first electrodes and the second electrodes of each solar cell using a conductive adhesive and an optional string forming operation of performing a thermal process to connect the first conductive line included in one solar cell and the second conductive line included in other solar cell adjacent to the one solar cell to an interconnect. The tabbing operation includes at least two thermal processes each having a different maximum temperature.

Abstract: A magnetic field focusing assembly includes a magnetic field generating device configured to generate a magnetic field, and a split ring resonator assembly configured to be magnetically coupled to the magnetic field generating device and configured to focus the magnetic field produced by the magnetic field generating device.

Abstract: A wire bonding method includes the following steps. First, a substrate including at least one metal finger is provided. Next, a first chip including at least one first boding pad is disposed on the substrate. Next, a metal ball bump is formed on the corresponding metal finger. Next, a first wire is formed from the metal ball bump toward the corresponding first boding pad. Next, a first free air ball is formed on the first wire by electronic flame-off process. Then, the first free air ball connected to the first wire is pressed on the corresponding first boding pad, such that the first wire is located between the first free air ball and the corresponding first boding pad.

Abstract: A semiconductor structure includes a lead frame having a flag and a plurality of leads, a semiconductor die attached to a first major surface of the flag, and a plurality of re-routed lead fingers attached to the lead frame. The plurality of leads has a first pitch. The first end of each re-routed lead finger is attached to a lead of the plurality of leads. Each re-routed lead finger extends over the semiconductor die such that a second end of each re-routed lead finger is over and spaced apart from the flag of the lead frame. The second ends of the plurality of re-routed lead fingers has a second pitch different from the first pitch.

Abstract: Each of a plurality of power semiconductor module includes a can-type cooling case that is formed with a plate spring portion that generates compressive stress in the semiconductor circuit unit, an adjustment portion that is deformed to adjust elastic deformation of the plate spring portion, and a sidewall portion to which the plate spring portion and the adjustment portion are joined.

Abstract: Fixing a semiconductor element to a substrate, electrically connecting signal and main terminals to the semiconductor element, a terminal aggregate includes a frame portion, the signal terminal, the main terminal, which has a larger width than the signal terminal, and a dummy terminal, and forming a to-be-encapsulated body in which the substrate, the semiconductor element, and the terminal aggregate are integrated, mounting the to-be-encapsulated body on a lower mold half such that a plurality of blocks formed in the lower mold half are meshed with the signal, main, and dummy terminals with no space left therebetween after the mounting, placing a bottom surface of an upper mold half on top surfaces of the plurality of blocks, and top surfaces of the signal, main, and dummy terminals to form a cavity for the substrate and the semiconductor element, and performing molding by injecting mold resin into the cavity are included.

Abstract: A method of manufacturing a leadless integrated circuit (IC) package comprising an IC chip mounted on a metal leadframe and a plurality of electrical contacts electrically coupled to the IC chip. The IC chip, the electrical contacts, and a portion of the metal leadframe are covered with an encapsulation compound, with portions of the electrical contacts exposed on a bottom surface of the encapsulation compound. The electrical contacts of the IC package having metal traces connecting bonding areas on a top surface thereof and contact areas on a bottom surface thereof, wherein at least some of the bonding areas are laterally disposed from the contact areas connected thereto.

Abstract: The invention relates to a chip module for an RFID system, in particular for an RFID-label, a coupling label for use in an RFID-label, an RFID-Inlay for an RFID-label, and an RFID label produced using an RFID inlay on a strip-shaped backing material (5, 8), in particular a backing film; an RFID chip (3) and a coupling antenna (4) that is electrically, in particular galvanically, connected to the RFID-chip (3), are arranged on the strip-shaped backing material.

Abstract: According to example embodiments, a stack-type semiconductor package includes a lower semiconductor package, an upper semiconductor package, connection pads, and a metal layer pattern. The lower semiconductor package includes a lower semiconductor chip on a top surface of a lower package substrate, lower lands on the lower package substrate, and an encapsulant on the top surface of the lower package substrate. The encapsulant defines via holes that expose the lower lands. The upper semiconductor package is on the encapsulant. Upper solder balls are connected to a bottom surface of the upper semiconductor package. The connection pads are on the via holes and the encapsulant. The connection pads electrically connect the lower semiconductor package to the upper semiconductor package. The metal layer pattern is between the lower package substrate and the upper semiconductor package. The metal layer pattern surrounds the connection pads and is isolated from the connection pads.

Abstract: According to one embodiment, the connector has a first portion and a second portion. The first portion is provided on the second surface of the semiconductor chip and bonded to the second electrode. The first portion has a first bonding surface bonded to the second electrode of the semiconductor chip, and a heat dissipation surface opposite the first bonding surface and exposed from the resin. The second portion protrudes from the first portion toward the second lead frame side and thinner than the first portion. The second portion has a second bonding surface bonded to the second lead frame and a level difference portion provided near the second bonding surface at the first portion side.

Abstract: A semiconductor module is configured such that heat radiation substrates are connected to lead frames and semiconductor chips are directly connected to the lead frames, so that the semiconductor chips are not connected to the lead frames through conductive portions of the heat radiation substrates. Therefore, the conductive portion can have a solid shape without being divided. As such, an occurrence of curving of the heat radiation substrates is suppressed when a temperature is reduced from a high temperature to a room temperature after resin-sealing at the high temperature or the like. Therefore, connection between the semiconductor chip and the lead frames and connection between the lead frames and the heat radiation substrates enhance.

Abstract: An assembly having a substrate and at least one component fastened thereon by sintering using a sintering agent, in particular sintering paste. The sintering agent is situated in a recess of the substrate that accommodates at least some areas of the component. A method for producing an assembly having a substrate and at least one component fastened thereon by sintering using a sintering agent, in particular sintering paste. The sintering agent is brought into a recess of the substrate that accommodates at least some areas of the component.

Abstract: Provided is an electronic device whereby it is possible to suppress a decline in heat-dissipating properties. This liquid crystal display device (electronic device) (1) is provided with a semiconductor element (6a, 6b), a substrate (7) to which the semiconductor element is attached, and a chassis (5) disposed in opposition to the substrate and furnished with a rib (11, 12) that protrudes towards the semiconductor element side. The rib includes a contact part (11a, 12a) for contacting the semiconductor element. A pressing member (9) for inducing the semiconductor element into contact with the contact part is furnished at least at a position corresponding to the center part (7c) of the substrate.

Abstract: Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described.

Abstract: Chip-on-film packages and device assemblies including the same may be provided. The device assembly includes a film package including a semiconductor chip, a panel substrate connected to one end of the film package, a display panel disposed on the panel substrate, and a controlling part connected to another end of the film package. The film package includes a film substrate, a first wire disposed on a top surface of the film substrate, and a second wire disposed on a bottom surface of the film substrate.

Abstract: Roughly described, an integrated circuit device has a conductor extending entirely through the substrate, connected on one end to the substrate topside surface and on the other end to the substrate backside surface. In various embodiments the conductor is insulated from all RDL conductors on the backside of the substrate, and/or is insulated from all conductors and device features on any below-adjacent chip in a 3D integrated circuit structure. Methods of fabrication are also described.

Abstract: A semiconductor system includes a semiconductor chip; a penetrating electrode, which is formed to penetrate the semiconductor chip; two or more metals, which are formed in the upper portion of the penetrating electrode; a bump, which is formed to contact the upper portions of the metals and supplies a data signal inputted from outside to the metals; a detection block suitable for detecting whether or not the bump is coupled with the metals by comparing voltage levels of the metals with each other and generating a decision signal; and a signal output block suitable for outputting the decision signal externally.

Abstract: Methods and apparatuses related to packaging a monolithic voltage regulator are disclosed. In one embodiment, an apparatus includes: (i) a monolithic voltage regulator with a transistor arranged as parallel transistor devices; (ii) bumps on the monolithic voltage regulator to form connections to source and drain terminals of the transistor; (iii) a single layer lead frame with a plurality of interleaving lead fingers coupled to the monolithic voltage regulator via the bumps, where the single layer lead frame includes first and second surfaces, where the first surface includes a first pattern to form connections to the bumps, and where the second surface includes a second pattern that is different from the first pattern; and (iv) a flip-chip package encapsulating the monolithic voltage regulator, the bumps, and the single layer lead frame, where the flip-chip package has external connectors of the monolithic voltage regulator at the second surface of the single layer lead frame.

Abstract: The present disclosure relates to a package structure of a lead frame. The package includes a die, a dielectric layer, at least one conducting pillar, at least one lead frame and at least one solder ball. The dielectric layer is disposed on a surface of the die. The at least one conducting pillar penetrates through the dielectric layer and is disposed on the surface. The at least one lead frame is disposed on the dielectric layer and is spaced from the at least one conducting pillar with a gap. The solder ball fills the gap and electrically connects the at least one conducting pillar and the at least one lead frame.

Abstract: In one embodiment, an electronic package structure includes a lead having a first width. An electronic chip having a conductive bump on a major surface, the conductive bump has a second width greater than the first width. The conductive bump is attached to the lead such that a portion of the conductive bump extends to at least partially surround a side surface of the lead. A molding compound resin encapsulates the electronic chip, the conductive bump, and at least a portion of the lead. The lead is configured so strengthen the joining force between the lead and conductive bump.

Abstract: Provided is a semiconductor device in which misalignment between a semiconductor die and a substrate (e.g., a circuit board) can be prevented or substantially reduced when the semiconductor die is attached to the circuit board. In a non-limiting example, the semiconductor device includes: a semiconductor die comprising at least one bump; and a circuit board comprising at least one circuit pattern to which the bump is electrically connected. In a non-limiting example, the circuit board comprises: an insulation layer comprising a center region and peripheral regions around the center region; a plurality of center circuit patterns formed in the center region of the insulation layer; and a plurality of peripheral circuit patterns formed in the peripheral regions of the insulation layer. The center circuit patterns may be formed wider than the peripheral circuit patterns, formed in a zigzag pattern, and/or may be formed in a crossed shape.

Abstract: A trench portion (trench) is formed at each of four corner portions of a chip bonding region having a quadrangular planar shape smaller than an outer-shape size of a die pad included in a semiconductor device. Each trench is formed along a direction of intersecting with a diagonal line which connects between the corner portions where the trench portions are arranged, and both ends of each trench portion are extended to an outside of the chip bonding region. The semiconductor chip is mounted on the chip bonding region so as to interpose a die-bond material. In this manner, peel-off of the die-bond material in a reflow step upon mounting of the semiconductor device on a mounting substrate can be suppressed. Also, even if the peel-off occurs, expansion of the peel-off can be suppressed.

Abstract: Electronic devices including a semiconductor device package, a substrate, and first and second solder joints. The semiconductor device package includes a die pad, leads and enhancement elements surrounding the die pad, a chip electrically connected to the leads, and a package body encapsulating the chip, portions of the leads, and portions of the enhancement elements, but leaving exposed at least a side surface of each enhancement element. Side surfaces of the enhancement elements and the package body are coplanar. The substrate includes first pads corresponding to the leads and second pads corresponding to the enhancement elements. The first solder joints are disposed between the first pads and the leads. The second solder joints are disposed between the second pads and the enhancement elements. The second solder joints contact side surfaces of the enhancement elements. The surface area of the second pads is greater than the surface area of the corresponding enhancement elements.

Abstract: Semiconductor packages having lead frames include a lead frame, which supports a semiconductor chip and is electrically connected to the semiconductor chip by bonding wires, and a molding layer encapsulating the semiconductor chip. The lead frame includes first lead frames extending in a first direction and second lead frames extending in a second direction. The first lead frames may run across the semiconductor chip and support the semiconductor chip and the second lead frames may run across the bottom surface of the semiconductor chip.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a lead-frame having a metal connector mounted thereon and having a peripheral mounting region; forming an insulation cover on the lead-frame and on the metal connector; connecting an integrated circuit die over the insulation cover; forming a top encapsulation on the integrated circuit die with the peripheral mounting region exposed from the top encapsulation; forming a routing layer, having a conductive land, from the lead-frame; and forming a bottom encapsulation partially encapsulating the routing layer and the insulation cover.

Abstract: A power semiconductor device comprises a lead frame unit, a control die, a first MOSFET die and a second MOSFET die, wherein the lead frame unit comprises at least a die paddle for mounting the first and second MOSFET dies, a first pin and a second pin for connecting to top electrodes of the first and second MOSFET dies, a first row of carrier pins and a second row of carrier pins disposed in-line with the first and second pins respectively for the control die to mount thereon.

Abstract: An RFID that performs a wireless communication, including an antenna part (10a) formed by a lead frame (10), a semiconductor device (30) mounted on the lead frame, a first thermoplastic resin (50) configured by performing injection molding on both surfaces of the lead frame so that the semiconductor device is filled, and including a convex portion, and a second thermoplastic resin (56) configured by performing injection molding on both surfaces of the lead frame with reference to a position of the convex portion of the first thermoplastic resin.

Abstract: Disclosed herein are various chip lead frame and packaging structures, and methods of fabrication. In one embodiment, a lead frame can include: (i) a horizontal plate arranged at a bottom of the lead frame, where the horizontal plate is conductive; and (ii) a plurality of conductive bumps arranged on a surface of the horizontal plate, where the plurality of conductive bumps are configured to support and electrically connect to at least one chip. In one embodiment, a method of making the lead frame can include: (i) forming the horizontal plate by a mold; (ii) arranging a mask with a through-hole on the surface of the horizontal plate; (iii) electroplating conducting material on a portion of the horizontal plate that is exposed by the through-hole; and (iv) removing the mask after formation of the plurality of conductive bumps. Also, a package structure can be formed using the lead frame.

Abstract: A semiconductor device housing package includes a base body having, on its upper surface, a mounting region of a semiconductor device; a frame body having a frame-like portion disposed on the upper surface of the base body, surrounding the mounting region, and an opening penetrating through from an inner side of the frame-like portion to an outer side thereof; a flat plate-like insulating member disposed in the opening, extending from an interior of the frame body to an exterior thereof; wiring conductors disposed on an upper surface of the insulating member, extending from the interior of the frame body to the exterior thereof; and a metallic film disposed on a part of the upper surface of the insulating member, the metallic film lying outside the frame body surrounding the wiring conductors.

Abstract: A method and structure for encoding information on an integrated circuit chip. The method includes selecting a set of chip pads of the integrated circuit chip for encoding the information; encoding the information during a wirebonding process, the wirebonding process comprising forming ball bonds on chip pads of the integrated circuit chip and wedge bonds on leadframe fingers adjacent to one or more edges of the integrated circuit chip, the ball bonds and the wedge bonds connected by respective and integral wires; and wherein the information is encoded by varying one or more wirebonding parameters on each chip pad of the set of chip pads, the wirebonding parameters selected from the group consisting of the location of a ball bond, the diameter of a ball bond, both the location and diameter of a ball bond, the location of a wedge bond and combinations thereof.

Abstract: A semiconductor power chip, may have a semiconductor die having a power device fabricated on a substrate thereof, wherein the power device has at least one first contact element, a plurality of second contact elements and a plurality of third contact elements arranged on top of the semiconductor die; and an insulation layer disposed on top of the semiconductor die and being patterned to provide openings to access the plurality of second and third contact elements and the at least one first contact element.

Abstract: In accordance with an embodiment of the present invention, a semiconductor package includes a first lead frame having a first die paddle, and a second lead frame, which has a second die paddle and a plurality of leads. The second die paddle is disposed over the first die paddle. A semiconductor chip is disposed over the second die paddle. The semiconductor chip has a plurality of contact regions on a first side facing the second lead frame. The plurality of contact regions is coupled to the plurality of leads.

Abstract: A quad flat no-lead (QFN) integrated circuit package is provided. The QFN integrated circuit package includes an insulating adhesive layer, a semiconductor chip attached to the insulating adhesive layer, and a lead frame bent to be electrically connected to the semiconductor chip and attached to the insulating adhesive layer. The QFN integrated circuit package according the present invention does not use a die paddle and is thus thin. Accordingly, the volume of the package can be minimized.

Abstract: An integrated circuit module including a generally flat die attachment pad (DAP) positioned substantially in a first plane; and a generally flat lead bar positioned substantially in a second plane above and parallel to said first plane and having at least one downwardly and outwardly extending lead bar lead projecting therefrom and terminating substantially in the first plane; a top leadframe having a plurality of generally flat contact pads positioned substantially in a third plane above and parallel to the second plane and a plurality of leads having proximal end portions connected to the pad portions and having downwardly and outwardly extending distal end portions terminating substantially in said first plane; an IC die connected to the top leadframe, and the DAP; and encapsulation material encapsulating at least portions of the DAP, the lead bar, the top lead frame, and the IC die.

Abstract: A method for producing a component and device including a component is disclosed. A basic substrate having paper as substrate material is provided, at least one integrated circuit is applied to the basic substrate, the at least one integrated circuit applied on the basic substrate is enveloped with an encapsulant, and at least parts of the basic substrate are removed from the at least one enveloped integrated circuit.

Abstract: A method includes forming a polymer layer over a metal pad, forming an opening in the polymer layer to expose a portion of the metal pad, and forming an under-bump-metallurgy (UBM). The UBM includes a portion extending into the opening to electrically couple to the metal pad.

Abstract: A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads.

Abstract: A semiconductor device includes: a lead frame; a semiconductor element held by the lead frame; a frame body which is formed on the lead frame to surround the semiconductor element, cover a side surface of the lead frame, and expose a bottom surface of the lead frame; and a protective resin filling a region surrounded by the frame body. The lead frame includes an uneven part formed in a section which is part of an upper surface of the lead frame, and is covered with the frame body.