Abstract: A laminate capable of mounting semiconductor elements thereon; comprising an insulating layer which is constituted by a resin portion of sea-island structure and a woven reinforcement. The resin portion of sea-island structure is, for example, such that a resin as islands are dispersed in a resin as a matrix. Thus, the insulating layer exhibits a coefficient of thermal expansion of 3.0.about.10 (ppm/K) in a planar direction thereof and a glass transition temperature of 150.about.300 (.degree.C.). Owing to these physical properties, thermal stresses which the laminate undergoes in packaging the semiconductor elements thereon can be reduced, so that the connections of the laminate with the semiconductor elements can be made highly reliable.

Abstract: An area TAB film has a plurality of first lead lines and a plurality of second lead lines on a base film. Each of first lead lines will be electrically connected to each of peripheral electrode pads while each of second lead lines will be electrically connected to each of inner electrode pads when the chip will be mounted on the TAB film. In this TAB film, the first and the second lead lines have a staggered arrangement from each other and are extended in opposite directions. Practically, the distance or the gap between the first lead lines is wider than that of conventional TAB film. Consequently, the TAB film can cope with an increase of the number of pads with a package size kept unchanged and serves to obtain a low cost package as compared with the conventional TAB film.

Abstract: In a lead frame with a reinforcing ring surrounding a semiconductor element which are electrically connected to leads through electrodes is integrally formed through suspending portions, reinforcing portions for reinforcing the suspending portions are provided on the suspending portiones. Upon application of a lead frame forming technique in which a laminate plate of three or more layers is used as a base, and inner leads are formed at one side while outer leads are formed by the surface layer at the other side, the lead frame is formed by forming a ring in place of outer leads, for example. A semiconductor package is formed by mounting the lead frame on a semiconductor chip.

Abstract: A radio frequency identification tag (14) utilizes an antenna (22) formed in association with, and thus integral to, an article, package, package container, label and/or identification badge (10). In a preferred embodiment, a radio frequency identification tag circuit chip assembly (12) is secured to the article (10) and is electrically coupled to the antenna (22) formed on the article (10). Printing a conductive pattern on the article using conductive ink forms a preferred antenna.

Abstract: A semiconductor package provided with a reinforcing plate on the side of the lead joined face of which a chip housing concave portion is formed, a semiconductor chip housed and fixed in the chip housing concave portion of this reinforcing plate, a plurality of leads joined and held on the lead joined face of the reinforcing plate, the inner lead section of which is joined to the semiconductor chip via a bump and in the outer lead section of which a protruded electrode is formed, a solder resist film formed on the lead except the bump formed area and the electrode formed area of this lead and a polyimide film formed on the side of the inner lead section of the lead on the solder resist film and the manufacturing method are disclosed and hereby, the quality of the semiconductor package with ultra-multipin structure is stabilized.

Abstract: A QFP adapted to lowering the heat resistance and increasing the number of pins, and a method of producing the same. The QFP includes a heat-radiating metal plate having bumpers formed at the four corners thereof as a unitary structure, a semiconductor chip mounted on the heat-radiating metal plate, leads provided on the heat-radiating metal plate and surrounding the peripheries of the semiconductor chip, bonding wires for connecting the leads to the semiconductor chip, and a sealing resin member for sealing part of the semiconductor chip, inner leads of the leads, bonding wires and part of the heat-radiating metal plate. The tips of the bumpers integrally formed with the heat-radiating metal plate are positioned outside the tips of the outer leads that are protruding from the sealing resin member. In the QFP producing method, the heat-radiating metal plate having the bumpers and the lead frame having the leads are secured outside the sealing resin member.

Abstract: An improved semiconductor device and method of manufacturing employs interconnecting films on film circuit as ground lines which extend to the periphery of the film circuit where there is a further connection to a conductive reinforcing plate 25. Advantageously, the conductive reinforcing plate reduces electrical noise from interfering with the semiconductor device and prevents the semiconductor device from radiating undesired signals. The interconnecting films also reduce cross-talk between signal lines of the semiconductor device.

Abstract: A semiconductor device manufacturing method and a semiconductor lead frame and its manufacturing method are disclosed. The semiconductor lead frame, in one form, comprises a chip pad section on which a semiconductor chip is mounted and a lead section including inner leads that are wire-bonded to electrodes of the semiconductor chip and outer leads that protrude out from the lead frame after packaging. Further, when the pad section and the lead section are connected together using a folding portion, which has not been folded, then the chip pad section sits apart from the lead section without overlapping. When the folding portion is folded, the ends of the inner leads of the lead section overlap the chip pad section and are located around a semiconductor chip mounting position of the chip pad section. Other forms of the semiconductor lead frame and various forms of the above-mentioned manufacturing methods are also disclosed.

Abstract: A configuration for a conventional lead frame for conserving limited leads and for allowing the location of bond pads anywhere on the periphery of the semiconductor device and for reducing the cost of tooling changes by permitting the use of current tooling. The present invention utilizes an extended lead finger that extends along the periphery of a semiconductor device to provide a power source or ground so that any number of bond pads may be used in any position without requiring additional leads or tooling changes.

Abstract: Electrodes of a semiconductor element are connected to lead wires provided on a flexible substrate, thereby forming a structural unit of a semiconductor element. A plurality of structural unit of a semiconductor elements are stacked on a mounting board, and the lead wires of each flexible substrate are electrically connected to wiring patterns on the package board. The stacked structure units of semiconductor elements are sealed on a package board through use of resin.

Abstract: There is provided a method for manufacturing a lead frame which can easily manufacture a high quality lead frame.A pattern layer is selectively formed on a copper plate and the surface of the substrate having formed this pattern layer is then plated with gold to form a gold layer using the pattern layer as the mask. Next, the gold layer is then plated with copper to form a copper layer, thereby forming a fine lead consisting of two layers of gold layer and copper layer. Thereafter, the pattern layer is selectively removed, an insulated resist film is formed and the copper plate is etched. In this case, the gold layer is used as the etching stop layer. Thereby, the lead frame having the fine lead of double-layer structure can be formed.

Abstract: In a lead frame, leads are formed on a surface of protective insulation film having a device hole. Protruding electrodes (solder balls) are formed on the surface of the leads opposite the surface closer to the protective insulation film. A reinforcement plate is also formed on the rear surface of the protective insulation film.

Abstract: A lead frame equipped with modified lead fingers which have inclined tip portions for achieving an improved wire bond is provided. The inclined tip portions on the lead fingers can be formed in a stamping process with an angle on a top surface of the inclined tip portion measured at smaller than 30.degree. from a horizontal plane of the lead finger. It is preferred that the inclined angle should be between about 5.degree. and about 30.degree., and more preferred that the angle should be between about 5.degree. and about 20.degree.. A wedge bond formed on the inclined tip portion of a lead finger has improved thickness and thermal stress endurance. The thermal stress endurance may be improved by at least 20% and preferably by at least 50% when tested in a thermal cycling test between 150.degree. C. and -65.degree. C.

Abstract: In a tape carrier, one or a plurality of overhang patterns, each being shorter than a length that reaches an edge of a semiconductor chip, is provided in an area where the pitch between adjacent inner leads is relatively large or in a corner area of the device hole where inner leads are not provided, depending upon the size of such area. An average of resin sealing ranges on the rear surface of the tapes is 0.8 mm and the diversification is 0.06 mm.

Abstract: A semiconductor device in which inner leads among a plurality of leads are arranged on a circuit formation face of a semiconductor chip encapsulated by a resin encapsulating body and bonding pads formed on the circuit formation face of the chip and the inner leads are electrically connected. An adhesive is selectively applied only to the inner leads on the outermost sides arranged on both ends of the chip among the plurality of inner leads. The circuit formation face of the chip and the inner leads of the selected leads are joined with the adhesive Each of the selected leads has a step on the main face of the semiconductor chip and the leads except for the selected leads have almost straight shapes without being processed to have steps.

Abstract: A semiconductor device includes a semiconductor chip in which electrode pads are formed with a first pitch, leads electrically connected with the electrode pads through lines, and sealing plastic sealing the semiconductor chip. In the semiconductor device, projections used for external connection ports are formed in the leads with a second pitch. The sealing plastic seals the lines connecting the electrode pads and the leads, but the projections are exposed from the sealing plastic.

Abstract: The integrated semiconductor circuit has a semiconductor chip, a housing that accommodates the semiconductor chip, and a lead frame that connects the contact areas of the semiconductor chip and forms external terminals of the integrated semiconductor circuit. The conductors of the lead frame are sunk, in the regions of the housing in which the distance between the edge of the housing and the semiconductor chip is relatively large, to the central plane of the housing, with the result that the conductors of the lead frame have depressions in those regions.

Abstract: A plastic-encapsulated semiconductor device is provided, which makes it possible to reinforce the power/ground line by a bus-bar without using the over-lead bonding technique.

Abstract: A bottom lead package is capable of increasing a memory capacity for a mounting position on a mother board by stacking several semiconductor packages such that exposed surfaces of leads on upper and lower surfaces of the package are aligned. The package includes a semiconductor chip, a plurality of lower leads attached to the lower side of the chip by an adhesive, a plurality of upper leads attached to the upper side of the chip by an adhesive and to the upper surfaces of the lower leads, wherein metal wires electrically connect the upper leads with a plurality of chip pads formed on the chip, and wherein a molding section packages the chip, the metal wires and the upper and lower leads, such that the upper and lower surfaces of the upper and lower leads, respectively, are externally exposed.

Abstract: An integrated circuit (IC) module incorporates a modified lead frame having a die attach platform, a plurality of leads extending away from the die attach platform, and a plurality of bus bars surrounding the die attach platform. Multiple I/O pads on an IC chip mounted on the die attach platform requiring a common power supply voltage or communication signals are connected to a common bus bar, allowing a greater variety of signals to be provided from the fixed number of IC-PCB interconnections on the IC module. The bus bar design is readily incorporated into all IC module packaging techniques using conventional manufacturing processes. An embodiment of a lead frame for a lead frame BGA package also includes circular attachment pads at the ends of all leads in order to provide a circular area for mounting of solder balls to ensure consistent solder flow and uniform final solder ball profile without requiring circular vias.

Abstract: A thermally enhanced package for an integrated circuit, the integrated circuit having a surface with bond pads formed thereon, includes a heat sink structure attached to a central region of the integrated circuit surface inward of the bond pads. The package further includes a substrate attached to the heat sink structure. The heat sink structure includes a heat sink and first, second adhesive layers between the heat sink and the integrated circuit, substrate, respectively. The heat sink enhances heat transfer between the integrated circuit and the substrate. Further, the first, second adhesive layers decouple any difference in thermal expansion between the integrated circuit, the heat sink and the substrate.

Abstract: A semiconductor device is provided which can improve a heat radiation characteristic of the package, and also can solve an uniform characteristic of ball sizes when a projection electrode such as soldering balls is formed by way of the electrolytic plating method. A semiconductor device is comprised of: a semiconductor chip in having a plurality of electrode pads and an inside of a pad forming region thereof used as an effective element region; a reinforcement plate provided under such a condition that this semiconductor chip is surrounded by the reinforcement plate; a plurality of leads constituted by an outer lead and an inner lead, in which a projection electrode is provided on the outer lead, and also a tip portion of the inner lead is connected to the electrode pads sealing resin filled into a peripheral region of the semiconductor chip.

Abstract: A radio frequency identification tag (14) includes a radio frequency identification tag circuit chip (12) coupled to an antenna (10) including a conductive pattern (22) printed onto a substrate (16). The substrate may form a portion of an article, a package, a package container, a ticket, a waybill, a label and/or an identification badge. The conductive pattern includes a first coupling region (28) and a second coupling region (30) arranged for coupling to the radio frequency identification tag circuit chip. The first coupling region and the second coupling region are precisely located and isolated from one another via an aperture (31) formed in the substrate.

Abstract: As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

Abstract: A semiconductor device including a semiconductor chip; a plurality of electrodes provided on a surface of the semiconductor chip; an insulative board which includes a plurality of conductive patterns, one end of each of the plurality of conductive patterns being protruded from a periphery of the insulative board so as to function as an outer terminal; a connecting element for electrically connecting the outer terminal to a corresponding one of the plurality of electrodes; and a conductive element which is in electrical contact with a corresponding one of the plurality of conductive patterns.

Abstract: A semiconductor device in which a flat inner lead is connected to a semiconductor pellet so that a side edge of the inner lead is connected to the semiconductor pellet. The lead includes a constricted portion that is twisted so that the side edge faces a surface of the pellet to which the lead is connected. A lead frame is arranged so that the side edge can be twisted into position.

Abstract: A circuit board has traces attached to a flexible trace surface such that the traces can be displaced in a direction of thermal expansion of a component attached to the traces without causing the failure of the solder joint between the component and the trace. In one embodiment, the printed circuit board substrate is etched away in areas not covered by the traces such that flexible protuberances are formed from the substrate underneath the traces. In one method for constructing such a circuit board, a conductive layer is deposited on the printed circuit board substrate. The conductive layer is then etched to form conductive traces. The printed circuit board substrate is then selectively etched using the traces as a mask for etching the printed circuit board substrate. In a second printed circuit board embodiment, a flexible layer of a material is deposited onto the printed circuit board substrate. The traces are then formed on top of the flexible layer.

Abstract: A semiconductor device has a semi-conductor chip 1 having bonding pads 2 thereon, conductive leads 4, each of which comprises an inner lead 41 and an outer lead 42, insulating adhesive tapes 3 by which each of the inner leads 41 of the leads 4 is stuck to the surface 1a of the semiconductor chip 1, bonding wires 6 by which each of the leads 4 is electrically connected to each corresponding bonding pad 2. The semiconductor chip 1, bonding pad 2, adhesive tapes 3, inner leads 41, and bonding wires 6 are molded by a molding resin 5. The boundary of the inner lead 41 and the cuter lead 42 of the lead 4 is bent in S-shape so that there is a step between inner lead 41 and the upper side portion 42a of the outer lead 42 in a certain depth. Then the outer lead 42 protrude out of the molding resin and extend in J-shape. The surface 4a of the upper side portion 42a of the outer lead 42 is higher than the top of the looped bonding wire 6.

Abstract: A double sided single inline memory module (20) comprising a substrate (70) having a plurality of openings (86) and first and second surfaces (92, 94), a plurality of pads (82) being integral with the substrate (70) and extending into the opening (86), a plurality of chips (50) adhered to the substrate (70) having bonding pads (120), wire bonding (80) electrically connecting at least one of the bonding pads (120) to at least one of the pads (82) and potting material (90) encapsulating the wire bonding (80) and filling the opening (86) is disclosed.

Abstract: A semiconductor device packaged in a plastic package wherein the thickness of the plastic mold on the top surface of the semiconductor device chip is less than the height of the lead on the top surface of the semiconductor device chip and the top surface to the plastic mold filling the space between the leads is convex downward in an arc shape, and a metal mold employable for producing the semiconductor device packaged in a plastic package comprising a lower mold having a cavity in which a semiconductor device chip provided with a plurality of leads thereon, is placed during a molding process, and an upper mold having a lower surface having a plurality of longitudinal projections and recesses arranged in parallel to one anther, the cross section of the longitudinal projections and recesses produced along the lower surface of the upper mold being effective to cause longitudinal linear contact along the longitudinal projections and recesses, between the lower surface and the edges of the leads, during a molding

Abstract: A semiconductor chip is bonded onto a die pad portion of a lead frame including nickel/palladium/gold stacked plate layers. Then, a first bonding procedure is carried out with a metal wire of gold pressed against an electrode pad of the semiconductor chip while applying a load of approximately 60 g and ultrasonic waves with a power of approximately 55 mW by using a bonding tool. Subsequently, a second bonding procedure is carried out with the metal wire pressed against an inner lead portion of the lead frame while applying a load of 150 through 250 g and the ultrasonic waves with a power of 0 through 20 mW. In the second bonding procedure, the wire bonding in conformity with the property of the stacked plate layers can be conducted using a large load and a small ultrasonic power, resulting in attaining firm bonding in a short period of time without causing peeling of the gold plate layer.

Abstract: A semiconductor chip is supported on a tape carrier provided with lead wirings. The semiconductor chip is electrically connected to the lead wirings. The semiconductor chip of this quality is bonded in combination with the pe carrier to an aluminum nitride substrate. The lead wirings provided on the carrier combine the two functions as an internal lead and an external lead. The semiconductor package of such a structure as is described above allows multi-terminal connection by the narrowing of pitches between the leads and permits provision of a miniature package excelling in the heat-radiating property. Alternatively, the lead wirings supported on the tape carrier and electrically connected to the semiconductor chip are utilized as internal leads. For the external leads, such lead frames as are bonded to the aluminum nitride substrate are used. The lead frames are electrically connected to the internal leads provided in the tape carrier.

Abstract: The present invention provides printed circuit boards for mounting to a semiconductor integrated circuit die. In one embodiment the printed circuit boards comprise a rigid dielectric substrate having a planar face, a plurality of circuit lines affixed to the face of the substrate, and a plurality of conductive bumps affixed to the face of the substrate. Each conductive bump has an upper bonding surface that is substantially planar and a lateral surface which is essentially perpendicular to the face of the substrate. The conductive bumps and the circuit lines are formed from a single metallic layer. The conductive bumps and circuit lines constitute a unitary, integral structure, i.e., each conductive bump and connecting circuit line lack a physical interface therebetween. The upper surfaces of the conductive bumps extend to essentially the same height above the surface of the substrate, i.e., the upper surfaces of the conductive bumps are substantially coplanar relative to each other.

Abstract: A method for manufacturing a semiconductor package in which production time and cost are reduced and production yield is increased is disclosed, including the steps of: providing a backer having a groove, a cap of the backer, a semiconductor chip having a bonding pad, and a lead frame; coating a binder on an edge portion of the recess of the backer and an edge portion of the cap of the backer; mounting the semiconductor chip on the recess of the backer; forming a conductive material on an edge portion of a lead in the lead frame and contacting the lead having the conductive material thereon with the bonding pad of the semiconductor chip; contacting the backer and the cap; and trimming and forming the lead frame.

Abstract: Chip-support arrangement (23) with a chip support (23) for the manufacture of a chip casing, said chip support being provided on a support foil (20) with conducting paths (21) which are connected on the front side of the support foil facing a chip (39) to contact-surface metallizations (40) of the chip and which with their free ends form a connection-surface arrangement (42) distributed in planar manner for the purpose of connection to an electronic component or a substrate, whereby the conducting paths (21) are arranged on the reverse side of the support foil (20), recesses (28) in the support foil (20) are provided in the region of the contact-surface metallizations (40), the conducting paths for forming the connection-surface arrangement (42) are covered with a perforated mask (36) and the thickness (s) of the support foil is smaller than or substantially equal to the height (h) of the contact-surface metallizations (40) on the surface of the chip.

Abstract: A semiconductor device which is greatly reliable and is also advantageous in high-density mounting, as well as the method for producing the semiconductor device, includes a filmy material placed along the peripheral sides of the semiconductor chip and along one surface of the semiconductor chip. The conductor pattern is provided on the filmy material such that one end of the pattern is connected to the corresponding electrode which has been provided on the other surface of the semiconductor chip and the other end is opposed to the back of the semiconductor chip. Hereby a semiconductor device can be realized which is greatly reliable and is also advantageous for high-density mounting. Besides, the semiconductor device is produced in such a way that a cutting and bending process of each lead and the film tape is performed toward the tape carrier package, so that the other end of each lead is opposed to the back of the semiconductor chip, holding the film tape between them.

Abstract: A bottom lead semiconductor chip stack package which includes a first body and a second body. The first body includes a pair of lead frames, each lead frame having a first lead portion and a second lead portion. A protrusion enclosed in a solder extends from the first lead portion. The first body also includes a semiconductor chip containing chip pads disposed on the surface thereof, the chip pads being connected to the solder enclosed protrusions. The second body has substantially the same structural configurations as the first body and is reversely stacked relative to the first body such that the semiconductor chips are disposed in opposing relationship relative to each other. An adhesive attaches the lead frames of the first body to the corresponding lead frames of the second body.

Abstract: The invention is directed to a chip-sized package (CSP) and method for making a CSP which is simple to manufacture, less costly and more compact, thus being truly a chip-sized package. The inventive CSP has a chip that has an array of chip ports on an active surface, such as an array of solder or metal bumps or any other conductive material. The chip may be held in a cavity of a frame by a pair of frame tie-bars. An encapsulant encapsulates the chip and portions of the chip ports located near the active surface, leaving portions of the chip ports located away from the active surface exposed. Package ports, such as solder balls may be attached to the portions of the chip ports located away from the active surface and used to attach the CSP to a printed circuit board. Various methods are used to leave portions of the chip ports located away from the active surface exposed from the encapsulant. The encapsulant may be removed by laser or grinding to expose portions of the chip ports.

Abstract: An LOC die assembly includes a die dielectrically adhered to the underside of a lead frame. The active surface of the die underlying the attached lead frame is coated with a polymeric material such as polyimide. The underside of the lead frame overlying the die is coated with a layer of soft material, such as silver, which has a lower hardness than the coating on the active surface for absorbing point stresses. Penetration of stacked filler particles into the soft material reduces point stresses on the active die surface and disadhesion stresses on the lead frame components.

Abstract: To provide a semiconductor device in which a thin resin film is provided on the whole margin of the principal plane of a semiconductor chip a lead is provided on the thin resin film, the lead is electrically connected with input and output electrode pads of the semiconductor chip, and the electrical joint is covered and sealed with a seal resin.

Abstract: A semiconductor device with a LOC structure having a semiconductor device lead frame, TAB leads, and an insulating TAB tape, wherein the semiconductor device lead frame has a plurality of leads and is formed by fixing a semiconductor element on one surface side of the leads through insulating tapes. The leads are arranged to correspond to electrodes of the semiconductor element, wherein the TAB leads electrically connect the leads of the semiconductor device lead frame and the electrodes on the semiconductor element, and wherein the insulating TAB tape has electrical insulating characteristics and is fixed on the other surface side of the leads of the semiconductor device lead frame to surround a group electrodes of the semiconductor element, the insulating TAB tape serving to hold the TAB leads to be isolated from each other.

Abstract: A semiconductor chip scale package and method of producing the package are disclosed. The package has a semiconductor chip having signal leading bumps. A PCB is electrically connected to the chip, thus transmitting input and output signals. A plurality of solder balls are formed on the lower surface of the PCB and are used as signal input and output terminals. An epoxy resin layer bonds the chip to the PCB. The PCB consists of a polymer resin substrate, a copper circuit pattern and a solder mask. The copper circuit pattern has a chip bump land and a solder ball land. The lands electrically connect the signal leading bumps to the solder balls. The package has a package size being similar to or slightly larger than a semiconductor chip within 120 % of the size of the chip.

Abstract: A semiconductor device and manufacturing method thereof capable of collectively bonding inner leads to a plurality of electrodes to make mechanically and electrically strong coupling therebetween. An insulating coat 2a, having a conductive property when being subjected to heating, is adhered onto a surface of a semiconductor chip 1 other than an electrode 2, and the tip portion of an inner lead 4a from a lead frame 4 is made to extend to cover the top surface of the electrode 2, before the inner lead 4a tip portion and the insulating coat 2a are anode-junctioned with each other so that the electrode 2 and the inner lead 4a are brought into contact with each other under pressure so as to be electrically coupled to each other.

Abstract: An apparatus and method of attaching I/O pads of an integrated circuit die to package leads. The attachment is made using conventional assembly processes but without using wire bonding. A leadframe with lead fingers is formed and the lead fingers are aligned with bumps extending from the I/O pads. A connection is made by physical contact, laser spot welding, or other coupling techniques.

Abstract: To provide a slim and miniaturized semiconductor integrated circuit device which eliminates the needs for making through holes and conducting in through holes and uses a carrier substrate with a small thermal expansion coefficient difference from a semiconductor chip. A semiconductor integrated circuit device using a carrier substrate having a plurality of extraction conductive layers 3 formed as a single layer on an insulating base body 11 having a thermal expansion coefficient of 4.times.10.sup.-6 .degree. C..sup.-1 to 16.times.10.sup.-6 .degree. C..sup.-1 and comprising a plurality of ball-like external connection terminals 7 in a plurality of closed-end holes 15 arriving at external connection parts 4, each of the external connection terminals 7 having a diameter larger than the depth of each of the closed-end holes 15.

Abstract: A lead frame includes a plurality of leads held by an insulative holding film and each formed of an inner lead portion for being bonded to a semiconductor chip and an outer lead portion, a pad portion formed at an end portion of the outer lead portion, an insulating film formed in a pattern so as to insulate the adjacent leads, a ground film formed on the pad portion and partially on the insulating film and having a wider area as compared with that of the pad portion, and a projecting electrode formed on the ground film.

Abstract: Removable extension areas electrically connected to the original die bond pad allow for testing connections to be made. After removal of the extension areas, the circuitry below the region of the extension areas can be seen through a microscope. The use of perforations and/or underlayer sections can aid in the removal of the extension areas. Underlayer sections may comprise a metal that forms an intermetallic interaction with the metal layer of the extension areas.

Abstract: A semiconductor device includes connector leads which have an offset portion supported by the primary surface of a semiconductor chip on which electronics circuitry is formed into an integrated circuit. The offset portion is disposed near the contact pads for connecting the electronics circuitry. The remaining portion of the connector leads far from the contact pads is spaced from the primary surface by an adhesive strip of electrically insulative material. Bonding wires connect the connector leads to the contact pads. The total thickness of the package is reduced to accomplish a thinner and flatter semiconductor device.

Abstract: An inexpensive pre-molded package for electronic semiconductor circuit with increased thermal extraction capability, improved electrical performance, improved dielectric constant of sealing medium, optically transmissive sealing lid, and partially reduced electromagnetic radiation. In one embodiment, the pre-molded package includes electronic semiconductor circuit, a plurality of electrically conductive leads, a heat spreader, a plurality of electrically conductive bond wires, and a seal lid. Preferably, a surface of the heat spreader remains exposed to the exterior of the pre-molded package. In another embodiment, the pre-molded package includes a semiconductor circuit, a plurality of electrically conductive leads, a heat spreader, a plurality of electrically conductive bond wires, and an optically transmissive seal lid.

Abstract: A method of forming a contact for a photosensitive element of a photosensitive imager including a common electrode separated from a bottom contact by intervening layers of an SiOx transistor passivation layer over the bottom contact and an SiNx diode passivation layer over the transistor passivation layer. Controlled etching through the passivation layers exposes but does not damage the thin film transistor passivation layer extending in regions beyond the common electrode, and also improves adherence of a protective gasket in such regions. The contact pad formed in this process has a layer of diode passivation material and a layer of transistor passivation material disposed between the upper common electrode material layer and the underlying source and drain electrode material layer, with a via provided having smooth and sloped sidewalls over which the common electrode material extends to provide electrical contact between the common electrode material layer and the source and drain electrode material layer.