Abstract: A semiconductor chip package is produced using a lead frame which has an island where a plurality of through holes are formed corresponding to the electrodes of the semiconductor chip, respectively. After an insulating film is formed on the island, the semiconductor chip is fixed to one side of the island through an adhesive layer while aligning the electrodes of the semiconductor chip with the through holes of the island portion, respectively. After sealing the semiconductor chip with sealing resin, solder balls are formed on the other side of the island portion, the solder balls are connected to the electrodes of the semiconductor chip through the through holes of the island portion, respectively.

Abstract: An integrated circuit device is provided that has I/O bonding pads across the surface of the chip, where the I/O bonding pads can be electrically accessed via ancillary testing pads in order to perform functionality or other necessary tests prior to bump bonding formation without damaging the bonding pads or the underlying circuitry.

Abstract: A semiconductor device which comprises a first lead having a tip formed with an island, a semiconductor chip unit mounted on the island of the first lead by means of a solder layer and having a plurality of electrode bumps projecting away from the island, and a plurality of additional leads each of which has a tip electrically connected to the electrode bumps via respective solder deposits. The additional leads include at least second and third leads. The tips of the second and third leads are at least partially wider than the semiconductor chip.

Abstract: Disclosed is a semiconductor device comprising an integrated circuit chip, a first lead having a portion extending substantially in parallel to one side plurality of the chip, and a second lead located adjacent to the first lead. Each of the first and second leads has a recess and a projection continuously. The first lead and second lead are arranged adjacent to each other with the recess and projection of the first lead being in engagement with the projection and recess of the second lead. Bonding wires are bonded on the projection of the first lead and the projection of the second lead. The bonding wires electrically connect the chip to the first lead and also to the second lead.

Abstract: Between an IC and an IC receptacle is interposed a flexible wiring sheet, via which contact pieces of the IC and contacts of the IC receptacle are held in contact with one another. In this case, lateral deviation and flexing of the wiring sheet are prevented satisfactorily, and proper contact between the IC and IC receptacle is ensured. A back-up frame is applied by adhesive to the flexible wiring sheet to form a contact agency. The back-up frame 11 has a central window 11 to form a non-backed-up region in a central portion of the flexible wiring sheet 3 that covers the window. The IC 3 and flexible wiring sheet are held in forced contact with each other in the non-backed-up region. The back-up frame has an outer edge portion forming a back-up region for backing up an edge portion of the wiring sheet. In this back-up region, the IC receptacle and the flexible wiring sheet 1 are held in contact with each other.

Abstract: A novel radio frequency transponder (tag) with a minimum of components and connects is thin and flexible because these components and connects can be unsupported by a substrate layer. This is accomplished by using a conducting leadframe structure not only as a connection medium but also as a circuit element, i.e., the transponder antenna. In various preferred embodiments, the leadframe is mechanically positioned and fixably attached to a circuit chip so that the leadframe (antenna) is self supporting. A protective coating can be added where the leadframe is attached to the circuit chip. Further a protective surrounding can envelops the entire leadframe antenna, circuit chip, and, if provided, the protective coating.

Abstract: To provide a semiconductor device in which a thin resin film is provided on the whole margin of the principal plane of a semiconductor chip, a lead is provided on the thin resin film, the lead is electrically connected with input and output electrode pads of the semiconductor chip, and the electrical joint is covered and sealed with a seal resin.

Abstract: A semiconductor die includes a metal layer deposited thereon for enhancing adhesion between the die and a mold compound package. The metal layer is substantially oxide free. The die is coated with a layer or layers of copper (Cu) and/or palladium (Pd) by electroplating or electroless coating techniques. The metal layer provides a uniform wetting surface for better adhesion of the die with the mold compound during encapsulation. The increased adhesion reduces delamination potential of the die from the package.

Abstract: There is provided a carrier film (130, 140) having a plurality of slits (135) formed by the periphery of a chip mounting region (138) on which a semiconductor chip 10 is to be mounted. The chip mounting region is rectangular and four slits are formed along the four sides of the chip mounting region. The slits may be formed by means of punching with a die or etching.

Abstract: A semiconductor lead frame in which a semiconductor chip is mounted using an insulating adhesive film. The semiconductor lead frame includes an inner lead and a plating layer. The inner lead has a plating groove formed therein at an end portion of a surface opposite a surface to which the insulating adhesive film is attached. The plating layer rests on the plating groove such that an upper surface of the plating layer and the opposite surface of the inner lead are flush. Since the upper surfaces of the plating layer and the inner lead are flush, a pressing force by a heater is uniformly transmitted to a semiconductor chip, thereby improving adhesion reliability of the semiconductor chip.

Abstract: An electronic package which includes a thermally conductive, e.g., copper, member having a thin layer of dielectric material, e.g., polyimide, on at least one surface thereof. On the polyimide is provided the desired high density circuit pattern which is electrically connected, e.g., using solder or wirebonds, to the respective contact sites of a semiconductor chip. If wirebonds are used, the copper member preferably includes an indentation therein and the chip is secured, e.g., using adhesive, within this indentation. If solder is used to couple the chip, a plurality of small diameter solder elements are connected to respective contact sites of the chip and to respective ones of the pads and/or lines of the provided circuit pattern. Significantly, the pattern possesses lines and/or pads in one portion which are of high density and lines and/or pads in another portion which are of lesser density.

Abstract: A three dimensional stack package device that can realize vertical electrical interconnection of the stacked individual package devices without a cost increase or additional complicated processing steps.

Abstract: A flexible circuit board includes an insulating flexible film having a lower surface provided with first wiring patterns having first inner ends, and second outer ends extending to a peripheral area of the insulating flexible film. A semiconductor element is electrically connected to and supported by the first inner ends of the first patterns. A connecting circuit board includes an insulating base substrate having an upper surface provided with second wiring patterns having first inner ends, and second outer ends extending to a peripheral area of the base substrate, and a lower surface provided with external connecting terminals electrically connected to the first inner ends of the second wiring patterns by vias. A resin fills a space between the lower surface of the flexible circuit board and the upper surface of the connecting circuit board so that the semiconductor element is hermetically sealed with the resin.

Abstract: A semiconductor device has a semiconductor element, an output terminal coupled to the semiconductor element and a thin metal member or foil secured to an output terminal. A protective layer covers the semiconductor element including the periphery of the metal foil to define an opening located at the metal foil. By covering the periphery of the metal foil, the protective layer secures the metal foil to the semiconductor element. A lead element is affixed to the metal foil by soldering through the opening. The resulting structure increases the adhesion of the lead element. Furthermore, because the protective film covers and seals the periphery of the metal foil, the advance of moisture into the inside of the semiconductor device is retarded. Accordingly the moisture resistance of the semiconductor device is improved.

Abstract: The present invention is a computational unit comprising a logic processing device, and a memory array deposited on top of and communicating with the logic processing device. More specifically, the present invention is a computational unit comprising a logic processing device, and electrically erasable phase change memory deposited on top of and communicating with the logic processing device.

Abstract: A film carrier tape for a semiconductor package comprises a tape base film having a signal plane with leads disposed thereon and a ground plane on the surface opposite the signal plane. The ground plane has ground plane leads projecting into a device hole and OLB lead holes defined in the tape base film, the ground plane leads confronting the leads on the signal plane. The ground plane leads are electrically connected to selected leads on the signal plane.

Abstract: In a resin-sealed semiconductor device, leads are respectively connected to a plurality of connection electrodes of a semiconductor chip. The leads include a plurality of inner leads respectively connected to the connection electrodes and a plurality of outer leads, first ends of which are connected to the inner leads and second ends of which are connected to an external device. Distal ends of the inner leads have cut-off thin portions, which define a recess for holding the semiconductor chip. The inner leads and the semiconductor chip are covered by a resin sealing material.

Abstract: A thin semiconductor package having a support film formed on an upper surface of the inner leads with a thickness approximately equal to the thickness of a portion of the molding compound overlaying the inner leads.

Abstract: A semiconductor package including a semiconductor chip having at its upper surface a plurality of bonding pads and a tape lead frame having a paddle on which a semiconductor chip is laid, a plurality of inner leads each having a sufficient length to be directly connected with each corresponding bonding pad of the semiconductor chip and a plurality of outer leads each connected with each corresponding inner lead and having a thickness larger than that of the inner lead. The semiconductor chip is die bonded on the paddle of the tape lead frame. An insulating layer is formed over the upper surface of the semiconductor chip except for portions corresponding the bonding pads. Each inner lead has at its one end a bonding bumper for electrically connecting the inner lead with each corresponding bonding pad. Using the epoxy molding compound, the inner leads and the paddle of the tape lead frame, the semiconductor and the insulating layer are molded.

Abstract: An electronic package which includes a thermally conductive, e.g., copper, member having a thin layer of dielectric material, e.g., polyimide, on at least one surface thereof. On the polyimide is provided the desired high density circuit pattern which is electrically connected, e.g., using solder or wirebonds, to the respective contact sites of a semiconductor chip. If wirebonds are used, the copper member preferably includes an indentation therein and the chip is secured, e.g., using adhesive, within this indentation. If solder is used to couple the chip, a plurality of small diameter solder elements are connected to respective contact sites of the chip and to respective ones of the pads and/or lines of the provided circuit pattern. Significantly, the pattern possesses lines and/or pads in one portion which are of high density and lines and/or pads in another portion which are of lesser density.

Abstract: A semiconductor device is provided with a stack of a plurality of semiconductor elements each having a bump deposited on each of surface electrodes, and a plurality of leads disposed closely adjacent to the stacked semiconductor elements, the leads being bonded to the bumps respectively thereby structurally integrally assembling the plural semiconductor elements.

Abstract: A chip carrier semiconductor device comprises a semiconductor chip having a surface on which a plurality of contact pads, a tape carrier overlying the semiconductor chip and a plurality of leads provided on the tape carrier to overly the semiconductor chip, each of the leads having an inside end being provided with at last one bump for bonding a board, the bump being positioned on an inside area of the contact pads.

Abstract: A semiconductor package, including semiconductor dies, a ball grid array, and a printed circuit board, is described. Said package has been designed with a view to minimizing its level of internal mechanical stress. This has been achieved through use of two sets of solder joints that have different melting points. The joints with the higher melting point are positioned in the region, on the ball grid array, where it is known that stress will be a maximum in the finished package. The lower melting point joints occupy the remaining positions on the underside of the ball grid array. Ball grid array and printed circuit board are attached to one another by heating at a temperature that is between the aforementioned two melting points.

Abstract: Disclosed is a semiconductor device comprising an integrated circuit chip, a first lead having a portion extending substantially in parallel to one side plurality of the chip, and a second lead located adjacent to the first lead. Each of the first and second leads has a recess and a projection continuously. The first lead and second lead are arranged adjacent to each other with the recess and projection of the first lead being in engagement with the projection and recess of the second lead. Bonding wires are bonded on the projection of the first lead and the projection of the second lead. The bonding wires electrically connect the chip to the first lead and also to the second lead.

Abstract: An object of the present invention is to, in methods of processing metal plates and lead frames, enable workpieces to be finely processed into a satisfactory configuration with high dimensional accuracy without suffering the effect of heat produced under irradiation of a laser beam. According to the present invention, resist films (1) are first coated on both surfaces of a metal plate (1), and a laser beam (202) is then irradiated to the metal plate (101) from surfaces of the resist films (1) to form a multiplicity of discontinuous through holes (3) in line, while leaving joints (6) as not-processed portions between the adjacent through holes (3). Openings (2) formed in each resist film (1) by the laser cutting are joined with each other to serve as an etching pattern. Next, etching is carried out to etch side walls (6) defining the through holes and also to remove the joints (6), thereby interconnecting the through holes (3) formed in line to form a gap (303a) of a desired shape.

Abstract: An interposer between the leads of a leadframe and the ends of wires connected to an integrated circuit die is described herein. The interposer may consist a polyimide tape or other insulating material with conductive traces formed thereon, each trace electrically connecting an inner bonding pad to an outer bonding pad formed on the tape. The outer bonding pads are generally arranged around the periphery of the interposer and are bonded to respective ends of the leadframe. An integrated circuit die is placed in approximately the center of the interposer surrounded by the inner bonding pads. An automatic bonder then bonds wires to the bonding pads on the die and to the inner bonding pads on the interposer. The die is now electrically connected to the leadframe via the traces on the interposer.

Abstract: A bonding pad structure for use with compliant dielectric materials and a method for wire bonding is described in which a rigid layer is formed between the bonding pad and the compliant dielectric layer. The rigid layer increases the stiffness of the bonding structure such that an effective bond may be achieved by conventional ultrasonic and thermosonic bonding methods.

Abstract: A single stacked semiconductor package has at least two semiconductor chips densely mounted via a lead on chip method for attaching leads of a lead frame by alternately arranging the leads over or under the semiconductor chips. A tape automated bonding method using thin metal leads formed on insulating tapes, and an adhesive coated on the lower portions of the leads to mount at least two semiconductor chips can also be used. A stacked semiconductor device manufacturing method and the semiconductor package according thereto are suitable for use in large scale integration circuits.

Abstract: A raised pedestal is formed on a leadframe die mount pad and is used in forming an electrical connection between the die bond pad and the semiconductor die, the electrical connection being isolated from the shear forces developed during temperature cycling or during thermal shock of the resultant semiconductor device. Such shear forces usually result in destruction of the bond between the semiconductor die and the die bond pad.

Abstract: Positive mechanical alignment is provided between substrates using micro-bump contacts by forming "detented" conductive bump contacts on one substrate having a concave end which receive and align the generally convex contour of bump contacts on the other substrate. Various configurations of concavities and convexities are described. Flux may be disposed in the concave end of the detented bump contact to promote formation of joints between the concave and convex bump contacts. Both bump contacts may be formed of reflowable material, such as solder, or one or the other of the contacts may be formed of a non-reflowable material which may also function as a standoff between the two substrates. Each substrate is provided with a plurality of bump contacts, and one substrate may be provided with a combination of convex and concave bump contacts corresponding to concave and convex bump contacts on the other substrate. The inventive technique is useful for joining die-to-die, die-to-substrate, or package-to-substrate.

Abstract: A tape carrier comprises an insulating film and a pattern formed of a metal foil on at least one side surface of said film, said tape carrier being characterized in that an adhesive resin overcoat is applied to the pattern surface portion around a portion to be coated with an IC sealing resin, and a polyimide resin-based overcoat is applied to the remaining pattern surface portion.

Abstract: A method of fabricating a high density thin film circuit includes the step of bonding a high density connector having a plurality of electrical connection lines with a wafer having a plurality of electrical contact pads arranged in a pattern with a pitch less than about 100 .mu.m so that an electrical coupling is formed between respective ones of the wafer contact pads and corresponding ones of connector electrical connection lines. The step of forming the electrical coupling comprises pyrolysis of an adhesive disposed between the high density connector and said wafer.

Abstract: An inner lead of a lead frame has an outer end portion extending so as to be connected with a side surface of an etching stop layer and with an upper surface of an outer lead. The outer lead is formed by etching both surfaces of a metal base, and the inner lead is formed by plating metal on the metal base with a resist layer used as a mask. The pitch of the outer lead can be made fine, and a bonding strength of the inner lead to the outer lead can be increased.

Abstract: A miniaturized electronic device and a manufacturing method for the same is disclosed. Solder is provided on pads provided on leads and corresponding pads provided on an electronic part chip of the electronic device are placed on the solder. The solder is radiated with infrared rays and thereby melted. Then connecting parts are completed. This electronic device does not have a die and wires for bonding. Therefore, it is more miniaturized than a conventional electronic device.

Abstract: An electronic module comprising a multiplicity of prestacked IC chips, such as memory chips, and an IC chip, referred to as an active substrate or active backplane, to which the stack of chips is directly secured. A multiplicity of aligned solder bumps may interconnect the stack and the substrate, providing electrical, mechanical and thermal interconnection. The active substrate is a layer containing substantial amounts of integrated circuitry, which interfaces, on one hand, with the integrated circuitry in the stacked chips, and, on the other hand, with the external computer bus system. Some of the high priority circuitry which may be included in the substrate is used for control, fault-tolerance, buffering, and data management.

Abstract: A resin encapsulation type semiconductor device is provided with first leads electrically connected to the signal terminals of a semiconductor element and plate-like conductor elements electrically connected to the power source terminals of the semiconductor element. The first leads and the plate-like conductor elements are arranged in parallel with each other to form a two-layer structure. The number of the leads of the semiconductor element of the invented semiconductor device is reduced from that of the leads of the conventional semiconductor device. At least one through hole is formed in each of the plate-like conductor elements in a power source lead frame so as to make the flow distribution more uniform than in the plate-like conductor elements without the through holes.

Abstract: A semiconductor device has a semiconductor element mounted on inner leads of a TAB tape and first and second heat radiator elements having respective first and second peripheral flanges which cooperatively engage and thereby support the TAB tape in a sandwich manner therebetween, at least one heat radiator member having a central portion protruding toward and providing a support for the semiconductor element. A sealing resin fills the space between the heat radiator members and thereby integrally interconnects and hermetically seals interior surfaces of the leads of the TAB tape. A central portion of at least one of the heat radiator members protrudes toward and provides a support for the semiconductor element.

Abstract: There is provided a lead frame structure used in a semiconductor device which is fabricated by a tape carrier bonding method. The lead frame structure has a convex portion at its top portion which is subjected to a thermal compression with a bonding tool. The convex portion may be formed by bending the top portion of the lead frame toward the bonding tool side up to an angle of at least approximately 90 degrees. When the bonding tool compresses the top portion of the lead frame, the bent portion is compressed and deformed but no damage of the lead frame thereby preventing formations of a depression region and a rapid drop portion in the lead frame, which is defined by an edge of the bonding tool in which the rapid drop portion is likely to cause disconnection of the lead frame during or after the bonding process. The invention permits the lead frame to be free from disconnection by a thermal compression with the bonding tool.

Abstract: Disclosed is a semiconductor device comprising a lead frame which includes a metal layer forming an outer lead, a thin metal layer forming an inner lead, an intermediate layer held between the thick metal layer and the thin metal layer for forming a connection portion between the outer lead and the inner lead and a bump positioned at the extreme end of the lead frame, whereby making the lead frame as an electrode leading means by directly connecting the bump to each electrode of a semiconductor element, wherein the lead formed of the thick metal layer has a thickness of 30 to 300 .mu.m, the lead formed of the thin metal layer has a thickness of 10 to 50 .mu.m, and the bump has thickness of 5 to 50 .mu.m.

Abstract: A semiconductor package and a method for manufacturing such a package in which a desired thickness of the package is accomplished. The package includes a semiconductor chip provided with a plurality of solders which are formed on pads of the chip, respectively, and a plurality of inner leads of a lead frame which are electrically connected to the solders by soldering. The method comprises the steps of coating polyimide layers on a surface of semiconductor chip, forming solders on pads of the chip, soldering inner leads of a lead frame to the solders in order to electrically connect the chip to the inner leads, molding an encapsulation epoxy resin coating in order to cover a predetermined area including the semiconductor chip and the inner leads, and trimming and forming the package having been processed in above steps.

Abstract: An outer lead of a metal lead frame is connected to an inner lead of a flexible lead-patterned substrate via a Au-Sn alloy layer. The Au-Sn alloy layer contains Au of 10 to 40 weight %.An inner lead of a metal lead frame is connected to a patterned lead of a flexible lead-patterned substrate by a heating tool. The inner lead is coated on bottom and side surfaces of its tip portion. The bottom surface faces the patterned lead.

Abstract: A CCD package and a method for assembling a CCD package utilizing a TAB process. The method comprises the steps of preparing a tape for TAB which has outer leads, inner leads and die bonding paddles, bonding a chip on the paddles and then bonding the free ends of the inner leads on the bonding pads of the chip, connecting the inner leads and the outer leads through insulations, adding a light shield layer beneath the chip, and attaching a glass lid to the surface portions of the inner leads positioned just above the chip. Accordingly, packages of light, laminated and simple structure can be obtained, thereby advantageously enabling the compactness of products utilizing CCD elements. Also, the process is also simplified, thereby decreasing the cost of producing CCD elements.

Abstract: A semiconductor package includes a die having a first surface including a plurality of bond pads disposed thereon and a second surface. Inner lead portions of a TAB leadframe are coupled to the bond pads and outer lead portions electrically coupled to the inner lead portions extend therefrom. An encapsulation is disposed on the first surface of the die including the bond pads having the inner lead portions of the TAB leadframe bonded thereto. Encapsulation is also disposed about the sides of the die. The second surface of the die remains exposed. This allows for a relatively thin package having superior thermal dissipation properties.

Abstract: A semiconductor device comprises a plurality of semiconductor chips; electrodes formed on circuit surfaces of said plurality of semiconductor chips; inner leads made of a metal foil and bonded at first ends thereof to the electrodes, outer leads each having a predetermined surface at a first end thereof bonded to a second end of at least one of the inner leads, and a sealing material sealing said plurality of semiconductor chips, the electrodes, the inner leads, and part of each of the outer leads. The semiconductor chips are laminated in such a manner that those surfaces of the semiconductor chips on which their respective circuits are formed are disposed in facing relation to each other. This provides a semiconductor device which is excellent in assembling efficiency.

Abstract: An integrated circuit chip carrier assembly, comprising a semiconductor device (10) having interconnection pads (14) disposed on an active surface (12) of the device. The device (10) is attached by means of electrically conducting bumps (26) to a circuitry pattern (18) on a first side of a circuit carrying substrate (16). The substrate is typically an aramid reinforced organic resin, such as epoxy. The circuitry (18, 20) is electrically connected by conductive through-holes (22) to an array of solder pads on a second side of the substrate. Some or all of the through-holes (22) are covered by the device. The overall length and width of the circuit carrying substrate (16) are each a maximum of about 0.15 inches greater than the equivalent dimensions of the device (10), creating a carrier that is only slightly larger than the semiconductor device itself.

Abstract: A partially overmolded integrated circuit package (10) comprises a substrate (14) having circuit traces (11) and a semiconductor die receiving area (15) for attachment of a semiconductor die to the semiconductor die receiving area. Conductive bumps (18) are then applied to a plurality of contact pads on the semiconductor die. Then overmolding compound (16) is applied over the semiconductor die and a portion of the conductive bumps, leaving a portion of the conductive bumps partially exposed (19). Finally, interconnections (13) between the exposed portion of the conductive bumps and the circuit traces of the substrate are formed.

Abstract: A lead frame for mounting a circuit component includes plural terminal legs for connection with a circuit. At least two of the terminal legs have pads for connection with the circuit component which has wire leads. The lead frame pads and wire leads are of materials which are incompatible for welding. A rivet of a material compatible for welding with the component lead wires is mounted in the pad of each terminal leg for connection with the circuit element. A weld secures each component lead wire with one of the rivets.

Abstract: A semiconductor apparatus with high thermal radiating property and a method for producing the same is provided. The semiconductor apparatus comprises a TAB tape 11 having an inner wire 13 and a middle wire; a semiconductor chip 1 connected to the inner wire 13 through a bump 12; and a lead frame 3 having as an integral structure a middle lead connected to the middle wire 14 and a metallic bed 5 in contact with the semiconductor chip 1. The shape of the bed 5 is nearly constant regardless of the size of the semiconductor chip 1. The bed 5 extends nearly to each outer edge of a sealing plastic resin 2. The heat generated in the semiconductor chip 1 is effectively radiated to the outside through the extending bed 5 of the lead frame 3.

Abstract: A conductor attachment wherein each conductor is mounted on a dielectric tape and has an attachment portion that is supported by the tape to an adjacent location a uniform distance from the bonding location and that contacts on a level with the plane of the underside of the tape. One conductor supporting tape has portions of the tape that extend into a central contacting area opening to contact locations at contacting pads in rows remote from the edge. Another supporting tape has window openings at the contacting locations. The conductor ends are brought into the level of the underside of the tape by a manufacturing rolling operation between an elastomer surface roller and a solid backing roller.

Abstract: An integrated circuit (IC) and lead frame assembly comprises a first TAB segment having a plurality of leads having inner and outer ends. The inner ends are connected to bumps formed in a square pattern adjacent the periphery of the IC. A second TAB segment includes a plurality of leads having inner and outer ends. The inner ends are connected to a second set of bumps formed on the IC inwardly from the first set. The outer ends of the leads on the second TAB segment are connected to traces on the first TAB segment which are interleaved between the leads on the first TAB segment. The outer ends of the traces and leads on the first TAB segment thus connect to all of the IC bumps. This arrangement increases the number of connections which can be made to the IC.