With Bumps On Ends Of Lead Fingers To Connect To Semiconductor Patents (Class 257/673)
  • Patent number: 5231303
    Abstract: A semiconductor device comprises a semiconductor chip mounted within a prepared aperture formed in a flexible film carrier. A conductive lead pattern is formed on the surface of the film carrier and the inner lead ends of the lead pattern project over and into the film aperture in aligned relation with a plurality of bonding pads formed on the active surface of the semiconductor chip. The semiconductor chip, or the semiconductor chip together with inner portions of the conductive lead pattern, are encapsulated with a sealing resin to the film carrier. A spatial interval, A defined by the edge of the carrier aperture and the edge of the outer side periphery of the semiconductor chip to be installed in the device aperture, is set within the range of about 0.4 mm to 0.8 mm. Also, the inner leads are provide with a small extended length, preferably in those portions extending into and over the device aperture.
    Type: Grant
    Filed: May 7, 1991
    Date of Patent: July 27, 1993
    Assignee: Seiko Epson Corporation
    Inventors: Yoshihiko Kasahara, Tatsuro Ito
  • Patent number: 5216278
    Abstract: A semiconductor device (10) having first and second wiring layers (30, 33) on opposite surfaces of a carrier substrate (12) interconnected through vias (32) formed in the carrier substrate (12) electrically coupling an electronic component (18) to a mounting substrate through compliant solder balls (26) displaced away from vias (32), the semiconductor device (10) characterized by a standard size carrier substrate (12) having high performance electrical package interconnections (24) and good heat dissipation. Improved electrical performance is obtained by providing independent wiring layers (30, 33) each having a lead trace layout specifically designed for a particular electronic component (18) and a particular board connection requirement while using a standard size package outline. Assembly costs are reduced by providing a plastic package mold (36) over a standard size carrier substrate (12) capable of supporting a variety of different electronic components (18) themselves having varying dimensions.
    Type: Grant
    Filed: March 2, 1992
    Date of Patent: June 1, 1993
    Assignee: Motorola, Inc.
    Inventors: Paul T. Lin, Michael B. McShane, Howard P. Wilson
  • Patent number: 5198883
    Abstract: First and second frame bodies are used to fabricate a semiconductor device. The first frame body includes a die pad. The second frame body only includes a plurality of leads. The die pad is depressed by a predetermined amount which is equal or greater than the thickness of a semiconductor chip to be mounted on the die pad. The two frame bodies are welded, and wire bonding and cutting of the leads are performed.
    Type: Grant
    Filed: July 19, 1989
    Date of Patent: March 30, 1993
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenji Takahashi, Yasuhiro Yamaji, Susumu Harada, Kazuichi Komenaka, Mitsugu Miyamoto, Masashi Muromachi, Hiroshi Harada, Kazuo Numajiri, Haruyuki Shimakawa, Toshiharu Sakurai
  • Patent number: 5173763
    Abstract: In joining conductors at different levels on a carrier to contact locations on a planar substrate, mound shaped connections are employed, with the height of each mound shaped connection extending to the level of the particular conductor to which it is bonded. The mound shaped connections are formed using planar processes of controlled volume deposition, surface tension shaping on reflow, and physical deformation. The height of the mound shaped connections are calculated empirically from the volume deposited bounded by the substrate pad after surface tension limits the slump on reflowing.
    Type: Grant
    Filed: February 11, 1991
    Date of Patent: December 22, 1992
    Assignee: International Business Machines Corporation
    Inventors: Thomas M. Cipolla, Paul W. Coteus, Robert H. Katyl, Robert J. Kelleher, Paul A. Moskowitz