Abstract: Improvement is affected in uniformizing the thickness of a tape carrier package having a semiconductor chip in which bonding pads are disposed in such a way that the bonding pads are arranged concentratedly on one side of the semiconductor chip.

Abstract: An object of the present invention is to provide a radio frequency integrated circuit module that is less susceptible to the electromagnetic influence and that is not degraded in electric connection. The radio frequency circuit module of the present invention including circuit elements mounted on a multi-layer circuit substrate having dielectric layers is characterized in that an exposed connection portion is provided by removing a part of the dielectric, and a strip line connected to said circuit elements and a co-axial line for transmitting a radio frequency signal from/to said strip line are connected together in a bottom portion of said exposed connection portion so as to be rectilinear in a three dimensional way.

Abstract: A reinforced semiconductor package (20,30) and method utilizes at least one of the grooves (15,16) and ridges (24,25) formed on the package body (17,23) to reinforce the package body (17,23) to prevent warping of the package after molding.

Abstract: A semiconductor apparatus includes a thin film belt-like insulating tape having a plurality of predetermined wire patterns thereon, and a plurality of IC chips that are provided on a surface of the insulating tape at uniform spaces in a lengthwise direction and electrically connected with the wire patterns, and further includes thick film reinforcing tapes with sprocket holes for transport use provided at uniform spaces, the reinforcing tapes being provided on both side portions of the insulating tape, in the lengthwise direction.

Abstract: A lead frame for a semiconductor chip package includes a frame body and at least two chip-receiving windows formed in the frame body. Each chip-receiving window receives a respective integrated circuit chip therein. A plurality of internal connection leads are formed on the frame body adjacent to the chip-receiving windows, and are connected electrically to bonding pads on the integrated circuit chips in the chip-receiving windows such that internal electrical connection among the integrated circuit chips can be established via the internal connection leads., A plurality of external connection leads are formed on the frame body adjacent to at least one of the chip-receiving windows, and are connected electrically to the bonding pads on the integrated circuit chip in the adjacent chip-receiving window.

Abstract: An electronic component includes an inner lead having a tip with a projection; an insulating coating that is electrically conductive when heated disposed around the projection; and a metallic coating disposed around an electrode on a semiconductor chip, with a crater reaching the electrode, the projection engaging the crater to make a contact between the inner lead and the electrode, the insulating coating and the metallic coating being anodically bonded to each other.

Abstract: A lead frame (1) is provided which includes elongated side frames (2, 3) extending in parallel to each other, and section bars (4) connecting the side frames in a manner allowing the side frames to be shifted longitudinally. The side frame (2) is integrally formed with first lead terminals (6), whereas the side frame (3) is integrally formed with second lead terminals (7). Extremities of the first and the second lead terminals are overlapped after the side frames (2, 3) are shifted. At least either one of the first lead terminal (6) and the second lead terminal (7) is formed with a weaker portion having reduced bending strength. The extremities of the first and the second lead terminals is bonded to a semiconductor element (T) after the side frames (2, 3) are shifted. Thereafter, restoring force due to the spring-back action of the section bars (4) acts on the lead terminals (6, 7) and the semiconductor element (T). However, the restoring force is used to deform the weaker portion.

Abstract: Leadless plastic chip carriers are formed from a matrix of lead frames provided in a section of a metal strip. Each lead frame in the matrix includes a die-attach pad and multiple leads disposed in close proximity to the die-attach pad. After a semiconductor die is attached to each of the die-attach pad and wire-bonded, the leadless plastic chip carriers are formed by providing a plastic encapsulation which exposes the bottom sides of the die-attach pad and the leads. The bottom sides of the leads serve as solder pads to be used for attaching the leadless plastic chip carrier to a printed circuit board.

Abstract: A semiconductor device includes a lead frame, a semiconductor chip, a resin-encapsulated portion, and tie bars. The semiconductor chip is mounted on a die pad of the lead frame. The resin-encapsulated portion resin-encapsulates the semiconductor chip. The tie bars are provided to outer lead portions of the lead frame to prevent resin leakage during resin encapsulation, and are cut and removed in a finishing step of resin encapsulation. A plating surface is formed on a sectional surface of each of the tie bars. A semiconductor device manufacturing method and apparatus are also disclosed.

Abstract: A memory TCP loaded with four chips (1-bank 16-bit type) is constructed by a tape of one two-layer wiring layer structure, four chips mounted to this tape, etc. Common signal terminals are arranged on one set of two opposed sides, and an independent signal terminal is arranged on another side. The common signal terminals on the two sides are electrically connected to each other common signal wiring. Further, in a DIMM in which this memory TCP is mounted to front and rear sides of a substrate, plural external terminals are formed on one long side of the rectangular substrate, and the memory TCP is mounted such that the independent signal terminal of the memory TCP is arranged along an arranging direction of these external terminals.

Abstract: A semiconductor device comprising an insulating film having a device hole, a plurality of bumps formed on the insulating film, a plurality of first leads having end faces thereof exposed on an outline edge of the insulating film, each of the first leads being electroplated and connected with one of the bumps, a plurality of second leads having end portions thereof protruding into the device hole, each of the second leads being electroplated and connected with one of the bumps, and a semiconductor chip connected with the end portions of the second leads in the device hole. The insulating film is outlined to have a cut in a region including each of the exposed end faces of the first leads.

Abstract: In a semiconductor device, a bus bar (4a) is provided with a projection (9a). Based on a positional relationship between the projection and a metal wire (13a) subjected to the lateral deflection upon resin filling, the metal wire lateral deflection amount is managed. The projection may be provided on a suspension pin or at another portion of a lead frame. A cutout may be provided instead of the projection.

Abstract: An electronic device having first and second external pins; first and second pads connected to the first external pin by respective bonding wires; and third and fourth pads connected to the second external pin respective bonding wires, and to a first common line by respective resistors. By means of a circuit configuration of this type, the intactness of the bonding wires can easily be checked by carrying out a simple resistance measurement between the first and the second external pin.

Abstract: A package for an integrated circuit is disclosed. The package comprises two layers (a top layer and a bottom layer) of flexible tape, each of which has a top surface and a bottom surface, with metal traces on the top surface. A die is mounted on top of the two layers and wire bonds connect bond pads on the die to metal traces on each of the two flexible tapes. The metal traces are routed along the top surfaces of the flexible tapes and are coupled to solder balls through holes in the tapes. These solder balls are mounted along the bottom of the package and serve as the electrical interface to a printed circuit board. Additional holes in the bottom layer tape allow solder balls to extend through the bottom layer tape so that they may be electrically coupled to traces on the top layer tape.

Abstract: An insert-molded leadframe having wire bonding posts formed on an inner portion, device pins formed on an outer portion, and a central portion connecting between the inner portion and the outer portion. Plastic encases the central portion of the conductive leadframe, such that the bonding posts and the device pins are exposed at inner and outer edges, respectively, of the plastic casing. The bonding posts and the device pins are disposed substantially perpendicular to one another. The conductive leadframe is formed with the bonding posts in a first plane and the device pins in a second plane, the first and second planes being substantially mutually parallel. The conductive leadframe then is encased in plastic by injection molding to form the insert-molded leadframe of the invention.

Abstract: The invention provides means for effectively preventing a wire disconnection generated due to an increase of calorie applied to a semiconductor integrated circuit device. The semiconductor integrated circuit device is structured such that a metal layer containing a Pd layer is provided in a portion to which a connecting member having a conductivity is connected, and an alloy layer having a melting point higher than that of an Sn—Pb eutectic solder and containing no Pb as a main composing metal is provided outside a portion molded by a resin. Further, a metal layer in which a thickness in a portion to which the connecting member having the conductivity is adhered is equal to or more than 10 &mgr;m is provided in the connecting member.

Abstract: An optoelectronic device is mounted on a planar substrate in electrical connection with solder bumps adjacent an edge of the substrate and connection to a lead frame is made by loading the edge of the substrate on a lead frame support with lead frame conductors in engagement with the solder bumps and applying heat to melt the solder.

Abstract: A semiconductor device having enhanced reliability which is obtained by cutting a wafer encapsulated by an encapsulating material layer in such a manner that each of end faces of bumps for an external terminal is exposed, and a method of isolating a metal in an encapsulating material to allow measuring. The semiconductor device comprises a semiconductor element, bumps formed on a surface thereof for external terminals, and an encapsulating material layer, the encapsulating material layer being formed of an encapsulating material containing greater than 70% by weight and not greater than 90% by weight of fused silica, based on the total weight of the encapsulating material.

Abstract: A mounting substrate and related mounting method for a semiconductor device. The mounting substrate includes a mounting area to which the semiconductor device is to be mounted and fixed by an adhesive, a peripheral channel formed in the mounting substrate so as to surround the mounting area, and radial channels extending radially from the center towards the periphery of the mounting area. An adhesive is applied at least to either the center of the mounting surface of the semiconductor device or the center of the mounting area of the mounting substrate. The semiconductor device is placed on the mounting area and the adhesive flows outwardly along the radial channels, with the adhesive then being cured. The peripheral channel provides control of the amount of adhesive which flows to the outside of the semiconductor device and the mounting area. The adhesive overflow can be adjusted such that adhesive climbs up the sides of the semiconductor device but not reach the upper surface of the device.

Abstract: A wire interconnect structure for electrically and mechanically connecting an integrated circuit chip to a substrate and a process for manufacturing the same. The wire interconnect structure comprises an insulator layer disposed on an integrated circuit chip and an electrically conductive post extending through the insulator layer to the integrated circuit chip. The post has an elongated body, a bottom at one end of the body which is mechanically and electrically connected to the integrated circuit chip, and a top having a spherical shape at the opposite end of the body which extends outward from the insulator layer.

Abstract: An antenna composed of composite material which can be screen printed is proposed for RFID transponders and other RF communication systems.

Abstract: A lead frame for LOC to which a semiconductor chip is fixed within a semiconductor chip-mounting region. In addition to applying insulative adhesives to the conventional portions or spots which are on the bottom surfaces of the leading edges of respective inner leads for wire bonding to the pads for the semiconductor ship, the insulative adhesives are applied to other portions of the inner leads in the vicinity of the semiconductor chip-mounting region. Accordingly, the area for bonding the semiconductor chip can be enlarged resulting in improvements in the stability of adhesion between the leads and the semiconductor chip, and in the stabilities of wire bonding and resin molding.

Abstract: A radio frequency identification device (RFID) has an antenna formed on a chip. The chip has backside and a front side coated with conductive traces, which are connected through conductive traces on the sides of two elongate through-hole slots formed on the chip to form an operative coil having the chip as a core. In one embodiment, the antenna chip may be stacked above an integrated circuit. In another embodiment, the integrated circuit may be formed on the antenna chip. The antenna chip may include a high magnetic permeability layer to increase the inductance of the coil, a capacitor to tune the coil to a desired frequency, and a coupling capacitor to power the integrated circuit. As well as the specific application disclosed, an inductance useful in numerous applications can be formed according to the above structure.

Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.

Abstract: A semiconductor device comprising a resin mold, two semiconductor chips positioned inside the resin mold and having front and back surfaces and external terminals formed on the front surfaces, and leads extending from the inside to the outside of the resin mold, wherein each of said leads is branched into two branch leads in at least the resin mold, the one branch lead is secured to the surface of the one semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, the other branch lead is secured to the surface of the other semiconductor chip and is electrically connected to an external terminal on the surface thereof through a wire, and the two semiconductor chips are stacked one upon the other, with their back surfaces opposed to each other.

Abstract: A semiconductor device includes a lead frame, a dielectric tape layer, a plurality of conductive contacts and a semiconductor die. The lead frame is provided with a plurality of leads. The dielectric tape layer has a first adhesive surface adhered onto the leads, and a second adhesive surface opposite to the first adhesive surface. The dielectric tape layer is formed with a plurality of holes at positions registered with the leads for access thereto. Each of the holes is confined by a wall that cooperates with a registered one of the leads to form a contact receiving space. The conductive contacts are placed in the contact receiving spaces, respectively. The die has a die mounting surface adhered onto the second adhesive surface of the dielectric tape layer. The die mounting surface is provided with a plurality of contact pads that are bonded to the conductive contacts to establish electrical connection with the leads of the lead frame. A method for fabricating the semiconductor device is also disclosed.

Abstract: In a motor driving device, an IC chip of a drive circuit for driving a motor is die-bonded to one island of a leadframe, and a diode chip of a protection diode for preventing the drive circuit from being destroyed when supplied power is connected to the IC chip with reverse polarities is die-bonded to another island of the leadframe. The supplied-power pad of the IC chip is wire-bonded to the second island, which serves as the cathode electrode of the diode chip.

Abstract: A stacked bottom lead package for use in semiconductor devices includes leads that are bent along with the circumference of the body which has been premolded, wherein a chip is included inside the premolded body. The package configuration prevents solder fatigue of the lead due to heat carried via the extended lead and emitted out of the chip and decreases the area required for stacking semiconductor packages.

Abstract: A bow resistant semiconductor package includes a semiconductor die, a leadframe segment and a plastic body. The leadframe segment includes lead fingers attached and wire bonded to the die, and opposing volume equalizing members proximate to lateral edges of the die. The volume equalizing members are downset from a first plane proximate to a face of the die, to a second plane proximate to a center line of the package. In addition, the volume equalizing members are configured to rigidify the package, and to substantially equalize the volumes of molding compound on either side of the package center line and leadframe segment. The equal volumes of molding compound reduce thermo-mechanical stresses enerated during cooling of the molding compound, and reduce package bow. With reduced package bow, a planarity of the terminal leads on the package is maintained.

Abstract: A bonding pad test configuration for establishing whether or not a semiconductor chip is bonded. The test configuration has a circuit that evaluates a state of a bond between a bonding wire and the bonding pad and is able to activate and deactivate operating and test modes depending on the bond state established. To this end, the bonding pad is divided into at least two parts, so that the circuit produced in the semiconductor chip itself can use signals derived from the parts of the bonding pad to establish whether or not the bonding wire is in contact with the parts.

Abstract: Wire sweep/crossing during resin molding is significantly reduced or prevented by reducing the gap spacing between corner lead pins and the tie bars of a die-attach pad. Embodiments of the present invention include spacing the tie bars from the corner lead pins by a distance no greater than about 18 mils, e.g., about 4 to 12 mils. Embodiments of the present invention also comprise a lead frame wherein the inner ends of the lead pins are arranged in a substantially planar array to define a substantially circular region surrounding the die-attach pad.

Abstract: Disclosed is a mold-BGA-type semiconductor device which has: a semiconductor chip which includes insulating resin film formed on at least a part of the surface of the semiconductor chip except a pad; a conductive layer formed in a region on the insulating resin film, the region including at least part corresponding to a position where a solder ball is mounted; a first metal thin wire which is wire-bonded between the pad and the conductive layer; a second metal thin wire which is wire-bonded on the conductive layer; resin part which seals the semiconductor chip, the resin part including a hole to expose part of the second metal thin wire; and a solder ball which is mounted on the hole.

Abstract: In a semiconductor device, the adhesive layer of a tape that is adhered to the surface of a chip is disposed so that there is no overlap with an aperture in the uppermost surface of a semiconductor element. With the usual type of tape, the tape is kept at a distance of at least 0.1 mm from the cover aperture in the surface of the semiconductor element, and in the case in which there are two covers, the tape is kept at a distance of at least 0.1 mm from an aperture at the uppermost surface of the semiconductor element. The aperture includes either a fuse aperture or a bonding bad and fuse aperture.

Abstract: A method of treating a lead in a chip package. A conductive lead is positioned such that it extends across a gap in a dielectric substrate and is secured at either end to a first surface of the substrate. Directed energy is then applied to a desired portion of the surface of the lead within the gap. As a result of the application of energy, a surface layer of the lead is recrystallized thereby creating a fine grain, dense surface layer of lead material. Surface contaminates may be vaporized and contaminants at the grain boundaries of the recrystallized surface layers may be driven away from the grain boundaries such that a treated lead is more ductile and has better resistance to thermal cycling after the lead has been attached to a chip contact.

Abstract: A semiconductor device is provided which is highly reliable and operable at fast speed and low noises. In this semiconductor device, there are provided a power wiring section 1003a, a ground wiring section 1003b and a signal wiring section 1003c are formed on one level. The power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.

Abstract: The leadframe of the present invention comprises a supporting bar having the first terminals and the second terminals, wherein the first terminals are coupled to the separating portion of the leadframe and the second terminals are used to support the chip. A plurality of inner leads connected to the supporting bar. A plurality of external leads connected to the inner leads; Adhesive material, formed on the leadframe and used to attach the chip to the inner leads, wherein the area of adhesive material is smaller than that of said chip. A plurality of bonding wires is used to couple the chip to the leadframe. Finally, the chip is encapsulated with the molding compound to protect the chip and the bonding wires.

Abstract: A card-type semiconductor device including a thin (e.g., 30 to 70 &mgr;m) semiconductor chip which is thinner than an insulating resin film embedded in a device hole of a wiring film. The wiring film includes a copper wiring layer and inner leads arranged on one main face of the insulating resin film. Electrode pads are bonded to the inner leads by heating and pressing. A sealing resin layer is formed on the exterior of the bonded portion as required, and a polyester resin film is integrally laminated on the upper and lower faces of the wiring film. The card-type semiconductor device with the above construction has sufficient strength against bending, etc., and is suitable for integrated circuit (IC) card applications.

Abstract: A densely packaged semiconductor device includes a first semiconductor device having a plurality of bumps which are formed on a backside surface thereof, and a second semiconductor device having a plurality of terminals which are formed on the front surface thereof and which are to be electrically connected with bumps. The second semiconductor device is mounted on an area which is located on the backside surface of the first semiconductor device, the area having no bumps formed therein. The height of the second semiconductor device measured from the backside surface of the first semiconductor device is less than the height of the bumps. The second semiconductor device is mounted on the first semiconductor device such that the surface of the second semiconductor device provided with no terminals is joined to the backside surface of the first semiconductor device with an adhesive.

Abstract: A semiconductor device of surface-mount type includes a circuit strip tailored to have patterns projected, a semiconductor element fixedly joined to the circuit strip, and pads on the semiconductor element electrically connected by wires to the corresponding patterns on the circuit strip and sealed with a resin material. While the surface-mount type semiconductor device is adapted to be simple in structure and capable of high-density mounting, an appliance on which the semiconductor device is mounted and a method of producing the semiconductor device are also provided.

Abstract: In a semiconductor chip, electrode pads are formed in a peripheral portion of the chip front surface and the inside of the pad forming region is made an effective device region. An insulating, thick-film protective layer is laminated on the effective device region of the semiconductor chip. Leads are constituted of outer leads that are protected by an insulating film and inner leads that are integral with and extend from the outer leads. External connection terminals are formed on the outer leads, and the tips of the inner leads are connected to the electrode pads of the semiconductor chip. A reinforcement plate is provided so as to surround the semiconductor chip. A peripheral space of the semiconductor chip is charged with a sealing resin. According to a second aspect of the invention, a semiconductor chip has electrode pads on the chip front surface and disposed inside a conductive outer ring. A film circuit is disposed on the chip front surface side.

Abstract: A flip chip having solder bumps and an integrated flux and underfill, as well as methods for making such a device, is described. The resulting device is well suited for a simple one-step application to a printed circuit board, thereby simplifying flip chip manufacturing processes which heretofore have required separate fluxing and underfilling steps.

Abstract: A packaging and interconnection for connecting a contact structure to an outer peripheral component with a short signal pass length to achieve a high frequency operation. The packaging and interconnection is formed of a contact structure made of conductive material and formed on a contact substrate through a photolithography process, a contact trace formed on the contact substrate and electrically connected to the contact structure at one end, and the other end of the contact trace is extended toward an edge of the contact substrate, a connection target provided at an outer periphery of the contact structure to be electrically connected with the other end of the contact trace, an elastomer provided under the contact substrate for allowing flexibility in the interconnection and packaging of the contact structure, and a support structure provided between for supporting the contact structure, the contact substrate and the elastomer.

Abstract: An electronic component includes an insulating coating that is electrically conductive when heated disposed on a portion of a surface of a semiconductor chip; electrodes disposed on the surface of the semiconductor chip elsewhere; and inner leads extending from a lead frame and anodically bonded to the insulating coating so that the inner leads are electrically coupled to the electrodes.

Abstract: A manufacturing method of a semiconductor device for mounting an LSI bare-chip component, or a bare chip, on a printed circuit board, or a substrate, with flip-chip bonding technology, comprises a recess forming step of forming recesses on substrate pads of the substrate, an adhesive coating step of applying adhesive to a location on the substrate at which the bare chip is to be placed, a chip mounting step of placing the bare chip on the substrate while aligning the positions of the bumps formed on the chip pads of the bare chip and the substrate pads of the substrate, and an adhesive hardening step of hardening the applied adhesive. Also disclosed is a semiconductor device manufactured with the above-mentioned manufacturing method.

Abstract: A lead frame and a semiconductor package using the lead frame are disclosed in which one lead frame can be used to perform the package process regardless of the size of a chip. The size of the chip can be varied within the limit that the number of bonding pads of the chip does not exceed the number of corresponding inner leads. The lead frame includes a plurality of tie bars extended toward the center from edges of a lead frame body, a die pad supported by the tie bars on which a semiconductor chip can be bonded and a plurality of inner leads disposed around the die pad. The tie bars, the die pad and the inner leads are preferably in the same plane. The inner leads are electrically coupled with bonding pads of the chip. A plurality of outer leads respectively coupled with the inner leads and exposed outside a molded package.

Abstract: An LOC die assembly includes a die dielectrically adhered to the underside of a lead frame. The active surface of the die underlying the attached lead frame is coated with a polymeric material such as polyimide. The underside of the lead frame overlying the die is coated with a layer of soft material, such as silver, which has a lower hardness than the coating on the active surface for absorbing point stresses. Penetration of stacked filler particles into the soft material reduces point stresses on the active die surface and disadhesion stresses on the lead frame components.

Abstract: First, a reference point on a die pad and a leadframe tip arrangement line are set. A plurality of isosceles triangles having the same base length are set so that their apices are located at the reference point. A given number of isosceles triangles are arranged inside the leadframe tip arrangement line by adjusting the base length. The base length of the isosceles triangles is employed as a uniform lead pitch, and a uniform lead width is then determined. The base length of the isosceles triangles is calculated by using the successive bisection algorithm.

Abstract: A thin enhanced TAB BGA package includes an IC chip, a substrate having a center opening and one side laid with a metallic circuitry which has a plurality of inner leads extending to the center opening, a plurality of metallic solder balls attached to the substrate at one side and coupling with the metallic circuitry, and a heat dissipating member adhering partly to the a side of the chip and partly to the substrate for heat dissipating, positioning and supporting the IC chip and the substrate. The IC chip has a another side exposed to ambience to add heat dissipating effect. The heat dissipating member has about same thickness as the substrate. Hence the ball grid array package may be made of a small size and thin thickness. The adhering of heat dissipating member to the chip and substrate may be done at the same process of bonding the inner leads to the IC chip. Thus the thin enhanced TAB BGA package of this invention may be produced at low cost without additional equipment or process.

Abstract: The present invention provides for a semiconductor device that facilitates optical recognition to prevent poor wire bonding from occurring. The semiconductor device associated with the present invention comprises a semiconductor chip (20) having a plurality of electrodes and a lead (16) comprising an inner lead portion (16a) connected to each of the electrodes with a wire (24) and an outer lead portion (16b) providing an external terminal. The inner lead portion (16a) is formed with a groove (18) providing a center index portion at a center along its width in a bonding area of the wire (24).

Abstract: System modules are described which include a stack of interconnected semiconductor dies. The semiconductor dies are interconnected by micro bump bonding of coaxial lines that extend through the thickness of the various dies. The coaxial lines also are selectively connected to integrated circuits housed within the dies. In one embodiment, a number of memory dies are interconnected in this manner to provide a memory module.