Abstract: A memory card comprising a leadframe having a plurality of contacts, at least one die pad, and a plurality of conductive traces extending from respective ones of the contacts toward the die pad. Also included in the leadframe are at least two bumpers. Attached to the die pad is a semiconductor die which is electrically connected to at least one of the traces. A body defining at least two corner regions at least partially encapsulates the leadframe and the semiconductor die such that the contacts are exposed in a bottom surface defined by the body, and the bumpers are located at respective ones of the corner regions thereof.

Abstract: A substrate is electrically connected with an electrical device mounted on the substrate. A ball bond is formed between a first end of a wire and a bonding pad of the substrate. A reverse-motion loop is formed within the wire. A bond is formed between a second end of the wire and a bonding pad of the electrical device.

Abstract: A semiconductor device has a sealing body formed of an insulating resin and a semiconductor chip positioned within the sealing body. A gate electrode and a source electrode are on a first main surface of the semiconductor chip and a back electrode (drain electrode) is on a second main surface thereof. An upper surface of a portion of a drain electrode plate that projects in a gull wing shape is exposed from the sealing body and a lower surface thereof is connected to the back electrode through an adhesive. A gate electrode plate projects in a gull wing shape on an opposite end side of the sealing body and is connected to the gate electrode within the sealing body. A source electrode plate projects in a gull wing shape on the opposite end side of the sealing body and is connected to the source electrode within the sealing body.

Abstract: A chip package including a carrier having an opening, a first chip, bumps, a second chip, bonding wires, a first adhesive layer and a molding compound is provided. The first chip and the second chip are disposed at two opposite side of the carrier. The bumps are disposed between the carrier and a first active surface of the first chip to electrically connect with the first chip and the carrier. The bonding wires pass through the opening of the carrier and are electrically connected with the carrier and the second chip. The first adhesive layer adhered between the first active surface of the first chip and the carrier includes a first B-staged adhesive layer adhered on the first active surface of the first chip and a second B-staged adhesive layer adhered between the first B-staged adhesive layer and the carrier.

Abstract: A semiconductor die featuring vertical rows of bonding pad structures is disclosed. The rows of bonding pad structures are located vertically in the Y direction, or traversing the width of the semiconductor die. A vertical row of bonding pad structures is located on each side of the semiconductor die while a third vertical row of bonding pad structures is located in the center of the semiconductor die. A first set of wire bonds connect each bonding pad structure located on the sides of the semiconductor die to a conductive lead structure located on a ceramic package. A second set of wire bonds connect each bonding pad structure located in the center of the semiconductor die to a lead on chip (LOC) structure located on the semiconductor die.

Abstract: A flip chip mounted semiconductor device package having a dimpled leadframe is disclosed. The semiconductor device package includes a leadframe having a plurality of source dimples and a gate dimple, and a semiconductor die having a plurality of source contact areas and a gate contact area corresponding to the leadframe source dimples and gate dimple respectively, the semiconductor die being flipped onto the leadframe such that cured conductive epoxy provides electrical and mechanical contact between the plurality of source contact areas and the plurality of source dimples, and the gate contact area and the gate dimple.

Abstract: The present invention proposes a multi-chip semiconductor device having leads and a method for fabricating the same. The method includes the steps of: providing a substrate having a plurality of connection pads disposed on a surface thereof; mounting a plurality of semiconductor chips on the surface of the substrate, and electrically connecting the semiconductor chips to the surface of the substrate; forming an encapsulant on the substrate to encapsulate the semiconductor chips and expose the connection pads to form a package unit; and providing a lead frame having a plurality of leads, and electrically connecting the connection pads exposed from the package unit to the leads of the lead frame to form a multi-chip semiconductor device having leads, thereby forming a multi-chip semiconductor device having leads.

Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line and a filler, a connection joint that electrically connects the routing line and the pad, an encapsulant and an insulative base. The routing line contacts the filler and extends laterally beyond the filler, and the filler contacts the insulative base in an aperture that extends through the insulative base.

Abstract: A chip package structure including a chip, a lead frame, first bonding wires and second bonding wires is provided. The chip has an active surface, first bonding pads and second bonding pads, wherein the first bonding pads and the second bonding pads are disposed on the active surface. The chip is fixed below the lead frame, and the lead frame includes inner leads and bus bars. The inner leads and the bus bars are disposed above the active surface of the chip, and the bus bars are located between the inner leads and the corresponding first bonding pads. The first bonding wires respectively connect the first bonding pads and the bus bars. The second bonding wires respectively connect the bus bars and a part of the inner leads. The third bonding wires respectively connect the second bonding pads and the other of the inner leads.

Abstract: A semiconductor package using copper wires and a wire bonding method for the same are proposed. The package includes a carrier having fingers and a chip mounted on the carrier. The method includes implanting stud bumps on the fingers of the carrier and electrically connecting the chip and the carrier by copper wires with one ends of the copper wires being bonded to bond pads of the chip and the other ends of the copper wires being bonded to the stud bumps on the carrier. The implanted stud bumps on the carrier improve bondability of the copper wires to the carrier and thus prevent stitch lift. With good bonding, residues of copper wires left behind after a bonding process have even tail ends and uniform tail length to enable fabrication of solder balls of uniform size, thereby eliminating a conventional step of implanting stud bumps on the bond pads of chips and preventing ball lift from occurring.

Abstract: The present invention provides flip-chip packaging for optically interactive devices such as image sensors and methods of assembly. In a first embodiment of the invention, conductive traces are formed directly on the second surface of a transparent substrate and an image sensor chip is bonded to the conductive traces. Discrete conductive elements are attached to the conductive traces and extend below a back surface of the image sensor chip. In a second embodiment, a secondary substrate having conductive traces formed thereon is secured to the transparent substrate. In a third embodiment, a backing cap having a full array of attachment pads is attached to the transparent substrate of the first embodiment or the secondary substrate of the second embodiment. In a fourth embodiment, the secondary substrate is a flex circuit having a mounting portion secured to the second surface of the transparent substrate and a backing portion bent over adjacent to the back surface of the image sensor chip.

Abstract: An integrated circuit package system includes an integrated circuit package having a downset terminal lead, a planar recessed lead surface of the downset terminal lead, and an attached integrated circuit over the planar recessed lead surface.

Abstract: The present invention provides a flexible substrate for a package of a die which has an active surface and a plurality of first bond pads arranged in a form of a row and formed on the active surface. The flexible substrate includes a flexible insulating film and a plurality of first leads formed on the flexible insulating film. Each of the first leads corresponds to one of the first bond pads and has a respective first body portion, a respective first bond portion and a respective first extension portion. For each of the first leads, the width of the first bond portion is larger than those of the first body portion and the first extension portion.

Abstract: A semiconductor package is disclosed. In one embodiment, the semiconductor package includes a leadframe including a chip position and a plurality of leadfingers. Each leadfinger includes a cutout in an inner edge providing a chip recess. The semiconductor package further includes a semiconductor chip located in the chip recess. The semiconductor chip has an active surface with a plurality of chip contact pads on each of which an electrically conductive bump is disposed. The inner portions of the leadfingers protrude into the chip position and are electrically connected to the chip contact pads by electrically conductive bumps.

Abstract: The present invention provides a method of manufacturing a semiconductor device in which a plurality of wires are connected to the same electrode on a semiconductor chip, the method making it possible to inhibit an increase in electrode area. First, ball bonding is performed to compressively bond a first ball to an electrode on a semiconductor chip to form a first connection portion. Wedge bonding is then performed on an inner lead. Subsequently, ball bonding is performed to compress a second ball against the first connection portion from immediately above to bond the second ball to form a second connection portion. Wedge bonding is then performed on the inner lead.

Abstract: A semiconductor die has a bonding pad for a MOSFET such as a power MOSFET and a separate bonding pad for ESD protection circuitry. Connecting the bonding pads together makes the ESD protection circuitry functional to protect the MOSFET. Before connecting the bonding pads together, the ESD protection circuitry and/or the MOSFET can be separately tested. A voltage higher than functioning ESD protection circuitry would permit can be used when testing the MOSFET. A packaging process such as wire bonding or attaching the die to a substrate in a flip-chip package can connect the bonding pads after testing.

Abstract: A semiconductor device includes: a semiconductor substrate having an active face; a first electrode provided on or above the active face; an external connection terminal provided on or above the active face and electrically connected to the first electrode; and a connection terminal provided on or above the active face of the semiconductor substrate.

Abstract: Fabrication of a semiconductor package includes placing a conductive material on a protrusion from a leadframe to form a first assembly, forming a non-conductive mask about the protrusion, and placing a die on the first assembly, the die having an active area. Fabrication can further include reflowing the conductive material to form a second assembly such that a connection extends from the die active area, through the conductive material, to the protrusion. A semiconductor package includes a leadframe having a protrusion, a conductive material reflowed to the protrusion, and a die having an active area coupled to the protrusion by the reflowed solder.

Abstract: A flip chip semiconductor package is disclosed according to the present invention, the flip chip semiconductor package comprises a chip that is mounted on and electrically connects to a leadframe via a plurality of solder bumps by means of flip chip, and an encapsulate that encapsulates the chip, the plurality of solder bumps, and the leadframe, wherein, the leadframe further comprises a plurality of leads and a ground plane that is located between the plurality of leads, and also a slit is formed on the ground plane, and then a molding compound that makes up the encapsulant should be capable of filling within the slit, thus to enhance the adhesion between the ground plane and the encapsulant, and then avoid delamination between the ground plane and the encapsulant in subsequent thermal cycle processes, thereby increasing the reliability of fabricated products.

Abstract: A chip package structure mainly including a substrate, a chip and a lead frame is provided. The chip is disposed on the substrate, and is electrically connected to the chip by flip-chip or wire-bonding technique. The chip is electrically connected to the lead frame through a redistribution layer on the substrate. Therefore, a problem that the bonding wires may collapse due to a longer distance between the chip and the lead frame may be resolved, thus improving the yield rate thereof.

Abstract: A leadframe-based semiconductor package and a fabrication method thereof are provided. The leadframe-based semiconductor package includes a chip implanted with a plurality of first and second conductive bumps thereon, and a leadframe having a plurality of leads. The first conductive bumps are bonded to the leads to electrically connect the chip to the leadframe. The chip, the first and second conductive bumps, and the leadframe are encapsulated by an encapsulant, with bottom ends of the second conductive bumps and bottom surfaces of the leads being exposed from the encapsulant. This allows the second conductive bumps to provide additional input/output electrical connections for the chip besides the leads.

Abstract: A semiconductor chip assembly includes a semiconductor chip that includes a conductive pad, a conductive trace that includes a routing line, a bumped terminal and a filler, a connection joint that electrically connects the routing line and the pad, and an encapsulant. The routing line contacts the bumped terminal and the filler and extends laterally beyond the bumped terminal and the filler, and the filler contacts the bumped terminal in a cavity that extends through the bumped terminal.

Abstract: Chip-scale packages and assemblies thereof and methods of fabricating such packages including Chip-On-Board, Board-On-Chip, and vertically stacked Package-On-Package modules are disclosed. The chip-scale package includes a core member of a metal or alloy having a recess for at least partially receiving a die therein and includes at least one flange member partially folded over another portion of the core member. Conductive traces extend from one side of the package over the at least one flange member to an opposing side of the package. Systems including the chip-scale packages and assemblies are also disclosed.

Abstract: A stackable integrated circuit package system includes: forming a first integrated circuit die having a small interconnect and a large interconnect provided thereon; forming an external interconnect, having an upper tip and a lower tip, from a lead frame; mounting the first integrated circuit die on the external interconnect with the small interconnect on the lower tip and below the upper tip; and encapsulating around the small interconnect and around the large interconnect with an exposed surface.

Abstract: An apparatus for wire bonding and a capillary tool thereof are provided. An exemplary embodiment of a capillary tool capable of a wire bonding comprises a body having a first internal channel of a first diameter for accommodating a flow of a conductive wire. A compressible head is connected to the body, having a second internal channel of a second diameter for accommodating the flow of the conductive wire, wherein the first diameter is fixed and the second diameter is variable, the second diameter is not more than the first diameter and a diameter the conductive wire flowed through the compressible head is adjustable. An integrated circuit (IC) package is also provided.

Abstract: The central region of a leadframe (101, 201, 301, 401, 501, 601, 701, 801, 901, 1001, 1101, 1201), is selectively etched to leave upright portions (104, 204, 304, 404, 504, 604, 704, 804, 904, 1004, 1104, 1204). Subsequently, during the packaging process, an integrated circuit (3) is located on the central region of the leadframe, and wires (107) are formed between the upright portions of the leadframe and contacts (5) of the integrated circuit (3), which are to be grounded. Subsequently, the wires and upright portions of the leadframe are encased in resin (116). Since the upright portions of the leadframe are encased in resin, the resin (116) is mechanically locked to the leadframe. Furthermore, any delamination that occurs between the resin (116) and the leadframe cannot propagate easily up the sides of the upright portions as far as the wires (107), so the wires (107) are unlikely to be torn from the upright portions (104, 204, 304, 404, 504, 604, 704, 804, 904, 1004, 1104, 1204).

Abstract: A packaging structure and method for a light emitting diode is provided. The present invention uses flip-chip and eutectic bonding technology to attach a LED to a thermal and electrical conducting substrate. The flip-chip packaging structure comprises a thermal and electrical conducting substrate having an insulating layer formed in an appropriate area on the top surface of the substrate and a bonding pad formed on top of the insulating layer; and a LED reversed in a flip-chip style and joined to the substrate by eutectic bonding. A first electrode of the LED is eutectically bonded to an appropriate area on the top surface of the substrate via a eutectic layer, while a second electrode of the LED is electrically connected to the bonding pad.

Abstract: This invention is directed to preventing deformation, breakage, and the like of leads in a semiconductor device, reducing the fraction of defects, and making the semiconductor device smaller and thinner. In order to accomplish these objects, in a carrier including a base having a device hole and a plurality of leads for bonding a chip, the leads are provided with thin heat-resistant films.

Abstract: A radio frequency IC tag and a manufacturing method for the same includes an IC chip on which information is stored, and an antenna for transmitting the information that is stored on the IC chip. In the antenna, a power-feeding part on which the IC chip is mounted extends along a direction in which an electric current flows. Radiation parts are formed so that the width of the radiation parts becomes wider than that of the power-feeding part with respect to the longitudinal axis of the power-feeding part. The radiation parts extend from the power-feeding part, at both sides thereof, along the direction in which the electric current flows.

Abstract: Ball grid array packages that can be stacked to form highly dense components and the method for stacking ball grid arrays are disclosed. The ball grid array packages comprise flexible or rigid substrates. The ball grid array packages additionally comprise an arrangement for the substantial matching of impedance for the circuits connected to the semiconductor devices.

Abstract: Methods of fabricating comb drive devices utilizing one or more sacrificial etch-buffers are disclosed. An illustrative fabrication method may include the steps of etching a pattern onto a wafer substrate defining one or more comb drive elements and sacrificial etch-buffers, liberating and removing one or more sacrificial etch-buffers prior to wafer bonding, bonding the etched wafer substrate to an underlying support substrate, and etching away the wafer substrate. In some embodiments, the sacrificial etch-buffers are removed after bonding the wafer to the support substrate. The sacrificial etch-buffers can be provided at one or more selective regions to provide greater uniformity in etch rate during etching. A comb drive device in accordance with an illustrative embodiment can include a number of interdigitated comb fingers each having a more uniform profile along their length and/or at their ends, producing less harmonic distortion during operation.

Abstract: Embodiments in accordance with the present invention relate to the fabrication of packages for semiconductor devices, and in particular to the use of electroplating techniques to form features on the surface of a metal lead frame. In accordance with one embodiment, electroplating is used to fabricate non-integral pin portions shaped to remain securely encapsulated within the plastic molding of the package. In accordance with another embodiment, electroplating may be used to fabricate protrusions on the underside of the lead frame for elevating the package above the PC board, thereby preserving the rounded shape of solder balls used to secure the diepad to the PC board. In accordance with yet another embodiment, electroplating may be used to fabricate raised patterns on the upper surface of the diepad for ensuring uniform spreading of adhesive used to secure the die to the diepad, thereby ensuring level attitude of the die within the package.

Abstract: A lead frame of a through-hole light emitting diode (LED) is used to carry an LED chip, and a lens is used to package the chip and a portion of the lead frame. The lead frame includes at least two leads. One lead is used to carry the chip and each of the leads is extended outward from the lens and has a positioning bump. The positioning bumps partially protrude from the lens, such that when the lead frame is disposed on a circuit board, the lead frame is positioned through the positioning bumps and aligns the lens to guide an optical axis of the through-hole LED, thereby achieving the purposes of convenient assembly, thinness, and a reduced thermal-conducting distance.

Abstract: A semiconductor device and method having high output and having reduced external resistance is reduced and improved radiating performance. A MOSFET (70) has a connecting portion for electrically connecting a surface electrode of a semiconductor pellet and a plurality of inner leads, a resin encapsulant (29), a plurality of outer leads (37), (38) protruding in parallel from the same lateral surface of the resin encapsulant (29) and a header (28) bonded to a back surface of the semiconductor pellet and having a header protruding portion (28c) protruding from a lateral surface of the resin encapsulant (29) opposite to the lateral surface from which the outer leads protrude, wherein the header (28) has an exposed surface (28b) exposed from the resin encapsulant (29); the outer leads (37), (38) are bent; and the exposed of the outer leads (37), (38) are provided at substantially the same height.

Abstract: A method for making a semiconductor die package is disclosed. In some embodiments, the method includes using a leadframe structure including at least one lead structure having a lead surface. A semiconductor die having a first surface and a second surface is attached to the leadframe structure. The first surface of the semiconductor die is substantially planar to the lead surface and the second surface of the semiconductor die is coupled to the leadframe structure. A layer of conductive material is formed on the lead surface and the first surface of the semiconductor die to electrically couple the at least one lead structure to the semiconductor die.

Abstract: A vertical conduction power electronic device package and corresponding assembly method comprising at least a metal frame suitable to house at least a plate or first semiconductor die having at least a first and a second conduction terminal on respective opposed sides of the first die. The first conduction terminal being in contact with said metal frame and comprising at least an intermediate frame arranged in contact with said second conduction terminal.

Abstract: Invertible microfeature device packages and associated methods for manufacture and use are disclosed. A package in accordance with one embodiment includes a microfeature device having a plurality of device contacts, and a conductive structure electrically connected to the contacts. The conductive structure can have first and second package contacts accessible for electrical coupling to at least one device external to the package, with the first package contacts accessible from a first direction and the second package contacts configured to receive solder balls and accessible from a second direction opposite the first. An encapsulant can be disposed adjacent to the microfeature device and the conductive structure and can have apertures aligned with the second package contacts to contain solder balls carried by the second package contacts.

Abstract: In an electronic component comprising a semiconductor chip packaged in a molded part from which the lead terminals of the semiconductor chip project, a main cutting notch is formed on the obverse surface of each lead terminal before molding the molded part while leaving unnotched portions adjoining both ends of the main notch. Then, each lead terminal is cut at the main notch after molding the molded part, thereby making fewer and smaller cutting burrs occurring at the cut faces.

Abstract: Fabrication of a semiconductor package includes placing a conductive material on a protrusion from a leadframe to form a first assembly, forming a non-conductive mask about the protrusion, and placing a die on the first assembly, the die having an active area. Fabrication can further include reflowing the conductive material to form a second assembly such that a connection extends from the die active area, through the conductive material, to the protrusion. A semiconductor package includes a leadframe having a protrusion, a conductive material reflowed to the protrusion, and a die having an active area coupled to the protrusion by the reflowed solder.

Abstract: A semiconductor device includes a base plate, at least one first conductive layer carried by the base plate, and a semiconductor constructing body formed on or above the base plate, and having a semiconductor substrate and a plurality of external connecting electrodes formed on the semiconductor substrate. An insulating layer is formed on the base plate around the semiconductor constructing body. A plurality of second conductive layers are formed on the insulating layer and electrically connected to the external connecting electrodes of the semiconductor constructing body. A vertical conducting portion is formed on side surfaces of the insulating film and base plate, and electrically connects the first conductive layer and at least one of the second conductive layers.

Abstract: A semiconductor package includes a substrate having a plurality of lead fingers. A plurality of stud bumps is attached to the plurality of lead fingers. A die having a plurality solder bumps is provided. The plurality of solder bumps is attached to the plurality of stud bumps to form a plurality of electrical connections and provide controlled collapse of the plurality of solder bumps. An encapsulant encapsulates the die, the electrical connections, and the plurality of lead fingers to expose a lower surface of the plurality of lead fingers. The plurality of stud bumps may include a plurality of clusters of stud bumps.

Abstract: An improved wire bond is provided with the bond pads of semiconductor devices and the lead fingers of lead frames or an improved conductive lead of a TAB tape bond with the bond pad of a semiconductor device. More specifically, an improved wire bond is described wherein the bond pad on a surface of the semiconductor device comprises a layer of copper and at least one layer of metal and/or at least a barrier layer of material between the copper layer and one layer of metal on the copper layer to form a bond pad.

Abstract: A semiconductor device which permits reduction in the number of pins and in size thereof is provided.

Abstract: A semiconductor die package. It includes (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die. The molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.

Abstract: A die metallization and bump design/arrangement, and a die-package interface metallization and bump design/arrangement are described herein.

Abstract: A chip scale package is disclosed that includes a semiconductor die further comprising an array of power buses electrically coupled to a high power integrated circuit, and a plurality of Under Bump Metallization (UBM) multi-layer power buses disposed parallel to one another and spanning substantially across the entire length of the semiconductor die. The plurality of multi-layer UBM power buses, electrically coupled to the array of power buses, further includes a thick metal layer configured in a geometric shape that have interconnection balls completely posited thereupon.

Abstract: An integrated circuit package system that includes: providing a substrate with a protective coating; attaching a labeling film to a support member in a separate process; joining the protective coating and the labeling film; and dicing the substrate, the protective coating, and the labeling film to form the integrated circuit package system.

Abstract: Provided is a semiconductor package accomplishing a fan-out structure through wire bonding in which a pad of a semiconductor chip is connected to a printed circuit board through wire bonding. A semiconductor package can be produced without a molding process and can be easily stacked on another semiconductor package while the appearance cracks and the warpage defects can be prevented.

Abstract: An integrated circuit device comprising an integrated circuit die having a plurality of bond pads that are selectively connected to a plurality of inner leads of a leadframe. At least two bond pads are connected to at least one of the inner leads, and/or at least two inner leads are connected to at least one of bond pads with a single bond wire. A single bond wire is ball or wedge bonded to a first bond pad or inner lead and subsequently wedge bonded to one or more second bond pads or inner leads, then it is connected to a third or last bond pad or inner lead. The single bond wire requires only one connection area at each of the bond pad(s) and/or inner lead(s). The bond pad(s) of the die and/or inner lead(s) of the leadframe are thereby electrically connected together by the single bond wire.

Abstract: A package system for integrated circuit (IC) chips and a method for making such a package system. The method uses a solder-ball flip-chip method for connecting the IC chips onto a lead frame that has pre-formed gull-wing leads only on the source/gate side of the chip. A boschman molding technique is used for the encapsulation process, leaving exposed land and die bottoms for a direct connection to a circuit board. The resulting packaged IC chip has the source of the chip directly connected to the lead frame by solder balls. As well, the drain and gate of the chip are directly mounted to the circuit board without the need for leads from the drain side of the chip.