Abstract: Methods of fabricating comb drive devices utilizing one or more sacrificial etch-buffers are disclosed. An illustrative fabrication method may include the steps of etching a pattern onto a wafer substrate defining one or more comb drive elements and sacrificial etch-buffers, liberating and removing one or more sacrificial etch-buffers prior to wafer bonding, bonding the etched wafer substrate to an underlying support substrate, and etching away the wafer substrate. In some embodiments, the sacrificial etch-buffers are removed after bonding the wafer to the support substrate. The sacrificial etch-buffers can be provided at one or more selective regions to provide greater uniformity in etch rate during etching. A comb drive device in accordance with an illustrative embodiment can include a number of interdigitated comb fingers each having a more uniform profile along their length and/or at their ends, producing less harmonic distortion during operation.

Abstract: A system and method for encapsulating an integrated circuit package. More specifically, a system and method for encapsulating a board-on-chip package is described. A strip of material is disposed on one end of the slot in the substrate to control the flow of the molding compound during the encapsulation process.

Abstract: A semiconductor chip package includes a semiconductor chip having a through hole extending there through from an active first surface to an inactive second surface. A first conductive pad at least partially surrounds the through hole on the active first surface of the semiconductor chip. The package also includes a printed circuit board having a first surface attached to the inactive second surface of the semiconductor chip, and a second conductive pad aligned with the through hole of the semiconductor chip. A conductive material fills the through hole and contacts the first and second conductive pads.

Abstract: A semiconductor device assembly having a lead frame and a semiconductor die configured to be attached to each other is disclosed. An adhesive is applied at room temperature through a stencil to the lead frame. The semiconductor die is urged against the adhesive to effect the attachment between the semiconductor device and the lead frame. The adhesive preferably is from about 75 percent to about 95 percent isobutyl acetal diphenol copolymer and from about 25 percent to about 5 percent, respectively, of titanium oxide.

Abstract: A short-prevented lead frame and a method for fabricating a semiconductor package with the lead frame are proposed, wherein each lead of the lead frame is formed with a thickness-reduced portion at a peripheral position of the lead frame, allowing thickness-reduced portions of adjacent leads to be arranged in a stagger manner. This stagger arrangement significantly increases pitches between the neighboring thickness-reduced portions of leads. Therefore, during a singulation process as to cut through the leads, lead bridging and short-circuiting between adjacent leads caused by cut-side burrs can be prevented from occurrence, whereby singulation quality and product yield and reliability are effectively improved.

Abstract: Multi-terminal field effect devices comprising a chalcogenide material. The devices include a first terminal, a second terminal and a field effect terminal. Application of a gate signal to the field effect terminal modulates the current passing through the chalcogenide material between the first and second terminals and/or modifies the holding voltage or current of the chalcogenide material between the first and second terminals. The devices may be used as interconnection devices in circuits and networks to regulate current flow between circuit or network elements.

Abstract: Protective structures for bond wires or other intermediate conductive elements of a semiconductor device assembly cover the intermediate conductive elements without covering a substantial portion of a semiconductor device from which the intermediate conductive elements extend. In addition to coating at least portions of one or more intermediate conductive elements, the protective structure may include a fence which is configured to receive a semiconductor device. Such a fence may be formed integrally with the remainder of the protective structure or a separately formed member. The protective structures may be formed from a photopolymer material which has been at least partially cured, for example, by stereolithography processes. Accordingly, the protective structures may include a single layer or a plurality of superimposed, contiguous, mutually adhered layers.

Abstract: An image sensor device includes a QFN type leadframe having a central die attach flag and an outer bonding pad area having a plurality of bonding pads. A sensor IC is attached to the flag. The IC has a first surface with an active area and a peripheral bonding pad area that includes bonding pads. Wires are wirebonded to respective ones of the IC bonding pads and corresponding ones of the leadframe bonding pads, thereby electrically connecting the IC and the leadframe. Stud bumps are formed on the first surface of the IC and a transparent cover is disposed over the IC active area and resting on the stud bumps. The cover allows light to pass therethrough onto the IC active area. A mold compound is formed over the leadframe, wirebonds and a peripheral portion of the cover.

Abstract: The semiconductor device includes a semiconductor element having an electrode formed on a surface thereof, and a metal wiring formed on the surface of the semiconductor element and electrically connected to the electrode. The metal wiring has an external electrode portion functioning as an external electrode. A thickness of the external electrode portion is greater than that of a non-electrode portion of the metal wiring, i.e., a portion of the metal wiring other than the external electrode portion.

Abstract: A technique is provided for dissipating heat from an integrated circuit within a package. A thermally conductive strip may be installed between an integrated circuit and a substrate before packaging. The package is formed from molded epoxy formed around the integrated circuit and substrate with a portion of the thermally conductive strip extending beyond the confines of the package. Heat is conducted from the integrated circuit through the thermally conductive strip to the environment surrounding the package. A thermally conductive strip may be installed within a package by an adhesive or other mechanically means. A thermally conductive strip may be comprised of a metallic foil or other thermally conductive material.

Abstract: A leadframe of a conductive material includes a central region to accommodate a chip and a plurality of connecting fingers extending at least from one side in the direction of the central region, a contact region being provided adjacent to the central region on at least some of the connecting fingers. The course of the connecting fingers is such that a sectional face in an arbitrary imaginary cross-section at right angles to the main face of the leadframe has leadframe material. In such a case, it is attempted to keep cross-sections in a component without leadframe material as small as possible.

Abstract: A substrate and a fabrication method thereof are proposed, with at least a check point being formed on the substrate. Prior to wire bonding and/or molding processes, cleanness of the substrate (cleaned by plasma) is determined according to color variation of the check point, so as to allow only cleaned and contamination-free substrates to be subsequently formed with bonding wires and encapsulants thereon. Thereby, qualities of wire-bonded electrical connection and encapsulant adhesion for the substrate can be assured, which helps prevent the occurrence of delamination between the encapsulant and the substrate. Moreover, the check point formed on the substrate is made during general substrate fabrication by using current equipment and technique, and in a manner as not to interfere with trace routability on the substrate; thereby, costs and complexity of substrate fabrication would not undesirably increased.

Abstract: A lead pin with an Au—Ge based brazing material including a lead pin made of a copper-containing metal is provided. The lead pin including a joining surface to a substrate, at least the joining surface of the lead pin being plated with nickel and gold, and including an Au—Ge based brazing material being fused on top of the gold plating, wherein the lead pin after plated with nickel is subjected to heat-treatment and then plated with gold to fuse the brazing material.

Abstract: A high frequency semiconductor module, includes: a semiconductor chip having top and bottom surfaces; a semiconductor element merged in the semiconductor chip; a ground pad of the semiconductor element disposed on the top surface; a metal layer configured to connect to the ground pad and extend to sidewalls of the semiconductor chip; a ground metal arranged on a surface of a mounting substrate; and a conductive material formed on the ground, configured to connect the metal layer and the ground metal.

Abstract: A radio frequency identification (RFID) inlay includes a conductive connection electrically connecting an antenna to strap leads that are coupled to an RFID chip. The conductive connection may include conductive bumps attached to the strap, and/or may include conductive traces, such as a conductive ink traces. The conductive connections provide a convenient, fast, and effective way to operatively couple antennas and straps. The RFID inlay may be part of an RFID label or RFID tag.

Abstract: A wafer interposer assembly and a system for building the same are disclosed. The wafer interposer assembly includes a semiconductor wafer (10) having a die (11) and a redistribution layer pad (13) electrically connected to the die (11). An epoxy layer (20) is deposited on the surface of the redistribution layer pad (13) and the die (11). An interposer pad (50) is positioned in an opening (40) in the epoxy layer (20) in electrical contact with the redistribution layer pad (13).

Abstract: A bumped semiconductor component includes bumped contacts, a semiconductor die having die contacts, and a redistribution circuit having conductors for establishing electrical communication between the die contacts and the bumped contacts. The redistribution circuit also includes test contacts in electrical communication with the die contacts and with the bumped contacts. The test contacts allow the die to be tested without electrical engagement of the bumped contacts. The bumped semiconductor component can be contained on a wafer, or can be a singulated component such as a flip chip package. A test system includes the bumped semiconductor component, and an interconnect having contacts configured to electrically engage the test contacts without interference from the bumped contacts. If the test contacts are aligned with the die contacts, the same interconnect can be used to test the bare die as well as the bumped component.

Abstract: A semiconductor component includes a chip on board leadframe, a semiconductor die back bonded and wire bonded to the leadframe, an encapsulant on the die and an area array of terminal contacts on the leadframe. The leadframe includes leadfingers, interconnect bonding sites for wire bonding the die, terminal bonding sites for the terminal contacts, and bus bars which electrically connect selected leadfingers to one another. The interconnect bonding sites are located on the leadframe relative to the bus bars such that shorting to the bus bars by wire interconnects is eliminated. A method for fabricating the component includes the steps of attaching the die to the leadframe, bonding the wire interconnects to the die and to the interconnect bonding sites, forming the encapsulant, and then forming the terminal contacts on the terminal bonding sites.

Abstract: A method of making a semiconductor device is provided. The method includes the following steps. First, a semiconductor chip is mounted on a lower conductor, with first solder material applied between the chip and the lower conductor. Then, an upper conductor is placed on the chip, with second solder material applied between the chip and the upper conductor. Then, the first and the second solder materials are heated up beyond their respective melting points. Finally, the first and the second solder materials are allowed to cool down, so that the first solder material solidifies earlier than the second solder material.

Abstract: A frame for a semiconductor package has die-pads supported with suspending leads of individual lead frames. Semiconductor devices are arranged on the die-pads. These semiconductor devices are collectively molded with molding compound, and then the collectively molded semiconductor packages are cut into individual packages by means of a dicing saw. In the frame, suspending leads are formed into fish tails, wherein at least one of a longitudinal grid-lead and a transverse grid-lead is eliminated within areas enclosed with fish tails of the suspending leads. Accordingly, whether an R-shape generated by producing the frame by etching is large or small, the existence of metal pieces at the edges of the semiconductor packages is substantially prevented.

Abstract: A lead frame structure includes: at least a die pad for mounting a semiconductor chip thereon; a plurality of suspension members mechanically connected with the die pad; and a plurality of supporting members. Each supporting member has a connection region mechanically connected with each of the plurality of suspension members for mechanically supporting the at least die pad via the plurality of suspension pins. The connection region of the supporting member has a penetrating opening portion which provides a mechanical flexibility to the connection region and which allows the connection region to be deformed toward the suspension member upon application of a tensile stress to the suspension member in a down-set process.

Abstract: A semiconductor device comprising a semiconductor chip with plural electrodes arranged on a main surface thereof, plural leads electrically connected respectively to the plural electrodes on the semiconductor chip, and a resin sealing body which seals the semiconductor chip and the plural leads, wherein the plural leads include first leads and second leads adjacent to the first leads, the first leads having first external connections exposed from a mounting surface of the resin sealing body and positioned near a side face of the resin sealing body, the second leads having second external connections exposed from the mounting surface of the resin sealing body and positioned closer to the semiconductor chip with respect to the first external connections. The first and second leads are fixed to the semiconductor chip. The semiconductor device is suitable for a multi-pin structure and the manufacturing yield thereof is improved.

Abstract: A method for producing a die package is disclosed. A bumped die comprises solder bumps mounted to a leadframe including a first lead comprising a first locating hole and a second lead comprising a second locating hole. The solder bumps are present in the first and second locating holes, and a molding material is formed around the die.

Abstract: Embodiments of the invention are directed to semiconductor die packages. One embodiment of the invention is directed to a semiconductor die package including, (a) a semiconductor die including a first surface and a second surface, (b) a source lead structure including protruding region having a major surface, the source lead structure being coupled to the first surface, (c) a gate lead structure being coupled to the first surface, and (d) a molding material around the source lead structure and the semiconductor die, where the molding material exposes the second surface of the semiconductor die and the major surface of the source lead structure.

Abstract: A semiconductor device is formed by laminating two semiconductor chips with the rear surfaces thereof provided face to face. Each semiconductor chip is provided with an outer lead for clock enable to which the clock enable signal and chip select signal are individually input. On the occasion of making access to one semiconductor chip, the other semiconductor chip is set to the low power consumption mode by setting the clock enable signal and chip select signal to the non-active condition.

Abstract: In a semiconductor device, each of the leads is provided with guided-surfaces that are inclined surfaces and each of the bumps is provided with a recess that has guide-surfaces formed by inclined surfaces. The leads are smoothly guided toward the centers of the upper surfaces of the bumps with the aides of the inclined surfaces formed on the leads and bumps, so that the attitude of the leads is corrected and the leads are snugly brought into the recess and prevented form falling off of the bump.

Abstract: In a chip scale package, a chip is mounted in a cavity formed in a leadframe. The leadframe includes a plurality of leads that radiate from a heat dissipating part located in the cavity. Each lead extends from a thinner portion of inner lead in the cavity to a thicker portion of outer lead outside the cavity. The chip includes a plurality of bonding pads on which is respectively formed a layer of connecting material. The chip is attached on the heat dissipating material, and via the layer of connecting material, is electrically connected to the inner leads by thermal pressing. Via molding, the chip is encapsulated in the leadframe. The achieved package has a dimensional size that is approximately equal to that of the leadframe with an improved thermal dissipation.

Abstract: A thermally enhanced, chip-scale, Lead-on-Chip (“LOC”) semiconductor package includes a substrate having a plurality of metal lead fingers in it. A semiconductor chip having an active surface with a plurality of ground, power, and signal connection pads thereon is mounted on an upper surface of the substrate in a flip-chip electrical connection with the lead fingers. A plurality of the ground and/or the power connection pads on the chip are located in a central region thereof. Corresponding metal grounding and/or power lands are formed in the substrate at positions corresponding to the centrally located ground and/or power pads on the chip. The ground and power pads on the chip are connected to corresponding ones of the grounding and power lands in the substrate in a flip-chip connection, and a lower surface of the lands is exposed to the environment through a lower surface of the semiconductor package for connection to an external heat sink.

Abstract: A chip device including a leadframe that includes source and gate connections, a bumped die including solder bumps on a top side that is attached to the leadframe such that the solder bumps contact the source and gate connections, and a copper clip attached to the backside of the bumped die such that the copper clip contacts drain regions of the bumped die and a lead rail. The chip device is manufactured by flip chipping a bumped die onto the leadframe and placing the copper clip on a backside of; the trench die such that the backside of the trench die is coupled to the lead rail. The process involves reflowing the solder bumps on the bumped die and solder paste that is placed between the copper clip and the backside of the bumped die.

Abstract: A device, such as a radio frequency identification (RFID) inlay structure for an RFID tag or label, includes a microstructure element, with leads coupling the microstructure element to other electrical or electronic components of the device. The leads may be electroless-plated leads, and may contact connectors of the microstructure element without the need for an intervening planarization layer.

Abstract: A semiconductor device comprises a plurality of semiconductor chips stacked in the direction of thickness. Each of the semiconductor chips includes an upper surface formed with electrodes. The semiconductor device further comprises a plurality of terminal portions disposed beside these semiconductor chips, and a plural pieces of wire for electrical connection from the electrodes to respective terminal portions. Each of the terminal portions is at an elevation lower than the highest electrodes, and higher than the lowest electrodes.

Abstract: A chip-type semiconductor light-emitting device includes a semiconductor light-emitting chip connected to a pair of electrodes formed on a substrate. The semiconductor light-emitting chip is molded, together with respective parts of the electrodes, by resin. The electrode has a layered structure having a Cu layer, an Ni layer and an Au layer in that order from the lowermost layer, to have a step formed inside the mold by changing the wall thickness of the Cu layer.

Abstract: Disclosed is a ball grid array package with stacked center pad chips, which realizes a BGA package with stacked chips using center pad type semiconductor chips, and a method for manufacturing the same. The semiconductor chips are glued on each of upper and lower circuit boards, which have active surfaces facing each other; the chip pads are connected to each of the upper and lower circuit boards with gold wires; the upper and lower circuit boards are joined together with bumps interposed between them for electrical connection; the upper circuit board is included in a package mold; and the opposite ends of the lower circuit board are exposed to the lower portion of the package mold. The lower circuit board can be made of flexible insulation film. The exposed opposite ends of the lower circuit board can have solder balls formed thereon. Also, the opposite ends of the lower circuit board may be joined to a printed circuit board. Solder balls may be formed on the lower surface of the printed circuit board.

Abstract: A semiconductor device including a semiconductor chip having an electric circuit on a surface thereof, and an electrode pad formed on the surface of the semiconductor chip and which is electrically connected to the electric circuit. A conductive pattern is electrically connected to the pad, and a sealing resin covers the electric circuit and the conductive pattern. A part of the conductive pattern is exposed from the sealing resin, and a plurality of grooves are formed on the part of the conductive pattern. The plurality of grooves are disposed apart from each other and along a direction of stress of the expanding semiconductor chip. An external electrode is electrically connected to the conductive pattern. Stress of the external electrodes is thus relieved and as a result, reliability of the semiconductor device can be improved, because deterioration of the connecting quality can be prevented.

Abstract: A semiconductor package includes an upper substrate having an opening portion, a solder ball for connection between substrates arranged on the lower side of the upper substrate, a lower substrate arranged on the further lower side and having an opening portion, a solder ball for external connection connected on the lower surface of the lower substrate, and a semiconductor chip affixed on each substrate. The semiconductor chip is electrically connected to the solder ball through the opening portion of each substrate. The solder ball for connection between substrates is electrically connected to the solder ball for external connection.

Abstract: A semiconductor assembly includes a leadframe with leads having offset portions exposed at an outer surface of a material package to form a grid array. An electrically conductive compound, such as solder, may be disposed or formed on the exposed lead portions to form a grid array such as a ball grid array (“BGA”) or other similar array-type structure of dielectric conductive elements. The leads may have inner bond ends including a contact pad thermocompressively bonded to a bond pad of the semiconductor chip to enable electrical communication therewith and a lead section with increased flexibility to improve the thermocompressive bond. The inner bond ends may also be wirebonded to the bond pads. Components for and methods of forming semiconductor assemblies are included.

Abstract: Improved apparatus and methods for stacking integrated circuit packages having leads are disclosed. According to one embodiment, the leads of an integrated circuit package are exposed and provided with solder balls so that corresponding leads of another integrated circuit package being stacked thereon can be electrically connected. The stacking results in increased integrated circuit density with respect to a substrate, yet the stacked integrated circuit packages are able to still enjoy having an overall thin or low profile.

Abstract: A semiconductor integrated circuit device is provided which includes a wire having a diameter equal to or less than 30 &mgr;m, and a connected member molded by a resin. The connected member includes a metal layer including a palladium layer provided at a portion to which said wire is connected. A solder containing Pb as a main composition metal is provided at a portion outside a portion molded by the resin.

Abstract: An interconnection substrate comprises an uppermost interconnection layer having a plurality of terminal pads located at positions corresponding to a plurality of solder bumps (external connection terminals) provided on a semiconductor element which is to be mounted on the interconnection substrate. The interconnection substrate also has a metal column formed on each of the terminal pads and has a resin film covering a side surface of the metal column. The interconnection substrate further has an insulating layer formed on the uppermost interconnection layer so that a gap is formed between the insulating layer and an outer peripheral surface of the resin film.

Abstract: A semiconductor device having high output and a method of manufacturing the same are disclosed in which external resistance is reduced and radiating performance is improved.

Abstract: An electrically isolated and thermally conductive double-sided pre-packaged IC component, stamped lead members, drain pads, source pads, gate runner, and a MOSFET, IGBT, etc. are positioned between a pair of ceramic substrate members. Layers of solderable cooper material are directly bonded to the inner and outer surfaces of the substrate members.

Abstract: A semiconductor device includes an electrically insulating board; conductive interconnections formed on a first face of the board and on a second face opposite to the first face; a semiconductor chip fixed to the board through at least the interconnections on the first face, said semiconductor chip having a semiconductor element electrically connected to the interconnections; a conductive bump formed on the second face of the board and electrically connected to the interconnections on the second face; and a first through-hole passing through the board to ventilate at least a part of the region between the board and the semiconductor chip.

Abstract: An insulating sheet which connects a semiconductor chip and a wiring substrate is provided between the semiconductor chip and the wiring substrate. The insulating sheet has windows therethrough at positions corresponding to those of connection pads of the wiring substrate and has leads, one end of each of the leads being fixed on the sheet and the other end of each of the leads protruding from the opposite surface of the sheet through a window. Each of solder balls of the semiconductor chip is connected to the fixed one end of one of the leads, and each of the connection pads is connected to the other end of each of the leads to electrically connect the semiconductor chip and the wiring substrate.

Abstract: A semiconductor device having electrodes formed along a peripheral part thereof in a staggered arrangement of lines including inside-line, central-line and outside-line electrodes. The inside-line electrodes are octagonal shaped with hypotenuses on the central-line electrode and the pellet sides thereof. The central-line electrodes are octagonal shaped with hypotenuses on the inside-line and outside-line electrode sides thereof. The maximum width of outside-line electrode wires between the hypotenuses of adjacent inside-line and central-line electrodes depends on the distance between centers of the inside-line and central-line electrodes, minimum lengths of the inside-line and central-line electrodes and electrode protective film, and the necessary minimum conductor interval between the central-line and inside-line electrodes. The position and form of the central-line and inside-line electrodes are determinable based on the given relationship and the necessary value of current.

Abstract: To make it possible to mount micro ball electrodes of a semiconductor device of CSP (chip size package) or BGA (ball grid array) type, to reduce the diameter of the electrode forming hole, to make fine the pattern of the wiring film, to improve precision of the external accuracy, and to facilitate production. A plurality of wiring films (4) are formed on one surface part of the base (5) of an insulating resin such that said film surface is positioned flush with said base surface and at least part of the wiring films overlap the electrode forming hole (8) of said base, each electrode forming hole (8) is buried with an electrically conductive material and the external electrode (6) projecting to the opposite side of the wiring film is formed, and the semiconductor chip (14) is flip-chip-connected onto said one surface of the base (5).

Abstract: A semiconductor package comprising a leadframe which includes a die paddle having an opening formed therein. In addition to the die paddle, the leadframe includes a plurality of leads, at least one of which is disposed in spaced relation to the die paddle. The remaining leads are attached to the die paddle and extend therefrom. Electrically connected to the die paddle is the source terminal of a semiconductor die which also includes a gate terminal and a drain terminal. The gate terminal is itself electrically connected to the at least one of the leads disposed in spaced relation to the die paddle. A package body at least partially encapsulates the die paddle, the leads, and the semiconductor die such that portions of the leads and the drain terminal of the semiconductor die are exposed in the package body.

Abstract: Disclosed is a method of making a mold lock for bonding leadframe-to-plastic in an IC package. Steps include providing niches from opposing sides of the leadframe. The opposing niches are arranged such that an aperture and a mechanical key are formed within the leadframe material by the partial intersection of the niches. The key is encapsulated with mold compound to form a lock. An IC package mold lock in a leadframe is also disclosed, the lock having an aperture, a key, and mold compound encapsulating the key. Additionally, an IC package employing the leadframe-to-plastic lock is disclosed.

Abstract: A semiconductor device is provided which is highly reliable and operable at fast speed and low noises. In this semiconductor device, there are provided a power wiring section 1003a, a ground wiring section 1003b and a signal wiring section 1003c are formed on one level. The power wiring section or the ground wiring section is formed adjacently on both sides of at least one part of the signal wiring section.

Abstract: The semiconductor device includes a semiconductor element having an electrode formed on a surface thereof, and a metal wiring formed on the surface of the semiconductor element and electrically connected to the electrode. The metal wiring has an external electrode portion functioning as an external electrode. A thickness of the external electrode portion is greater than that of a non-electrode portion of the metal wiring, i.e., a portion of the metal wiring other than the external electrode portion.

Abstract: A method of making an interactive information package, including an interactive information closure including a radio frequency identification device, contemplates that a microelectronics assembly be provided, and positioned on an associated substrate for positioning adjacent an inside surface of the top wall portion of the closure of the package. In one embodiment, the mounting substrate is provided in the form of a disc-shaped sealing liner for the closure. In an alternate embodiment, the mounting substrate is laminated to an associated sealing liner, with the substrate, and microelectronics assembly positioned thereon, inserted together with the sealing liner into the associated molded closure.