Abstract: A lead frame includes a die pad having a surface, a first lead post, a first lead, a second lead post, and a second lead. The first lead post has a surface coplanar with the surface of the die pad and is in a first plane. The first lead is coupled to the first lead post. The second lead post is in a second plane different from the first plane. The second lead is coupled to the second lead post.

Abstract: A light emitting diode (LED) device includes a semiconductor layer and one or more portions of a wafer on which the semiconductor layer was formed, the other portions of the wafer having been removed by an etching process. The semiconductor layer has a front surface that includes a light emitting area. The remnants of the wafer on which the semiconductor layer are disposed on the front surface of the semiconductor layer and define a trench. The trench is positioned such that the light emitting area emits light into the trench. The remnants of the wafer make the LED device more robust and the trench may reduce crosstalk with adjacent LED devices.

Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

Abstract: In a described example, an integrated circuit (IC) package includes an IC die disposed on a die attach pad; a plurality of leads electrically connected to terminals on the IC die, the leads including a base metal; and molding compound material encapsulating portions of the IC die, the die attach pads, and the plurality of leads; the plurality of leads having a solder joint reinforcement tab. The solder joint reinforcement tabs include a first side, a second side opposite to the first side, a third side, a fourth side opposite to and in parallel to the third side, a fifth side forming an end portion of the solder joint reinforcement tab, the solder joint reinforcement tabs including a solderable metal layer on the second, third and fourth sides and on portions of the fifth side.

Abstract: An apparatus includes a first die attach pad and a second die attach pad. A first die is attached to the first die attach pad and a second die is attached to the second die attach pad. The first die attach pad and the second die attach pad are separated by a gap. A first edge of the first die attach pad adjacent to the gap is thinner than a second edge of the first die attach pad. The first edge of the first die attach pad is opposite the second edge of the first die attach pad. A first edge of the second die attach pad adjacent to the gap is thinner than a second edge of the second die attach pad. The first edge of the second die attach pad is opposite the second edge of the second die attach pad.

Abstract: A semiconductor package comprises a land grid array substrate, a first VDMOSFET, a second VDMOSFET, and a molding encapsulation. The land grid array substrate comprises a first metal layer, a second metal layer, a third metal layer, a plurality of vias, and a resin. A series of drain pads at a bottom surface of the semiconductor package follow a “drain 1, drain 2, drain 1, and drain 2” pattern. A method for fabricating a semiconductor package. The method comprises the steps of providing a land grid array substrate; mounting a first VDMOSFET and a second VDMOSFET on the land grid array substrate; applying a wire bonding process; forming a molding encapsulation; and applying a singulation process.

Abstract: Packages including substrate-less integrated components and methods of fabrication are described are described. In an embodiment, a packaging method includes attaching a ground structure to a carrier and a plurality of components face down to the carrier and laterally adjacent to the ground structure. The plurality of components are encapsulated within a molding compound, and the carrier is removed exposing a plurality of component terminals and a plurality of ground structure terminals. A plurality of packages are singulated.

Abstract: This invention provides a semiconductor package, the semiconductor package includes: a semiconductor chip having a connection pad; an encapsulant covering at least a portion of the semiconductor chip; and a connection structure disposed on the semiconductor chip and the encapsulant. The connection structure comprises a first insulation layer, a first redistribution layer disposed on the first insulation layer, and a second insulation layer disposed on the first insulation layer and covering the first redistribution layer. The first redistribution layer has one or more openings. The openings have a shape having a plurality of protrusions, respectively, and B/A is 1.5 or less, where A refers to a thickness of the first redistribution layer, and B refers to a thickness of a region of the second insulation layer covering the first redistribution layer.

Abstract: A surface mounted type leadframe includes a conductive base and an insulating material layer. The conductive base includes at least three connecting pads spaced apart from each other. First surface of the connecting pads are configured to form die bonding regions, and second surfaces of the connecting pads opposite to the first surfaces are configured to form soldering regions. The insulating material layer at least partially covers the first surfaces, surrounds the die bonding regions, and is filled in a gap between each two adjacent connecting pads. A photoelectric device with multi-chips adopting the surface mounted type leadframe is also provided.

Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a first die on a board, attaching an interposer on a top surface of the first die, and attaching a second die on the top surface of the first die that is adjacent the interposer, wherein the second die is offset from a center region of the first die. A first wire conductive structure may be attached to the second die that extends from the second die to a top surface of the interposer. A second wire conductive structure is attached to the interposer and extends from the interposer to the board.

Abstract: Disclosed is a device including a lead frame having a body with a top surface and a bottom surface and lead fingers. Each lead finger has a first end and a second end. A semiconductor die is coupled to the body. A first flag is a first exposed portion of the body and integral with the first end of a first lead finger. The first flag and the first lead finger are a continuous material. A second flag is a second exposed portion of the body and integral with the first end of a second lead finger. The second flag and the second lead finger are a continuous material. An encapsulant covers the die, the bottom surface of the body, the first end of the lead fingers and a portion of the top surface of the body. The flags are separated and electrically isolated from one another by the encapsulant.

Abstract: A device includes a die comprising a sensor. The device also includes a substrate that is coupled to the die via the electrical coupling. The device further includes a packaging container. The packaging container and the substrate form a housing for the die. The packaging container comprises an opening that exposes at least a portion of the die to an environment external to the housing. The exposed surfaces of the die, interior of the housing, the electrical coupling, and the substrate to the environment external to the housing through the opening are coated with a conformal film. The conformal film prevents liquid, e.g., water, gas, etc., contact to the exposed surfaces of the die, the electrical coupling and the substrate.

Abstract: A semiconductor module includes a base plate made of a metal, an insulating frame provided on a peripheral edge portion of the base plate, a lead made of a metal and provided on the frame, and a semiconductor device mounted on the base plate in a space surrounded by the frame, wherein the frame is fixed to the base plate by a bonding material containing silver, the frame has concave portions formed in an inner portion which is a corner portion on a space side and an outer portion which is a corner portion on a side opposite to the inner portion in a surface thereof which faces the base plate, and the concave portions are filled with a coating material.

Abstract: A chip mounting portion included in a semiconductor device has a region including a semiconductor chip in plan view. When an average surface roughness of the region is “Ra”, 0.8 ?m?Ra?3.0 ?m holds.

Abstract: A semiconductor package includes a leadframe having a first island and second island each having an upper surface corresponding with an upper surface of the leadframe. One or more tie bars couple the first island with the second island. At least one tie bar has a protrusion extending from the upper surface of the leadframe and configured to substantially prevent a flow of a solder between the first and second islands. A first die couples with the leadframe at the first island and a second die couples with the leadframe at the second island. At least one of the tie bars has a recess at a lower surface of the leadframe. The leadframe includes a slit between the first and second island.

Abstract: A multi-die module includes a first die with a first device and a second die with a second device. The multi-die module also includes a contactless coupler configured to convey signals between the first device and the second device. The multi-die module also includes a coupling loss reduction structure.

Abstract: In various embodiments, the present disclosure provides capacitors and methods of forming capacitors. In one embodiment, a capacitor includes a substrate, a first electrode on the substrate, a second electrode, and a first dielectric layer. A portion of the first electrode is exposed in a contact region. The first dielectric layer includes a first dielectric region between the first electrode and the second electrode, and a second dielectric region between the first dielectric region and the contact region. The second dielectric region is contiguous to the first dielectric region, and a surface of the second dielectric region defines a surface path between the first electrode and the contact region. The second dielectric region has a plurality of grooves that increase a spatial extension of said surface path.

Abstract: The present disclosure is directed to a leadframe package having solder wettable sidewalls that is formed using a pre-molded leadframe and methods of manufacturing the same. A metal plated leadframe with a plurality of recesses and a plurality of apertures is placed into a top and bottom mold tool. A molding compound is then formed in the plurality of recesses and apertures in the leadframe to form a pre-molded leadframe. A plurality of die and wires are coupled to the pre-molded leadframe and the resulting combination is covered in an encapsulant. Alternatively, a bare leadframe can be processed and the metal layer can be applied after encapsulation. A saw or other cutting means is used for singulation to form leadframe packages. Each resulting leadframe package has a solder wettable sidewall for improving the strength of solder joints between the package and a circuit board.

Abstract: A packaged electronic device includes a substrate comprising a die pad and a lead spaced apart from the die. An electronic device is attached to the die pad top side. A conductive clip is connected to the substrate and the electronic device, and the conductive clip comprises a plate portion attached to the device top side with a conductive material, a clip connecting portion connected to the plate portion and the lead, and channels disposed to extend inward from a lower side of the plate portion above the device top side. The conductive material is disposed within the channels. In another example, the plate portion comprises a lower side having a first sloped profile in a first cross-sectional view such that an outer section of the first sloped profile towards a first edge portion of the plate portion is spaced away from the electronic device further than an inner section of the first sloped profile towards a central portion of the plate portion. Other examples and related methods are also disclosed herein.

Abstract: An approach to forming an electronic device assembly that includes a plurality of interconnect pads on an electronic device, an interconnect die with a first set of interconnect pads adjacent to a first edge of the interconnect die connecting to a second set of interconnect pads adjacent to a second edge of the interconnect die, where a first set of connections between the plurality of interconnects on the electronic device and the first set of interconnect pads on the interconnect die occurs. Furthermore, the electronic assembly includes a second set of connections between the second set of interconnects on the interconnect die and a set of interconnect pads on a flex cable.

Abstract: A semiconductor package formed utilizing multiple etching steps includes a lead frame, a die, and a molding compound. The lead frame includes leads and a die pad. The leads and the die pad are formed from a first conductive material by the multiple etching steps. More specifically, the leads and the die pad of the lead frame are formed by at least three etching steps. The at least three etching steps including a first etching step, a second undercut etching step, and a third backside etching step. The second undercut etching step forming interlocking portions at an end of each lead. The end of the lead is encased in the molding compound. This encasement of the end of the lead with the interlocking portion allows the interlocking portion to mechanically interlock with the molding compound to avoid lead pull out. In addition, by utilizing at least three etching steps the leads can be formed to have a height that is greater than the die pad of the lead frame.

Abstract: A semiconductor device includes a substrate constituted of an insulator, a first conductor film provided on a surface of the substrate; a semiconductor chip including a first electrode and a second electrode, the first electrode being connected to the first conductor film; and an external connection terminal including an inner end portion and an outer end portion. The inner end portion is located between the substrate and the semiconductor chip and is connected to the second electrode. The external connection terminal further includes an intermediate portion located between the inner end portion and the outer end portion and joined to the surface of the substrate. A distance between the intermediate portion of the external connection terminal and the substrate is greater than a distance between the inner end portion of the external connection terminal and the substrate.

Abstract: A device comprises a base, a die, leads, and an electrically-insulating die housing covering the die. The base comprises a die mounting section in which the die is mounted. The leads extend away from the die mounting section and are electrically connected to the die. The base further comprises a base mounting section and a recessed section. The recessed section comprises a recess between the die mounting section and the base mounting section. The base further comprises a first side, a second side opposing the first side, and a thickness measured between the first and second sides. The thickness of the base throughout the recessed section is less than the thickness of the base throughout the base mounting section. The base further comprises an opening extending at least through the base mounting section from the first side to the second side.

Abstract: A substrate includes a first metal layer, a second metal layer, a third metal layer and an insulation layer surrounding the first metal layer, the second metal layer and the third metal layer. The first power component is electrically connected to the first metal layer. The second power component is electrically connected to the second metal layer. The shortest distance between the first metal layer exposed to a second surface of the insulation layer and the second metal layer exposed to the second surface is a first distance, the shortest distance between a first metal layer of the insulation layer exposed to the first surface and the second metal layer exposed to the first surface is a second distance, and a ratio value of the first distance to the second distance ranges between 1.25 and 1.4.

Abstract: A semiconductor device has a coil and wirings under the coil. In addition, a distance between the upper face of the wirings and the bottom face of the coil is 7 ?m or larger, and the wirings have a plurality of linear wiring parts each wiring width of which is 1 ?m or smaller. In addition, the linear wiring parts do not configure a loop wiring, and the coil and the linear wiring parts are overlapped with each other in planar view.

Abstract: A sensor, which is based on a coupling between a printed circuit board inductance and a number of attachment inductances that are applied using SMD technology.

Abstract: Semiconductor device packages and method are provided. A semiconductor device package according to the present disclosure includes a substrate including a first region, a passive device disposed over the first region of the substrate, a contact pad disposed over the passive device, a passivation layer disposed over the contact pad, a recess through the passivation layer, and an under-bump metallization (UBM) layer. The recess exposes the contact pad and the UBM layer includes an upper portion disposed over the passivation layer and a lower portion disposed over a sidewall of the recess. A projection of the upper portion of the UBM layer along a direction perpendicular to the substrate falls within an area of the contact pad.

Abstract: An apparatus is described that includes a semiconductor die package. The semiconductor die package includes a semiconductor die package substrate having a top side and a bottom side. The semiconductor die package includes I/O balls on the bottom side of the semiconductor die package substrate. The I/O balls are to mount to a planar board. The semiconductor die package includes a first semiconductor die mounted on the bottom side of the semiconductor die package substrate. The first semiconductor die is vertically located between the bottom side of the semiconductor die package substrate and a second semiconductor die that is a part of the semiconductor die package.

Abstract: A method of manufacturing a semiconductor package substrate includes forming a trench in one surface of a base substrate formed of a conductive material, performing a first filling operation of filling the trench with resin, performing a first curing operation of semi-curing the resin filled in the first filling operation, performing a second filling operation of additionally filling resin on a semi-cured resin, performing a second curing operation of fully curing the resin, removing the resin exposed from the trench, and etching an opposite surface of the base substrate to expose at least part of the resin filling the trench.

Abstract: Packaging methods for semiconductor devices are disclosed. A method of packaging a semiconductor device includes providing a workpiece including a plurality of packaging substrates. A portion of the workpiece is removed between the plurality of packaging substrates. A die is attached to each of the plurality of packaging substrates.

Abstract: A method includes providing a carrier, depositing a die attach material on the carrier, and arranging a semiconductor die on the die attach material, wherein a main surface of the semiconductor die facing the die attach material at least partly contacts the die attach material, wherein immediately after arranging the semiconductor die on the die attach material, a first maximum extension of the die attach material over edges of the main surface is less than about 100 micrometers.

Abstract: A leadless multichip semiconductor device includes a metal substrate having a through-hole aperture with an outer ring for holding a bottom semiconductor die with an inner row and an outer row of metal pads. The bottom semiconductor die has a back side metal (BSM) layer on its bottom side and a top side with bond pads mounted top side up on the ring. A metal die attach layer is directly between the BSM layer and walls of the metal substrate providing a die attachment that fills a bottom portion of the aperture. Bond wires are between the inner metal pads and the bond pads. A top semiconductor die has top bond pads mounted top side up on a dielectric adhesive on the bottom semiconductor die. Pins connect the top bond pads to the outer metal pads. A mold compound provides isolation between adjacent ones of the metal pads.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor chip, and a die pad. The die pad has a first surface. The semiconductor chip is bonded on the first surface using a paste including a metal particle. A concave structure is provided in the first surface. The concave structure is positioned directly under each of a plurality of sides of the semiconductor chip and extends along each of the plurality of sides.

Abstract: A semiconductor device includes a semiconductor substrate SB and a wiring structure formed on a main surface of the semiconductor substrate SB. The uppermost first wiring layer among a plurality of wiring layers included in the wiring structure includes a pad PD, and the pad PD has a first region for bonding a copper wire and a second region for bringing a probe into contact with the pad. A second wiring layer that is lower by one layer than the first wiring layer among the plurality of wiring layers included in the wiring structure includes a wiring line M6 arranged immediately below the pad PD, the wiring line M6 is arranged immediately below a region other than the first region of the pad PD, and no conductor pattern in the same layer as a layer of the wiring line M6 belong is formed immediately below the first region of the pad PD.

Abstract: An optoelectronic component includes a light emitting semiconductor chip, including an emission side and comprising an underside, wherein the optoelectronic component is configured to emit light via the emission side, the optoelectronic component including an insulating layer, the light emitting semiconductor chip is embedded into the insulating layer, the light emitting semiconductor chip including two electrical contact locations, the contact locations face away from the emission side, a first and a second electrically conductive contact layer are provided, respectively, an electrically conductive contact layer electrically conductively connects to a contact location of the semiconductor chip, the electrically conductive contact layers are arranged in the insulating layer, the first electrically conductive contact layer adjoins a first side face of the optoelectronic component, and the second electrically conductive contact layer adjoins a second side face of the optoelectronic component.

Abstract: A method of forming solder bumps includes preparing a substrate having a surface on which a plurality of electrode pads are formed, forming a resist layer on the substrate, the resist layer having a plurality of openings, each of the openings being aligned with a corresponding electrode pad of the plurality of electrode pads, forming a conductive pillar in each of the openings of the resist layer, forming conductive layers to cover at least side walls of the resist layer in the openings to block gas emanating from the resist layer, filling molten solder in each of the openings in which the conductive layers has been formed and removing the resist layer.

Abstract: According to one embodiment, a semiconductor package includes a die pad, a semiconductor chip, a lead frame, and an insulating part. The semiconductor chip is provided on the die pad. The lead frame is separated from the die pad. The lead frame is electrically connected to a terminal of the semiconductor chip. The lead frame includes a first part and a second part disposed between the first part and the die pad. An upper surface of the first part is located below an upper surface of the second part. The insulating part is provided on the die pad, the semiconductor chip, and the second part. The insulating part seals the semiconductor chip.

Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; a first clip frame disposed on the upper surface of the semiconductor chip; a first clip conductive connection member disposed between the first electrode on the semiconductor chip and a lower surface of the first clip frame, the first clip conductive connection member electrically connecting the first electrode of the semiconductor chip and the lower surface of the first clip frame; and a sealing resin for sealing the semic

Abstract: A performance of a semiconductor device is improved. The semiconductor device according to one embodiment includes a wire bonded to one bonding surface at a plurality of parts in an opening formed in an insulating film of a semiconductor chip. The semiconductor device includes also a sealer that seals the semiconductor chip and the wire so that the sealer is in contact with the bonding surface. The bonding surface includes a first region to which a bonding portion of the wire is bonded, a second region to which another bonding portion of the wire is bonded, and a third region between the first region and the second region. A width of the third region is smaller than a width of the first region and a width of the second region.

Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; and a sealing resin for sealing the semiconductor chip, the die pad frame, and the conductive connection member for die pad.

Abstract: A semiconductor device having a plurality of wiring layers including a first wiring layer and a second wiring layer, with the first wiring layer being the uppermost layer and including a pad PD that has a first region for bonding a copper wire, and a second region for bringing a probe into contact with the pad. The second wiring layer is one layer below the first wiring layer and includes a first wiring line arranged immediately below the second region of the pad, the second wiring layer having no conductor pattern at a region overlapping with the first region of the pad PD.

Abstract: A lead frame includes a first outer lead portion and a second outer lead portion which is arranged to oppose to the first outer lead portion with an element-mounting region between them. An inner lead portion has first inner leads connected to the first outer leads and second inner leads connected to the second outer leads. At least either the first or second inner leads are routed in the element-mounting region. An insulation resin is filled in the gaps between the inner leads located on the element-mounting region. A semiconductor device is configured with semiconductor elements mounted on both the top and bottom surfaces of the lead frame.

Abstract: A semiconductor device according to one embodiment of the present invention includes a wire electrically connecting a die pad and a semiconductor chip mounted on the die pad to each other, and an encapsulation body encapsulating the semiconductor chip. The die pad includes a wire-bonding region to which the wire is connected and a through hole penetrating through the die pad in a thickness direction. The wire-bonding region is covered by a metal film partially covering the die pad. The through hole is formed at a position overlapping the metal film. The encapsulation body includes a first portion formed over the die pad, a second portion formed under the die pad, and a third portion buried in the through hole of the die pad, wherein the first portion and the second portion of the encapsulation body are connected with each other via the third portion.

Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.

Abstract: A semiconductor package includes a core layer having a first surface and a second surface opposite to the first surface. The core layer includes a cavity. A first die is in the cavity. A first gap is between a sidewall of the cavity and a sidewall of the first die. A filling material is in the first gap. The filling material includes a first dimple in proximal to the second surface of the core layer. A first buffer layer on the second surface of the core layer. The first buffer layer has a bottom surface in proximal to the first die and a top surface opposite to the bottom surface. The first buffer layer filling the first dimple. A method for manufacturing a semiconductor package is also disclosed.

Abstract: A package structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The pads are disposed on the first substrate, and fill the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills the gaps between the conductive pillars. A bonding method of the package structure is also provided.

Abstract: A leadframe includes a common contact. A first transistor is disposed over the leadframe with a first interconnect structure of the first transistor disposed over the common contact. A second transistor is disposed over the leadframe with a second interconnect structure of the second transistor disposed over the common contact.

Abstract: The film-forming method according to an embodiment of the present invention includes: a step A for forming a photocurable resin liquid film on a substrate; a step B for vaporizing the photocurable resin in a first region on the substrate by selectively irradiating the first region with infrared rays or visible light having a wavelength that is longer than 550 nm; and a step C for obtaining a photocured resin film by curing the photocurable resin in the second region on the substrate, said second region including the first region, by irradiating, simultaneously with the step 3 or after performing the step 3, the second region with light, to which the photocurable resin is sensitive.

Abstract: According to the disclosure, a relationship of Tgp>Tgf, ?f1<?PCB1, and (Tgp?To)×?PCB1<(Tgf?To)×?f1+(Tgp?Tgf)×?f2 or a relationship of Tgp<Tgf, ?PCB1<?f1, and (Tgf?To)×?f1<(Tgp?To)×?PCB1+(Tgf?Tgp)×?PCB2 is satisfied, where linear expansion coefficients in an in-plane direction of the substrate at a temperature below a glass transition temperature Tgp of the substrate and at a temperature above the glass transition temperature Tgp of the substrate are denoted as ?PCB1 and ?PCB2, respectively, linear expansion coefficient of the frame at a temperature below a glass transition temperature Tgf of the frame and at a temperature above the glass transition temperature Tgf of the frame are denoted as ?f1 and ?f2, respectively, and a room temperature is denoted as To.

Abstract: A semiconductor device includes an integrated circuit that is disposed at a first face side of a semiconductor substrate, the semiconductor substrate having a first face and a second face, the second face opposing the first face, the semiconductor substrate having a through hole from the first face to the second face; an external connection terminal that is disposed at the first face side; a conductive portion that is disposed in the through hole, the conductive portion being electrically connected to the external connection terminal; and an electronic element that is disposed at a second face side.