With Structure For Mounting Semiconductor Chip To Lead Frame (e.g., Configuration Of Die Bonding Flag, Absence Of A Die Bonding Flag, Recess For Led) Patents (Class 257/676)
  • Patent number: 9349675
    Abstract: A method of manufacturing a semiconductor device includes preparing a lead frame provided with a die pad having an upper surface and a plurality of leads being arranged so as to be aligned on a side of the die pad and each including a wire joint part at a distal end on the side of the die pad, after the preparing the lead frame, mounting a semiconductor chip having a main surface and a plurality of electrode pads formed on the main surface, on the upper surface of the die pad, and after the mounting the semiconductor chip, electrically connecting a first electrode pad among the plurality of electrode pads of the semiconductor chip and a first lead among the plurality of leads to each other via a first wire.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: May 24, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshiharu Kaneda
  • Patent number: 9338900
    Abstract: A method of fabricating an interposer substrate is provided, including: providing a carrier having a first wiring layer and a plurality of conductive pillars disposed on the first wiring layer; forming a first insulating layer on the carrier, with the conductive pillars being exposed from the first insulating layer; forming a second wiring layer on the first insulating layer and the conductive pillars; disposing a plurality of external connection pillars on the second wiring layer; forming a second insulating layer on the first insulating layer, with the external connection pillars being exposed from the second insulating layer; forming at least a trench on the second insulating layer; and removing the carrier. Through the formation of the interposer substrate, which does not have a core layer, on the carrier, a via process is omitted. Therefore, the method is simple, and the interposer substrate thus fabricated has a low cost. The present invention further provides the interposer substrate.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: May 10, 2016
    Assignee: Phoenix Pioneer Technology Co., Ltd.
    Inventors: Pao-Hung Chou, Shih-Ping Hsu, Che-Wei Hsu
  • Patent number: 9337240
    Abstract: A lead frame for an integrated circuit (IC) package is disclosed. The lead frame includes a center region and a plurality of lead fingers surrounding the center region. The plurality of lead fingers that surrounds the center region defines a periphery region around the center region. A portion of the plurality of lead fingers extends from the center region to hold the center region in place. Tie bars that are typically used to hold the center region in place may not be included in the lead frame.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: May 10, 2016
    Assignee: Altera Corporation
    Inventors: Guan Khai Lee, Loon Kwang Tan, Ping Chet Tan, Pheak Ti Teh
  • Patent number: 9331003
    Abstract: An integrated circuit packaging system, and method of manufacture thereof, includes: lead islands; a pre-molded material surrounding a bottom of the lead islands; a device over a portion of the lead islands and having electrical connections to another portion of the lead islands, the electrical connections over areas of the another portion of the lead islands over areas covered by the pre-molded material; and an encapsulation over the device and the lead islands.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 3, 2016
    Assignee: STATS ChipPac Ltd.
    Inventors: Zigmund Ramirez Camacho, Bartholomew Liao Chung Foh, Sheila Marie L. Alvarez, Dao Nguyen Phu Cuong, HeeJo Chi
  • Patent number: 9330997
    Abstract: A heat spreader structure includes a planar portion and a slanted portion. The slanted portion extends at an angle from an edge of the planar portion. The first slanted portion includes a first slot. A second heat spreader structure includes a planar member, a first edge member and a second edge member. The first edge member extends only perpendicularly from a first edge of the planar member whereas the second edge member extends from the second edge of the planar member and has a slanted surface with respect to that of the planar member. In addition to that, the first and second heat spreader structure may be formed using different manufacturing methods.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: May 3, 2016
    Assignee: Altera Corporation
    Inventors: Ken Beng Lim, Myung June Lee, Yuan Li, Ping Chet Tan
  • Patent number: 9331029
    Abstract: Methods for fabricating microelectronic packages, such as Fan-Out Wafer Level Packages, and microelectronic packages are provided. In one embodiment, the method includes placing a first semiconductor die on a temporary substrate, forming an electrically-conducive trace in contact with at least one of the first semiconductor die and the temporary substrate, and encapsulating the first semiconductor die and the electrically-conductive trace within a molded panel. The temporary substrate is removed to reveal a frontside of the molded panel through which the electrically-conducive trace is at least partially exposed. At least one redistribution layer is formed over the frontside of the molded panel, the at least one redistribution layer comprises an interconnect line in ohmic contact with the electrically-conducive trace.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: May 3, 2016
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventors: Michael B. Vincent, Zhiwei Gong, Jason R. Wright
  • Patent number: 9331005
    Abstract: In one implementation, a power semiconductor package includes a non-contiguous, multi-section conductive carrier. A control transistor with a control transistor terminal is coupled to a first section of the multi-section conductive carrier, while a sync transistor with a sync transistor terminal is coupled to a second section of the multi-section conductive carrier. The first and second sections of the multi-section conductive carrier sink heat generated by the control and sync transistors. The first and second sections of the multi-section conductive carrier are electrically connected only through a mounting surface attached to the power semiconductor package. Another implementation of the power semiconductor package includes a driver IC coupled to a third section of the multi-section conductive carrier. A method for fabricating the power semiconductor package is also disclosed.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: May 3, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventor: Eung San Cho
  • Patent number: 9331251
    Abstract: To provide a light emitting device that can suppress the increase in pits and projections caused by the thermal history of the reflective film on the surface of the reflective film used in the light emitting device, the light emitting device includes: a light emitting element; and a reflective film for reflecting light from the light emitting element, in which the reflective film contains silver as a principal component, and nanoparticles of an oxide.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: May 3, 2016
    Assignee: NICHIA CORPORATION
    Inventors: Masafumi Kuramoto, Shuji Shioji, Katsuyuki Tsunano
  • Patent number: 9324633
    Abstract: A package assembly and a method for manufacturing the same are disclosed. The package assembly includes semiconductor chips, encapsulant layers, and a chip carrier. The plurality of semiconductor chips are stacked in a plurality of levels, including a lowermost level and at least one upper level. The plurality of encapsulant layers cover respective levels of semiconductor chips. The chip carrier is used for mounting lowermost-level semiconductor chips. At least one upper-level semiconductor chips are electrically coupled to the chip carrier by conductive traces. The conductive traces include extension conductors on a surface of a lower-level encapsulant layer and conductive vias which penetrate the lower-level encapsulant layer and are exposed at a bottom surface of the package assembly. The package assembly has improved high-frequency performance while having a small size and supporting multifunctionality.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: April 26, 2016
    Assignee: SILERGY SEMICONDUCTOR TECHNOLOGY (HANGZHOU) LTD.
    Inventor: Xiaochun Tan
  • Patent number: 9326338
    Abstract: Multi-junction solid-state transducer (SST) devices and associated systems and methods are disclosed herein. In several embodiments, for example, an SST system can include a first multi-junction SST chain having a first drive voltage, a first P-contact, and a first N-contact, and a second multi-junction SST chain having a second drive voltage, a second P-contact, and a second N-contact. The first and second multi-junction SST chains can be configured to be activated independently of each other. The SST system can further include a driver operably coupled to the first and second P- and N-contacts. The driver can be configured to activate the first multi-junction SST chain when voltage input is at least equal to the first drive voltage. When absolute voltage increases a predetermined voltage level, the driver can be configured to activate the second multi-junction SST chain or the first and second multi-junction SST chains.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: April 26, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Martin F. Schubert, Vladimir Odnoblyudov
  • Patent number: 9324644
    Abstract: A trench portion (trench or groove) is formed at each of four corner portions of a chip bonding region having a quadrangular planar shape smaller than an outer-shape size of a die pad included in a semiconductor device. Each trench is formed along a direction of intersecting with a diagonal line which connects between the corner portions where the trench portions are arranged, and both ends of each trench portion are extended to an outside of the chip bonding region. The semiconductor chip is mounted on the chip bonding region so as to interpose a die-bond material. In this manner, peel-off of the die-bond material in a reflow step upon mounting of the semiconductor device on a mounting substrate can be suppressed. Also, even if the peel-off occurs, expansion of the peel-off can be suppressed.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: April 26, 2016
    Assignee: Renesas Electronics Corporation
    Inventor: Atsushi Fujisawa
  • Patent number: 9324584
    Abstract: System and method of manufacturing an integrated circuit packaging system using transferable trace lead frame. A lead frame is provided having lower metal contacts. A masking layer can be formed on an upper surface of the lead frame for protection and shielding purposes. Routing layer and conductive lands may subsequently be formed by shaping the lead frame, along with bottom encapsulation. The masking layer may subsequently be removed for additional processing steps including connecting an integrated circuit die to the upper surface of the lead frame.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: April 26, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 9312218
    Abstract: A semiconductor device has a semiconductor die mounted to a substrate. A leadframe has a base plate and integrated tie bars and conductive bodies. The tie bars include a down step with an angled surface and horizontal surface between the conductive bodies. The leadframe is mounted to the semiconductor die and substrate with the base plate disposed on a back surface of the semiconductor die and the conductive bodies disposed around the semiconductor die and electrically connected to the substrate. An encapsulant is deposited over the substrate and semiconductor die and into the down step of the tie bars. A conductive layer is formed over the conductive bodies to inhibit oxidation. The leadframe is singulated through the encapsulant in the down step and through the horizontal portion of the tie bars to electrically isolate the conductive bodies. A semiconductor package can be mounted to the substrate and semiconductor die.
    Type: Grant
    Filed: May 12, 2011
    Date of Patent: April 12, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: DaeSik Choi, SooSan Park, HanGil Shin
  • Patent number: 9307665
    Abstract: The invention provides an air cavity package for a component. The package has a connection lead structure in which the or each connection lead has a connection zone within the package for receiving a wire connector. A region of no connection lead material is provided directly between the connection zone and the neighboring outer edge of the cavity. This provides a trap for flowing interconnect material.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: April 5, 2016
    Assignee: SAMBA HOLDCO NETHERLANDS B.V.
    Inventors: Michael Asis, Albertus Reijs, Tennyson Nguty, An Xiao
  • Patent number: 9305873
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming an isolated contact having a contact protrusion, the contact protrusion having a lower protrusion surface, an upper protrusion surface, and a protrusion sidewall; forming a die paddle, adjacent to the isolated contact, having a die paddle protrusion, the die paddle protrusion having a lower die protrusion surface, an upper die protrusion surface, and a die protrusion sidewall; depositing a contact pad on the contact protrusion; depositing a die paddle pad on the die paddle protrusion; coupling an integrated circuit die to the contact protrusion; and molding an encapsulation on the integrated circuit die.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: April 5, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Patent number: 9305869
    Abstract: A packaged semiconductor device (100) comprising a leadframe having a pad (101) with an assembled semiconductor chip (110), a plurality of straps (102) connecting the pad to side edges of the device package, leads (103), and a package (150) of plastic compound adhering to the leadframe; at least one surface (102a) of the straps covered with a layer (120) of a compound both non-adhesive to polymeric compounds and hydrophobic; the compound (220) selected from a group including fluorinated thiol compounds, fluorinated amine compounds, fluorinated aminesilanes, organosilanes, and their derivatives; or the compound (330) selected from a group including open-pore microcellular metal foams and polymer foams. Further, the package may include an array of holes through the plastic compound, extending from the package surface to the strap surface.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: April 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rongwei Zhang, Abram Castro
  • Patent number: 9299628
    Abstract: A power semiconductor module is provided which is capable of keeping low the degrees of increases in temperatures of wide bandgap semiconductor elements, reducing the degree of increase in chip's total surface area of the wide bandgap semiconductor elements, and being fabricated at low costs, when Si semiconductor elements and the wide bandgap semiconductor elements are placed within one and the same power semiconductor module. The Si semiconductor elements are placed in a central region of the power semiconductor module, and the wide bandgap semiconductor elements are placed on opposite sides relative to the central region or in edge regions surrounding the central region.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: March 29, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takayoshi Miki, Yasushi Nakayama, Takeshi Oi, Kazuhiro Tada, Shiori Idaka, Shigeru Hasegawa, Tomohiro Kobayashi, Yukio Nakashima
  • Patent number: 9293396
    Abstract: A method for manufacturing a semiconductor device, includes: (a) preparing a lead frame that includes a die pad having a first plane and a second plane located on the opposite side of the first plane, and a plurality of leads arranged next to the die pad; (b) mounting a semiconductor chip having a surface, a plurality of electrodes formed over the surface, and a reverse side located on the opposite side of the surface over a chip mounting area of the first plane of the die pad; (c) electrically coupling parts of the electrodes of the semiconductor chip and the leads through a plurality of first wires and electrically coupling the other parts of the electrodes and the die pad through a second wire.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: March 22, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Akito Shimizu, Kenji Nishikawa, Sadayuki Moroi, Tomoo Imura
  • Patent number: 9293399
    Abstract: A semiconductor device includes first and semiconductor elements, an electroconductive support member including electroconductive elements, and a resin package. The first semiconductor element includes a first active surface and first electrodes formed on the first active surface. The second semiconductor element includes a second active surface and second electrodes formed on the second active surface. The electroconductive support member is electrically connected to the first and second semiconductor elements and support these elements. The resin package covers the first and second semiconductor elements. The second semiconductor element is located between the first semiconductor element and the electroconductive support member. The first electrodes of the first semiconductor element and the electroconductive elements are connected by wire.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: March 22, 2016
    Assignee: ROHM CO., LTD.
    Inventors: Kenji Fujii, Mamoru Yamagami
  • Patent number: 9293397
    Abstract: A power semiconductor package and a method of preparation are disclosed. The power semiconductor package includes a pair of first and second die paddles arranged side by side, a first semiconductor chip attached to the first die paddle, a second semiconductor chip attached to the second die paddle, a metal clip electrically connecting a first electrode at the top surface of the first semiconductor chip and a first electrode at the top surface of the second semiconductor chip to a second pin, a first conductive structure connecting a second electrode at the top surface of a first semiconductor chip to a first pin, and a second conductive structure connecting a second electrode at the top surface of the second semiconductor chip to a third pin. In examples of the present disclosure, double-chip common source technique for the source electrodes of two power MOSFETs is achieved by applying a T-shape metal clip.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: March 22, 2016
    Assignee: ALPHA AND OMEGA SEMICONDUCTORS INCORPORATED
    Inventors: Hamza Yilmaz, Yan Xun Xue, Jun Lu
  • Patent number: 9281264
    Abstract: An electronics package is disclosed. The electronics package is disclosed as including a substrate core, a metal layer established on top of the substrate core, the metal layer being etched so as to include a die attachment anchor and at least one gap that separates a die bonding pad from at least one of a trace and wire bonding pad, for example. The die attachment anchor is established on top of the die bonding pad and has a depth that does not extend all the way through the die bonding pad.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 8, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Meng Ee Lee, Eng Chuan Ong, Seong Choon Lim
  • Patent number: 9275941
    Abstract: The present invention discloses a quad flat no lead package and a production method thereof. The quad flat no lead package comprises a lead frame carrier consisting of a carrier pit and three circles of leads arranged around the carrier pit, wherein the three circles of leads respectively consist of a plurality of leads that are disconnected mutually; an IC chip is adhered in the carrier pit; and an inner lead chemical nickel and porpezite plated layer is plated on all the leads; the inner lead chemical nickel and porpezite plated layer is arranged in the same direction as the IC chip; the IC chip is connected with the inner lead chemical nickel and porpezite plated layer through a bonding wire; and the IC chip, the ends of all the leads plated with the inner lead chemical plating nickel and palladium metal layers and the bonding wire are all packaged in a plastic package.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: March 1, 2016
    Assignees: TIANSHUI HUATIAN TECHNOLOGY CO., HUATIAN TECHNOLOGY (XI'AN) CO., LTD.
    Inventors: Wenhui Zhu, Wei Mu, Zhaoming Xu, Xiaowei Guo
  • Patent number: 9269648
    Abstract: A method and apparatus are provided for manufacturing a lead frame based thermally enhanced package (9) with exposed heat spreader lid array (96) designed to be optimized for compression mold encapsulation of an integrated circuit die (94) by including a perimeter reservoir regions (97r) in each heat spreader lid (96) for movement of mold compound (98) displaced during the mold compression process.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: February 23, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Leo M. Higgins, III
  • Patent number: 9252054
    Abstract: A thinned integrated circuit device and manufacturing process for the same are disclosed. The manufacturing process includes forming a through-silicon via (TSV) on a substrate, a first terminal of the TSV is exposed on a first surface of the substrate, disposing a bump on the first surface of the substrate to make the bump electrically connected with the TSV, disposing an integrated circuit chip (IC) on the bump so that a first side of the IC is connected to the bump, disposing a thermal interface material (TIM) layer on a second side of the IC opposite to the first side of the IC, attaching a heat-spreader cap on the IC by the TIM layer, and backgrinding a second surface of the substrate to expose the TSV to the second surface of the substrate while carrying the heat-spreader cap.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: February 2, 2016
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Sheng-Tsai Wu, Heng-Chieh Chien, John H. Lau, Yu-Lin Chao, Wei-Chung Lo
  • Patent number: 9252101
    Abstract: Packages for a three-dimensional die stack, methods for fabricating a package for a three-dimensional die stack, and methods for distributing power in a package for a three-dimensional die stack. The package may include a first lid, a second lid, a die stack located between the first lid and the second lid, a first thermal interface material layer between the first lid and a first die of the die stack, and a second thermal interface material layer between the second lid and the second die of the die stack. The second thermal interface material layer is comprised of a thermal interface material having a high electrical conductivity and a high thermal conductivity.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: February 2, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark C. Lamorey, Janak G. Patel, Peter Slota, Jr., David B. Stone
  • Patent number: 9240367
    Abstract: A semiconductor package includes a metallic leadframe having a plurality of cantilever leads, a mounting area for mounting a die, and one or more non-conductive supports adjacent to a recessed surface of the cantilever leads to support the leads during die mount, wire bond, and encapsulation processes. Encapsulant encapsulates and supports at least a portion of the die, the leadframe.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: January 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Jeffrey Gail Holloway
  • Patent number: 9240383
    Abstract: A high frequency switch module includes a multilayer substrate and a switch IC. The switch IC is mounted on a top plane of the multilayer substrate. A drive power signal input port and control signal input ports are connected to direct current external input ports through direct current voltage conductors, respectively. In-layer conductors of the direct current voltage conductors are arranged so that the in-layer conductors overlap each other at least partially in a state in which the multilayer substrate is viewed along a stacking direction.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: January 19, 2016
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hisanori Murase, Takanori Uejima, Muneyoshi Yamamoto
  • Patent number: 9230949
    Abstract: A stacked multi-chip packaging structure comprises a lead frame, a first semiconductor chip mounted on the lead frame, a second semiconductor chip flipped-chip mounted on the lead frame, a metal clip mounted on top of the first and second semiconductor chips and a third semiconductor chip stacked on the metal clip; bonding wires electrically connecting electrodes on the third semiconductor chip to the first and second semiconductor chips and the pins of the lead frame; plastic molding encapsulating the lead frame, the chips and the metal clip.
    Type: Grant
    Filed: March 7, 2015
    Date of Patent: January 5, 2016
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventors: Xiaotian Zhang, Hua Pan, Ming-Chen Lu, Jun Lu, Hamza Yilmaz
  • Patent number: 9224705
    Abstract: A semiconductor device includes a substrate having a plurality of electrodes and a plurality of leads that are connected to the electrodes and a semiconductor element that is mounted on the substrate. The semiconductor element has a rectangular shape including a long side, a short side, and a corner portion, and has bumps connected to the electrodes. An underfill is filled between the substrate and the semiconductor element and extends on the substrate around the semiconductor element. An overcoat covers the leads on the substrate. At least one of the plurality of leads that is connected to the electrode corresponding to the bump arranged nearest to the corner portion along the long side of the semiconductor element has at least two successive bent portions that are bent in the same direction and is laid out toward the short side of the semiconductor element in a plan view.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: December 29, 2015
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Shigehisa Tajimi
  • Patent number: 9214417
    Abstract: A combined packaged power semiconductor device includes flipped top source low-side MOSFET electrically connected to top surface of a die paddle, first metal interconnection plate connecting between bottom drain of a high-side MOSFET or top source of a flipped high-side MOSFET to bottom drain of the low-side MOSFET, and second metal interconnection plate stacked on top of the high-side MOSFET chip. The high-side, low-side MOSFET and the IC controller can be packaged three-dimensionally reducing the overall size of semiconductor devices and can maximize the chip's size within a package of the same size and improves the performance of the semiconductor devices. The top source of flipped low-side MOSFET is connected to the top surface of the die paddle and thus is grounded through the exposed bottom surface of die paddle, which simplifies the shape of exposed bottom surface of the die paddle and maximizes the area to facilitate heat dissipation.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: December 15, 2015
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Yueh-Se Ho, Hamza Yilmaz, Yan Xun Xue, Jun Lu
  • Patent number: 9209101
    Abstract: A semiconductor package and a method of manufacturing the semiconductor package are disclosed. A semiconductor package in accordance with an embodiment of the present invention includes a substrate, which is formed with a ground circuit and mounted with a semiconductor chip on one surface, a conductive ground layer, which is formed on the other surface of the substrate and connected with the ground circuit, a molding, which seals up the ground layer and the substrate having the semiconductor chip mounted thereon, and a conductive shield, which covers the molding and is connected with the ground layer. With a semiconductor package in accordance with an embodiment of the present invention, grounding for shielding is possible even in an entirely molded structure, and a double shielding structure to improve the shielding property.
    Type: Grant
    Filed: September 28, 2010
    Date of Patent: December 8, 2015
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Do-Jae Yoo, Young-Do Kweon, Joon-Seok Kang, Chang-Bae Lee
  • Patent number: 9209117
    Abstract: A quad flat no-lead (QFN) packaging structure. The QFN packaging structure includes a metal substrate, a first die coupled to a top surface of the metal substrate, and a plurality of I/O pads formed on the metal substrate, and extending to the proximity of the die. The no-exposed-pad QFN packaging structure also includes a first metal layer containing a plurality of inner leads corresponding to the plurality of I/O pads and extending to proximity of the die and is formed on the metal substrate by a multi-layer electrical plating process. Further, the no-exposed-pad QFN packaging structure includes metal wires connecting the die and the plurality of inner leads, and a second metal layer formed on a back surface of the plurality of I/O pads.
    Type: Grant
    Filed: May 28, 2014
    Date of Patent: December 8, 2015
    Assignee: Jiangsu Changjiang Electronics Technology Co., Ltd.
    Inventors: Xinchao Wang, Zhizhong Liang
  • Patent number: 9202777
    Abstract: A semiconductor package system includes: providing a leadframe having inner frame bars, outer frame bars, a die pad, tiebars, and rows of leads, the inner frame bars being coplanar with outer frame bars; attaching a semiconductor chip to the die pad; attaching bond wires between the semiconductor chip and the rows of leads; encapsulating the semiconductor chip, the bond wires, the inner frame bars, the outer frame bars, the die pad, the tiebars, and the rows of leads in an encapsulant; cutting a groove to remove the inner frame bars; and singulating the leadframe and the encapsulant to remove the outer frame bars.
    Type: Grant
    Filed: May 30, 2008
    Date of Patent: December 1, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Lionel Chien Hui Tay, Seng Guan Chow, Zigmund Ramirez Camacho
  • Patent number: 9202712
    Abstract: A method of manufacturing a lead frame, comprising the steps of: providing an electrically-conductive base material having first and second planar sides; forming a patterned conductive layer on the first planar side of the base material; etching the second planar side of the base material at portions with respect to exposed portions on the first planar side of the base material comprising the patterned conductive layer, to form partially-etched portions on the second planar side of the base material; providing a non-conductive filling material over the second planar side of the base material, wherein the filling material fills spaces inside the partially-etched portions on the second planar side of the base material to form adjacent portions of the filling material and a plurality of conductive portions on the second planar side of the base material; and etching the exposed portions of the first planar side of the base material comprising the patterned conductive layer to form partially-etched portions on the
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: December 1, 2015
    Assignee: ASM TECHNOLOGY SINGAPORE PTE LTD.
    Inventors: Dawei Xing, Jie Liu, Hong Wei Guan, Yue Gen Yu, Seow Kiang Khoo
  • Patent number: 9184114
    Abstract: A lead carrier provides support for an integrated circuit chip and associated leads during manufacture as packages containing such chips. The lead carrier includes a temporary support member with multiple package sites. Each package site includes a plurality of terminal pads surrounding a die attach region. The pads are formed of sintered electrically conductive material. A chip is placed at the die attach region and wire bonds extend from the chip to the terminal pads. The pads, chip and wire bonds are all encapsulated within a mold compound. The temporary support member can be peeled away and then the individual package sites can be isolated from each other to provide completed packages including multiple surface mount joints for mounting within an electronic system board. Edges of the pads are contoured to cause the pads to engage with the mold compound to securely hold the pads within the package.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: November 10, 2015
    Assignee: EOPLEX LIMITED
    Inventor: Philip E. Rogren
  • Patent number: 9171789
    Abstract: There is provided a lead frame including a plurality of plating layers formed on both an upper surface and a lower surface of a base material including a metal, wherein an upper outermost plating layer of an upper part of the lead frame is a silver plating layer including silver, and a lower outermost plating layer of a lower part of the lead frame is a gold plating layer including gold.
    Type: Grant
    Filed: August 5, 2013
    Date of Patent: October 27, 2015
    Assignee: HAESUNG DS CO., LTD
    Inventors: Dong-Il Shin, In-Seob Bae, Se-Chuel Park
  • Patent number: 9171787
    Abstract: Disclosed is a packaged device, comprising a carrier comprising a first carrier contact, a first electrical component having a first top surface and a first bottom surface, the first electrical component comprising a first component contact disposed on the first top surface, the first bottom surface being connected to the carrier, an embedded system comprising a second electrical component having a second top surface, an interconnect element, and a first connecting element, the embedded system having a system bottom surface, wherein the system bottom surface comprises a first system contact, wherein the second top surface comprises a first component contact, and wherein the first system contact is connected to the first component contact by the interconnect element and the first component contact of the second electrical component is connected to the first carrier contact by means of the first connecting element.
    Type: Grant
    Filed: June 4, 2013
    Date of Patent: October 27, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Khalil Hosseini, Joachim Mahler, Georg Meyer-Berg
  • Patent number: 9171740
    Abstract: A method for fabricating a quad flat non-leaded (QFN) package includes: forming die pads and bump solder pads by pressing a metal plate, wherein each of the die pads and the bump solder pads has at least a cross-sectional area greater than another located underneath along its thickness dimension, thereby enabling the die pads and the solder pads to be securely embedded in an encapsulant. The method further includes removing the metal plate after forming the encapsulant so as to prevent the encapsulant from overflowing onto the bottom surfaces of the bump solder pads.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: October 27, 2015
    Inventor: En-min Jow
  • Patent number: 9171766
    Abstract: A lead frame strip includes a plurality of connected unit lead frames. Each unit lead frame has a die paddle for attaching to a semiconductor die, a tie bar connecting the die paddle to a periphery of the unit lead frame, and a plurality of leads projecting from the periphery toward the die paddle. The lead frame strip further includes a support member patterned into or connected to the periphery of each unit lead frame at a proximal end and bent into a different plane than the leads so that a distal end of each support member is disposed above or below the leads and projects toward the die paddles. The distal end of the support members can be anchored in a mold compound encapsulating electronic components attached to the die paddles, to maintain structural integrity during lead frame strip testing prior to unit lead frame separation.
    Type: Grant
    Filed: May 3, 2013
    Date of Patent: October 27, 2015
    Assignee: Infineon Technologies AG
    Inventor: Carlo Baterna Marbella
  • Patent number: 9171828
    Abstract: A power supply system (200) has a QFN leadframe with leads and a pad (201). The pad surface facing a circuit board has a portion recessed with a depth (270) and an outline suitable for attaching side-by-side the sync (210) and the control (220) FET semiconductor chips. The input terminal (220a) of the control FET and the grounded output terminal (210a) of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip (230) is vertically stacked to the opposite pad surface and encapsulated in a packaging compound (290).
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: October 27, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Osvaldo Jorge Lopez, Jonathan Almeria Noquil
  • Patent number: 9165901
    Abstract: A semiconductor device includes a header, a semiconductor chip fixed to the header constituting a MOSFET, and a sealing body of insulating resin which covers the semiconductor chip, the header and the like, and further includes a drain lead contiguously formed with the header and projects from one side surface of the sealing body, and a source lead and a gate lead which project in parallel from one side surface of the sealing body, and wires which are positioned in the inside of the sealing body and connect electrodes on an upper surface of the semiconductor chip and the source lead and the gate lead, with a gate electrode pad arranged at a position from the gate lead and the source lead farther than a source electrode pad.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: October 20, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yukihiro Satou, Toshiyuki Hata
  • Patent number: 9165877
    Abstract: A system-in-package includes a package carrier; a first semiconductor die having a die face and a die edge, the first semiconductor die being assembled face-down to a chip side of the package carrier, wherein a plurality of contact pads are situated on the die face; a second semiconductor die mounted on the package carrier and adjacent to the first semiconductor die; a rewiring laminate structure between the first semiconductor die and the package carrier, the rewiring laminate structure comprising a re-routed metal layer, wherein at least a portion of the re-routed metal layer projects beyond the die edge; and a plurality of copper pillar bumps arranged on the rewiring laminate structure for electrically connecting the first semiconductor die with the package carrier.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: October 20, 2015
    Assignee: MEDIATEK INC.
    Inventors: Nan-Cheng Chen, Che-Ya Chou
  • Patent number: 9165909
    Abstract: A light source module including a substrate, a plurality of first light emitting diode (LED) chips, and at least one second LED chip is provided. The substrate has an upper surface. The plurality of first LED chips are disposed on the upper surface and electrically connected to the substrate. The second LED chip is disposed on the upper surface and electrically connected to the substrate. A first distance is between a top surface of each of the first LED chips away from the upper surface of the substrate and the upper surface, a second distance is between a top surface of the second LED chip away from the upper surface of the substrate and the upper surface, and the second distance is greater than each of the first distances.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: October 20, 2015
    Assignee: Genesis Photonics Inc.
    Inventors: Cheng-Yen Chen, Yun-Li Li, Po-Jen Su
  • Patent number: 9165872
    Abstract: A novel chip scale diode package due to no containing outer lead pins is miniaturized like a chip scale appearance to promote dimensional accuracy so that the diode package is so suitably produced by automation equipment to get automated mass production; the produced diode package may contain one or more diode chips to increase versatile functions more useful in applications, such as produced as a SMT diode package or an array-type SMT diode, and the present diode package due to made of no lead-containing material conforms to requirements for environmental protection.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: October 20, 2015
    Assignee: SFI ELECTRONICS TECHNOLOGY INC.
    Inventors: Ching-Hohn Lien, Xing-Xiang Huang, Hsing-Tsai Huang, Hong-Zong Xu
  • Patent number: 9165789
    Abstract: A fabrication method of a packaging substrate includes: providing a metal board having a first surface and a second surface opposite to the first surface, wherein the first surface has a plurality of first openings for defining a first core circuit layer therebetween, the second surface has a plurality of second openings for defining a second core circuit layer therebetween, each of the first and second openings has a wide outer portion and a narrow inner portion, and the inner portion of each of the second openings is in communication with the inner portion of a corresponding one of the first openings; forming a first encapsulant in the first openings; forming a second encapsulant in the second openings; and forming a surface circuit layer on the first encapsulant and the first core circuit layer.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: October 20, 2015
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Chi-Ching Ho, Yu-Chih Yu, Ying-Chou Tsai
  • Patent number: 9159852
    Abstract: A system and method for blocking heat from reaching an image sensor in a three dimensional stack with a semiconductor device. In an embodiment a heat sink is formed in a back end of line process either on the semiconductor device or else on the image sensor itself when the image sensor is in a backside illuminated configuration. The heat sink may be a grid in either a single layer or in two layers, a zig-zag pattern, or in an interleaved fingers configuration.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: October 13, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Chin Huang, Tzu-Jui Wang, Szu-Ying Chen, Dun-Nian Yaung, Jen-Cheng Liu, Bruce C. S. Chou, Jung-Kuo Tu, Cheng-Chieh Hsieh
  • Patent number: 9159655
    Abstract: A lead frame for mounting LED elements includes a frame body region and a large number of package regions arranged in multiple rows and columns in the frame body region. The package regions each include a die pad on which an LED element is to be mounted and a lead section adjacent to the die pad, the package regions being further constructed to be interconnected via a dicing region. The die pad in one package region and the lead section in another package region upward or downward adjacent to the package region of interest are connected to each other by an inclined reinforcement piece positioned in the dicing region.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: October 13, 2015
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Kazunori Oda, Masaki Yazaki
  • Patent number: 9147645
    Abstract: There is provided a semiconductor device having excellent moisture resistance and high temperature storage properties. The semiconductor device includes a lead frame that has a die pad and an inner lead, as a substrate, a semiconductor element that is mounted on the die pad, an electrode pad that is provided in the semiconductor element, a copper wire that connects the inner lead provided on the substrate and the electrode pad, and an encapsulant resin that encapsulates the semiconductor element and the copper wire. A region of the electrode pad disposed within a range of at least equal to or less than 3 ?m from a junction surface with the copper wire in a depth direction includes a metal, which is less likely to be ionized than aluminum, as a main component, and a content of sulfur in the copper wire is equal to or more than 15 ppm and equal to or less than 100 ppm with respect to a total amount of the copper wire.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: September 29, 2015
    Assignee: SUMITOMO BAKELITE CO., LTD.
    Inventor: Shingo Itoh
  • Patent number: 9147647
    Abstract: Each stitch part of a plurality of leads of a package has a first region having the most outer surface on which Ag plating is applied and a second region having the most outer surface on which Ni plating is applied. Further, the second region is arranged on a die pad side, and the first region is arranged on a periphery side of a sealer. Therefore, in each stitch part, types of plating applied on the most outer surfaces of the first region and the second region can be differentiated from each other, a thick Al wire can be connected to the second region of the second lead, and a thin Au wire can be connected to the first region of the first lead. As a result, usage of only Au plating can be avoided, so that the cost of the package is reduced.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: September 29, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Yoshiharu Kaneda
  • Patent number: 9142495
    Abstract: The present invention provides a lead frame having excellent solder wettability and solderability, that is well-bonded to a copper wire, and manufactured with low cost, and a semiconductor package manufactured by using the same. The lead frame includes: a base material; a first metal layer formed on at least one surface of the base material, the first metal layer comprising nickel; a second metal layer formed on a surface of the first metal layer, the second metal layer comprising palladium; and a third metal layer formed on a surface of the second metal layer, the third metal layer comprising silver.
    Type: Grant
    Filed: December 3, 2012
    Date of Patent: September 22, 2015
    Assignee: HAESUNG DS CO., LTD.
    Inventors: Sung-Kwan Paek, Dong-Il Shin, Se-Chuel Park