Abstract: A transistor array for semiconductor memory devices is provided. A plurality of semiconductor pillars extending outwardly from a bulk section of a semiconductor substrate is arranged in rows and columns. Each pillar forms an active area of a vertical channel access transistor. Insulating trenches are formed between the rows of pillars. Buried word lines extend within the insulating trenches along the rows of pillars. Bit line trenches are formed between columns of pillars. Bit lines extend perpendicular to the word lines in lower portions of the bit line trenches. A first and a second column of pillars face adjacent each bit line. Each bit line is coupled to the active areas in the pillars of the first column of pillars via a single sided bit line contact formed from polycrystalline silicon and is insulated from the active areas of the pillars of the second column of pillars.

Abstract: A semiconductor memory device includes diffusion regions formed in an active region; cell contacts connected to the diffusion regions, respectively; pillars connected to the cell contacts, respectively; a bit line connected to the pillar; capacitor contacts connected to the pillars, respectively; and storage capacitors connected to the capacitor contacts, respectively. Accordingly, the pillars exist between the cell contacts and the capacitor contacts, and thus, depths of the capacitor contacts are made correspondingly shorter. Therefore, it becomes possible to prevent occurrence of shorting defects while decreasing resistance values of the capacitor contacts.

Abstract: As for a memory element implemented in a semiconductor device typified by an RFID, it is an object of the present invention to reduce manufacturing steps and to provide a memory element and a memory circuit having the element with reduced cost. It is a feature of the present invention that a memory element sandwiched between electrodes has an organic compound, and an electrode connected to a semiconductor element controlling the memory element functions as an electrode of the memory element. In addition, an extremely thin semiconductor film formed on an insulated surface is used for the memory element; therefore cost can be reduced.

Abstract: A first set of semiconductor devices is formed on a first semiconductor substrate comprising a first semiconductor material having a first melting point. A first via-level dielectric layer containing first contact vias is formed on the first semiconductor substrate. A second semiconductor substrate comprising a second semiconductor material having a second melting point lower than the first melting point is formed either by bonding or deposition. A second set of semiconductor devices is formed on the second semiconductor substrate. A second via-level dielectric layer, second contact vias contacting the second set of semiconductor devices, and inter-substrate vias electrically connecting the first contact vias are thereafter formed. A metal interconnect layer containing a metal interconnect structure is formed over the second via-level dielectric layer to electrically connect the first and second set of semiconductor devices through the second contact vias and the inter-substrate vias.

Abstract: A semiconductor device having an improved gate process margin includes two active regions spaced apart from each other on a semiconductor substrate and respectively having bent sides with recesses and protrusions corresponding to each other, and two line-shaped gate patterns respectively formed in the longitudinal directions of the active regions. A gap at which the two gate patterns are spaced apart from each other by the recesses and the protrusions in the active regions is relatively narrower by a width difference between the recesses and the protrusions.

Abstract: An array substrate includes a substrate, a data line formed on the substrate, a passivation layer formed on the data line, a gate line including a gate electrode and a capacitor line formed on the passivation layer, a gate insulation layer formed on the gate electrode and the capacitor line, a semiconductor layer formed on the gate insulation layer, a contact hole formed through the passivation layer and the gate insulation layer to expose the data line and a source electrode and a drain electrode formed on the semiconductor layer. The capacitor electrode is overlapped with the data line. The source electrode is connected to the data line through the contact hole and the source electrode and the drain electrode include a transparent conductive material.

Abstract: It is an object of the present invention to provide a semiconductor device capable of additionally recording data at a time other than during manufacturing and preventing forgery due to rewriting and the like. Moreover, another object of the present invention is to provide an inexpensive, nonvolatile, and highly-reliable semiconductor device. A semiconductor device includes a first conductive layer, a second conductive layer, and an organic compound layer between the first conductive layer and the second conductive layer, wherein the organic compound layer can have the first conductive layer and the second conductive layer come into contact with each other when Coulomb force generated by applying potential to one or both of the first conductive layer and the second conductive layer is at or over a certain level.

Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield is etched through within the opening. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode.

Abstract: The memory device includes a first tunnel insulation layer pattern on a semiconductor substrate, a second tunnel insulation layer pattern having an energy band gap lower than that of the first tunnel insulation layer pattern on the first tunnel insulation layer pattern, a charge trapping layer pattern on the second tunnel insulation layer pattern, a blocking layer pattern on the charge trapping layer pattern, and a gate electrode on the blocking layer pattern. The memory device further includes a source/drain region at an upper portion of the semiconductor substrate. The upper portion of the semiconductor substrate is adjacent to the first tunnel insulation layer pattern.

Abstract: The present invention relates to a method for depositing a dielectric material comprising a transition metal compound. After providing a substrate, a first pre-cursor comprising a transition metal compound and a second pre-cursor predominantly comprising at least one of water vapour, ammonia and hydrazine are successively applied on the substrate for forming a first layer of transition metal containing material. In a next step the first pre-cursor and a third pre-cursor comprising at least one of ozone and oxygen are successively applied on the first layer for forming a second layer of the transition metal containing material.

Abstract: Method and apparatus are described for a memory cell includes a substrate, a body extending vertically from the substrate, a first gate having a vertical member and a horizontal member and a second gate comprising a vertical member and a horizontal member. The first gate is disposed laterally from the body and the second gate is disposed laterally from the first gate.

Abstract: A method of fabricating an image sensor which reduces fabricating costs through simultaneous formation of capacitor structures and contact structures may be provided. The method may include forming a lower electrode on a substrate, forming an interlayer insulating film on the substrate, the interlayer insulating film may have a capacitor hole to expose a first portion of the lower electrode.

Abstract: The present invention discloses a standby current erasion circuit applied in DRAM, which improves prior art word line driving circuit to have the word line voltage outputted in standby mode be equal to the bit line voltage, thereby the short DC standby current between the word line and bit line can be erased.

Abstract: A semiconductor device and its manufacture method wherein the semiconductor substrate has first and second insulating films, the first insulating film being an insulating film other than a silicon nitride film formed at least on a side wall of a conductive pattern including at least one layer of metal or metal silicide, and the second insulating film being a silicon nitride film formed to cover the first insulating film and the upper surface and side wall of the conductive pattern. The first insulating film may be formed to cover the upper surface and side wall of the conductive pattern. A semiconductor device and its manufacture method are provided which can realize high integrated DRAMs of 256 M or larger without degrading reliability and stability.

Abstract: A semiconductor device includes a first wiring line group made of a metal, wiring lines of the first wiring line group being arranged in parallel with each other, a second wiring line group which is made of a semiconductor and crosses the first wiring line group, wiring lines of the second wiring line group being arranged in parallel with each other and being movable in the vicinity of each intersection with the wiring lines of the first wiring line group, and a plurality of metal regions which are formed to be joined with the wiring lines constituting the second wiring line group, and have a work function different from that of the metal forming the first wiring line group.

Abstract: A method of forming a capacitor includes providing material having an opening therein over a node location on a substrate. A shield is provided within and across the opening, with a void being received within the opening above the shield and a void being received within the opening below the shield. The shield comprises a nitride. Etching is conducted within the opening through the nitride-comprising shield. After the etching, a first capacitor electrode is formed within the opening in electrical connection with the node location. A capacitor dielectric and a second capacitor electrode are formed operatively adjacent the first capacitor electrode. Other aspects and implementations are contemplated.

Abstract: A capacitor comprises: a lower electrode formed of a foil made of a polycrystalline metal; an upper conductor layer; and a dielectric layer disposed between the lower electrode and the upper electrode layer. Grain boundaries of the polycrystalline metal appear at the top surface of the lower electrode. The capacitor further comprises an insulator that is disposed between the top surface of the dielectric layer and the bottom surface of the upper electrode layer and that is present only in part of a region in which the top surface of the dielectric layer and the bottom surface of the upper electrode layer face each other. The insulator is disposed to cover at least part of the grain boundaries appearing at the top surface of the lower electrode when seen from above the top surface of the dielectric layer. The insulator is formed by electrophoresis.

Abstract: An MIM capacitor using a high-permittivity dielectric film such as tantalum oxide. The MIM capacitor includes an upper electrode, a dielectric film, and a lower electrode. A second dielectric film and the dielectric film are formed between the upper electrode and the lower electrode, at the end of the MIM capacitor. The second dielectric film is formed to have an opening at the top of the lower electrode. The dielectric film abuts the lower electrode via the opening. The upper electrode is formed on the dielectric film. The upper electrode and the dielectric film are formed in such a manner as to embrace the opening entirely, and the second dielectric film and the lower electrode are formed so that the respective widths are the same as, or greater than, the widths of the upper electrode and the dielectric film.

Abstract: A semiconductor-device manufacturing method includes forming an element separating insulating film on a semiconductor substrate; forming a gate multilayer film for forming a gate electrode thereon; removing the gate multilayer film in an alignment mark forming area positioned on the element separating insulating film; forming a pattern of a first conductive film in the element forming area; forming an alignment mark of the first conductive film, used in photolithography, in the alignment mark forming area surrounded by the gate multilayer film; forming an inter-layer insulating film thereon; removing the inter-layer insulating film in the alignment mark forming area, so that it remains on the gate multilayer film around the alignment mark forming area; removing or thinning the element separating insulating film around the alignment mark; and forming a pattern of a second conductive film on the inter-layer insulating film by performing alignment of the photolithography by using the alignment mark.

Abstract: A checkerboard deep trench dynamic random access memory cell array layout is disclosed, which includes a substrate, a plurality of gate conductor lines disposed on the substrate, a plurality of checkerboard-arranged and staggered deep trench capacitor structures embedded in the substrate under the gate conductor lines, and a plurality of active areas formed in the substrate under the gate conductor lines, alternatively arranged with the deep trench capacitor structures, and electrically connected with an adjacent deep trench capacitor structure. The width of the parts of the gate conductor lines above the deep trench capacitor structures is narrower than that of the parts of the gate conductor lines above the active areas.

Abstract: A capacitor capable of being formed in a vertical plane without an additional mask process and/or deposition process and a method of manufacturing the same are provided. The capacitor includes: a first conductive line formed on a substrate; a first interlayer dielectric including a first via hole formed at an upper portion of the first conductive line, and a second and third via hole pair formed at a region of the substrate; a first barrier metal layer and a contact plug formed in the first via hole; and first and second capacitor electrodes formed in the second and third via holes, respectively. The first and second capacitor electrodes and the first interlayer dielectric disposed between the first and second capacitor electrodes form a vertically constructed capacitor.

Abstract: A fuse area of a semiconductor device capable of preventing moisture-absorption and a method for manufacturing the fuse area are provided. When forming a guard ring for preventing permeation of moisture through the sidewall of an exposed fuse opening portion, an etch stop layer is formed over a fuse line. A guard ring opening portion is formed using the etch stop layer. The guard ring opening portion is filled with a material for forming the uppermost wiring of multi-level interconnect wirings or the material of a passivation layer, thereby forming the guard ring concurrently with the uppermost interconnect wiring or the passivation layer. Accordingly, permeation of moisture through an interlayer insulating layer or the interface between interlayer insulating layers around the fuse opening portion can be efficiently prevented by a simple process.

Abstract: In a semiconductor device having a capacitor and a method of fabricating the same, the semiconductor device comprises a semiconductor substrate having a memory cell array region and a peripheral region, a plurality of capacitors in the memory cell array region each having a storage electrode, a dielectric layer on the storage electrode, and a plate electrode on the dielectric layer, wherein an extended portion of the plate electrode extends in a direction toward the peripheral region, a dummy pattern in the peripheral region at an elevation above the semiconductor substrate that is substantially the same as that of the extended portion of the plate electrode and spaced apart from the extended portion of the plate electrode, an insulating layer formed on the plurality of capacitors in the cell array region and formed on the dummy pattern in the peripheral region, a first metal contact through the insulating layer between the extended portion of the plate electrode and the dummy pattern.

Abstract: A semiconductor device such as a DRAM memory device is disclosed. A substrate (12) of semiconductor material is provided with energy band modifying means in the form of a box region (38) and is covered by an insulating layer (14). A semiconductor layer (16) has source (18) and drain (20) regions formed therein to define bodies (22) of respective field effect transistors. The box region (38) is more heavily doped than the adjacent body (22), but less highly doped than the corresponding source (18) and drain (20), and modifies the valence and/or conduction band of the body (22) to increase the amount of electrical charge which can be stored in the body (22).

Abstract: A phase change memory device and a method of fabricating the same are disclosed. The phase change memory device includes a first conductor pattern having a first conductivity type and a sidewall. A second conductor pattern is connected to the sidewall of the first conductor pattern to form a diode. A phase change layer is electrically connected to the second conductor pattern and a top electrode is connected to the phase change layer.

Abstract: A phase change memory may be made with improved speed and stable characteristics over extended cycling. The alloy may be selected by looking at alloys that become stuck in either the set or the reset state and finding a median or intermediate composition that achieves better cycling performance. Such alloys may also experience faster programming and may have set and reset programming speeds that are substantially similar.

Abstract: A CMOS image sensor and method for fabricating same are provided. The CMOS image sensor can include a gate electrode formed on an active area of a first conductive type semiconductor substrate, on which a photodiode area and a transistor area are defined; a low-density second conductive type diffusion region formed on the photodiode area at a first side of the gate electrode; a high-density second conductive the diffusion region formed on the transistor area at a second side of the gate electrode; an insulating layer formed on the semiconductor substrate at both sides of the gate electrode with a thickness less than a thickness of the gate electrode, but greater than a thickness of a gate insulating layer; and insulating layer sidewalls formed on the insulating layer at both sides of the gate electrode.

Abstract: Phase change Random Access Memory (PRAM) devices include a substrate and a phase change layer pattern on the substrate. The phase change layer pattern includes a sharp tip and at least one wall that extends from the sharp tip in a direction away from the substrate. At least one contact hole node is provided that contacts the phase change material pattern adjacent the sharp tip.

Abstract: A semiconductor device includes a semiconductor substrate formed with a trench having a sidewall including a middle point. The trench includes a first part extending from a surface of the semiconductor substrate to the middle point of the trench and having a diameter that is gradually reduced as the first part extends deeper from the surface of the semiconductor substrate to the middle point of the trench. The trench includes a second part that is deeper than the middle point of the sidewall and that has a larger diameter than the middle point of the sidewall. An electrically conductive film is formed in an interior of the trench so as to be located lower than the middle point of the sidewall, the conductive film having a planarized upper surface, and a collar insulating film is formed on the conductive film and the sidewall of the trench so as to extend through the middle point of the sidewall along the sidewall.

Abstract: A semiconductor device includes a capacitor which includes a capacitor insulating film at least including a first insulating film and a ferroelectric film formed in contact with the first insulating film, containing a compound of a preset metal element and a constituent element of the first insulating film as a main component and having a dielectric constant larger than that of the first insulating film, a first capacitor electrode formed of one of Cu and a material containing Cu as a main component, and a second capacitor electrode formed to sandwich the capacitor insulating film in cooperation with the first capacitor electrode.

Abstract: There is provided a semiconductor device which comprises a first interlayer insulating film (first insulating film) formed over a silicon (semiconductor) substrate, a capacitor formed on the first interlayer insulating film and having a lower electrode, a dielectric film, and an upper electrode, a fourth interlayer insulating film (second insulating film) formed over the capacitor and the first interlayer insulating film, and a metal pattern formed on the fourth interlayer insulating film over the capacitor and its periphery to have a stress in an opposite direction to the fourth interlayer insulating film. As a result, characteristics of the capacitor covered with the interlayer insulating film can be improved.

Abstract: A memory cell and method of forming the same is provided. To make contact between a bit line and a select transistor of a dynamic memory unit on a semiconductor wafer, a contact hole is filled with a metal or a metal alloy. A liner layer may be introduced between the semiconductor substrate and the metal filling. The semiconductor substrate has a doped region in the contact hole.

Abstract: In the semiconductor device having a structure in which a plurality of layers are built-up by layers made of different materials or layers including various formed patterns, it is an object to provide a method which smoothing surface can be achieved without a polishing treatment by CMP method or a smoothing process by depositing a SOG film, a substrate material is not chosen, and the smoothing is simple and easy. In the semiconductor device in which a plurality of different layers are formed, smoothing surface can be achieved without the polishing treatment by the CMP method or the smoothing process by depositing the SOG film to a dielectric film formed on a dielectric film and a wring (electrode) or a semiconductor layer in a manner that an aperture portion is formed in the dielectric film, the wring (electrode) or the semiconductor layer is formed in the aperture portion.

Abstract: The present invention discloses capacitors having via connections and electrodes designed such that they provide a low inductance path, thus reducing needed capacitance, while enabling the use of embedded capacitors for power delivery and other uses. One embodiment of the present invention discloses a capacitor comprising the following: a top capacitor electrode and a bottom capacitor electrode, wherein the top electrode is smaller than the bottom electrode, comprising, on all sides of the capacitor; in an array, a multiplicity of vias located on all sides of the top and bottom capacitor electrodes, wherein the top electrode and the vias connecting to the top electrode act as an inner conductor, and the bottom electrode and the vias connecting to the bottom electrode act as an outer conductor.

Abstract: A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as a memory device. A method of forming the trap cites involves an atomic layer deposition of a material at pre-determined areas in the dielectric layer.

Abstract: Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming shallow trench isolation regions. The preferred sequence allows hybrid SOI CMOS fabrication without encountering problems caused by forming STI regions after epitaxy. A preferred device includes an NFET on a {100} crystal orientation and a PFET on a {110} crystal orientation. An NMOS channel may be oriented along the <100> direction, which is the direction of maximum electron mobility for a {100} substrate. A PMOS channel may be oriented along the <110> direction, which is the direction where hole mobility is maximum for a {110} substrate.

Abstract: A memory device able to be produced without requiring high precision alignment, a method of production of the same, and a method of use of a memory device produced in this way, wherein a peripheral circuit portion (first semiconductor portion) formed by a first minimum processing dimension is formed on a substrate, a memory portion (second semiconductor portion) formed by a second minimum processing dimension smaller than the first minimum processing dimension is stacked above it, and the memory portion (second semiconductor portion) is stacked with respect to the peripheral circuit portion (first semiconductor portion) with an alignment precision rougher than the second minimum processing dimension or wherein memory cells configured by 2-terminal devices are formed in regions where word lines and bit lines intersect in the memory portion, and contact portions connecting the word lines and bit lines and the peripheral circuit portions are arranged in at least two columns in directions in which the word lines

Abstract: The invention relates to a substrate for epitaxy, especially for preparation of nitride semiconductor layers. Invention covers a bulk nitride mono-crystal characterized in that it is a mono-crystal of gallium nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium nitride has a surface area greater than 100 mm2, it is more than 1,0 ?m thick and its C-plane surface dislocation density is less than 106/cm2, while its volume is sufficient to produce at least one further-processable non-polar A-plane or M-plane plate having a surface area at least 100 mm2. More generally, the present invention covers a bulk nitride mono-crystal which is characterized in that it is a mono-crystal of gallium-containing nitride and its cross-section in a plane perpendicular to c-axis of hexagonal lattice of gallium-containing nitride has a surface area greater than 100 mm2, it is more 1,0-?m thick and its surface dislocation density is less than 106/cm2.

Abstract: The semiconductor device comprises a semiconductor substrate 10 with a trench 16a and a trench 16b formed in; a device isolation film 32a buried in the trench 16a and including a liner film including a silicon nitride film 20 and an insulating film 28 of a silicon oxide-based insulating material; a device isolation film 32b buried in the bottom of the trench 16b; and a capacitor formed on a side wall of an upper part of the second trench 16b and including an impurity diffused region 40 as a first electrode, a capacitor dielectric film 43 of a silicon oxide-based insulating film and a second electrode 46.

Abstract: To achieve promotion of stability of operational function of display device and enlargement of design margin in circuit design, in a display device including a pixel portion having a semiconductor element and a plurality of pixels provided with pixel electrodes connected to the semiconductor element on a substrate, the semiconductor element includes a photosensitive organic resin film as an interlayer insulating film, an inner wall face of a first opening portion provided at the photosensitive organic resin film is covered by a second insulating nitride film, a second opening portion provided at an inorganic insulating film is provided on an inner side of the first opening portion, the semiconductor and a wiring are connected through the first opening portion and the second opening portion and the pixel electrode is provided at a layer on a lower side of an activation layer.

Abstract: A method for forming a capacitor comprises providing a substrate. A bottom electrode material layer is formed on the substrate. A first mask layer is formed on the bottom electrode material layer. A second mask layer is formed on the first mask layer. The second mask layer is patterned to form a patterned second mask layer in a predetermined region for formation of a capacitor. A plurality of hemispherical grain structures are formed on a sidewall of the patterned second mask layer. The first mask layer is etched by using the hemispherical grain structures and the patterned second mask layer as a mask, thereby forming a patterned first mask layer having a pattern. The pattern of the first mask layer is transferred to the bottom electrode material layer. And, a capacitor dielectric layer and a top electrode layer are formed on the bottom electrode material layer to form the capacitor.

Abstract: A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the body capacitance plate is precisely controlled. More specifically, the present invention forms the structure of a 1T-capacitorless SOI body charge storage cell having sidewall capacitor plates using a process that assures that there is 1) minimal overlap between plate and source/drain diffusions, and 2) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances. The inventive cell results in larger signal margin, improved performance, smaller chip size, and reduced dynamic power dissipation relative to the prior art.

Abstract: A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as a memory device. A method of forming the trap cites involves an atomic layer deposition,of a material at pre-determined areas in the dielectric layer.

Abstract: A semiconductor display device with an interlayer insulating film in which surface levelness is ensured with a limited film formation time, heat treatment for removing moisture does not take long, and moisture in the interlayer insulating film is prevented from escaping into a film or electrode adjacent to the interlayer insulating film. A TFT is formed and then a nitrogen-containing inorganic insulating film that transmits less moisture compared to organic resin film is formed so as to cover the TFT. Next, organic resin including photosensitive acrylic resin is applied and an opening is formed by partially exposing the organic resin film to light. The organic resin film where the opening is formed, is then covered with a nitrogen-containing inorganic insulating film which transmits less moisture than organic resin film does.

Abstract: A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.

Abstract: An EPROM cell includes a control gate and a control transistor. A portion of the control transistor is formed as a portion of the control gate.

Abstract: A semiconductor device includes a first trench capacitor formed in a first trench, a second trench capacitor formed in a second trench, a first gate electrode disposed above a first active area, a second gate electrode disposed above a second active area, a first impurity doped region formed in an outer periphery of the second trench including a boundary adjacent to the second trench and doped with an impurity of a first conduction type, and a second impurity doped region formed in the first impurity doped region so as to include the first active area located below the first gate electrode, the second impurity doped region being doped with an impurity of a second conduction type opposite to the first conduction type impurity.

Abstract: A method of forming memory circuitry having a memory array having a plurality of memory capacitors and having peripheral memory circuitry operatively configured to write to and read from the memory array, includes forming a dielectric well forming layer over a semiconductor substrate. A portion of the well forming layer is removed effective to form at least one well within the well forming layer. An array of memory cell capacitors is formed within the well. The peripheral memory circuitry is formed laterally outward of the well forming layer memory array well. In one implementation, memory circuitry includes a semiconductor substrate. A plurality of word lines is received over the semiconductor substrate. An insulative layer is received over the word lines and the substrate. The insulative layer has at least one well formed therein. The well has a base received over the word lines. The well peripherally defines an outline of a memory array area.

Abstract: This invention relates to a method and resulting structure, wherein a DRAM may be fabricated by using silicon midgap materials for transistor gate electrodes, thereby improving refresh characteristics of access transistors. The threshold voltage may be set with reduced substrate doping requirements. Current leakage is improved by this process as well.

Abstract: A TFT, in which source and drain electrodes having concentric circular shapes are formed, reduces an OFF current caused by a leakage current and optimizes an ON current and a stray capacitance between gate and source electrodes. The TFT includes a gate electrode formed on a substrate; and source and drain electrodes obtained by sequentially forming a gate insulating film, an intrinsic amorphous silicon layer, and an n+ amorphous silicon layer on the gate electrode, wherein the source and drain electrodes have circular shapes. One of the source and drain electrodes is disposed at the center, and the other one of the source and drain electrodes having a concentric circular shape surrounds the former. A channel region may be formed between the source and drain electrodes; and an area of an effective stray capacitance may be less than 150 ?m2. A ratio of a width of a channel to a length of the channel may be more than 4.5 and a filling capacity index to the effective stray capacitance may be less than 50.