Field Effect Device In Non-single Crystal, Or Recrystallized, Semiconductor Material Patents (Class 257/66)
  • Patent number: 11462646
    Abstract: A field-effect transistor including a semiconductor layer formed of an n-type metal oxide semiconductor, wherein the n-type metal oxide semiconductor includes indium oxide, wherein the indium oxide is n-type doped through introduction of one or more kinds of cations as dopants, and wherein the n-type metal oxide semiconductor has a peak detected at an angle corresponding to a (222) plane of indium oxide having a bixbite structure in an X-ray diffraction method using a two-dimensional detector.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: October 4, 2022
    Assignee: RICOH COMPANY, LTD.
    Inventors: Yukiko Abe, Yuichi Ando, Yuki Nakamura, Shinji Matsumoto, Yuji Sone, Naoyuki Ueda, Ryoichi Saotome, Sadanori Arae, Minehide Kusayanagi
  • Patent number: 11423838
    Abstract: An electro-optical device includes one or more control lines that include a scanning line, a data line and a pixel circuit. The pixel circuit has a drive transistor, a write-in transistor with a gate which is electrically connected to the scanning line, a light-emitting element that emits light at a brightness that depends on the size of a current that is supplied through the drive transistor, and a control line which overlaps the gate of the drive transistor when viewed from a direction that is perpendicular to a surface of a substrate on which the pixel circuit is formed is included in the one or more control lines.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: August 23, 2022
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Takashi Toya, Takehiko Kubota
  • Patent number: 11404437
    Abstract: A semiconductor device includes a semiconductor layer containing metal atoms, a charge storage layer provided on a surface of the semiconductor layer via a first insulating film, and an electrode layer provided on a surface of the charge storage layer via a second insulating film. The thickness of the first insulating film is 5 nm or more and 10 nm or less. The concentration of the metal atoms in the semiconductor layer is 5.0×1017 [EA/cm3] or higher and 1.3×1020 [EA/cm3] or lower.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: August 2, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Yuta Saito, Shinji Mori, Keiichi Sawa, Kazuhisa Matsuda, Kazuhiro Matsuo, Hiroyuki Yamashita
  • Patent number: 11387303
    Abstract: A display panel and a display device are provided. The display panel includes: a substrate, the substrate includes a plurality of pixel areas; a functional device layer, the functional device layer is disposed on the substrate; a plurality of via holes, the via holes are positioned on the functional device layer, and each of the via holes corresponds to one said first area; an organic layer, the organic layer is disposed on the functional device layer, and a portion of the organic layer extends into the via holes; a plurality of light emitting units; wherein, the via holes are positioned along an edge of a second area.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: July 12, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Jinrong Zhao
  • Patent number: 11387342
    Abstract: A semiconductor structure including nanosheet stacks on a substrate, each nanosheet stack including alternating layers of sacrificial semiconductor material and semiconductor channel material and a crystallized gate dielectric layer surrounding the semiconductor channel layers of a first subset of the nanosheet stacks, a dipole layer on top of the crystallized gate dielectric and surrounding the layers of semiconductor channel material of the first subset of the nanosheet stacks and a gate dielectric modified by a diffused dipole material surrounding the semiconductor channel layers of a second subset of the nanosheet stacks.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: July 12, 2022
    Assignee: International Business Machines Corporation
    Inventors: Jingyun Zhang, Takashi Ando, Choonghyun Lee, Alexander Reznicek
  • Patent number: 11380796
    Abstract: The disclosure relates to a thin film transistor. The thin film transistor may include a substrate, an active layer on the substrate, a gate on the active layer, and a source and a drain. The active layer may include a first conducting region, a second conducting region, and a channel region between the first conducting region and the second conducting region. An orthographic projection of the source and an orthographic projection of the drain on the substrate may cover at least an orthographic projection of a first conducting region and an orthographic projection of a second conducting region on the substrate.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: July 5, 2022
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Tongshang Su, Dongfang Wang, Jun Liu, Guangyao Li, Wei Li, Qinghe Wang, Chao Wang, Tao Sun
  • Patent number: 11374038
    Abstract: An array substrate and a manufacturing method thereof, wherein the array substrate includes a substrate; an active layer disposed on the substrate; a gate insulating layer disposed on the active layer; a gate disposed on the gate insulating layer; and a protection region dispose between the active layer and the gate, wherein the protection region is disposed on two sides of the gate and disposed on a same layer as the gate insulating layer.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: June 28, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Ming Xiang, Xing Ming
  • Patent number: 11374026
    Abstract: The present disclosure provides a TFT array substrate and a manufacturing method thereof. For the manufacturing method, a source electrode and a drain electrode are formed at first, and then edges of the source electrode and the drain electrode are used as masks to pattern a semiconductor layer to form an amorphous silicon island, which makes edges of the amorphous silicon island flush with the edges of the source electrode and the drain electrode, and completely removes the exposed semiconductor layer outside a metal layer, thereby decreasing photoelectric sensitivity of a TFT device, decreasing a size of the TFT device, and being beneficial for saving layouts and simplifying processes.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: June 28, 2022
    Inventor: Fen Long
  • Patent number: 11365476
    Abstract: The present disclosure generally relate to thin films incorporating high aspect ratio feature definitions and methods for forming the same. As gate height increases, 3D NAND gate stacks are subject to higher aspect ratio etching. Due to the current limitations of etching techniques, the vertical etch profile typically tapers as the depth into the gate stack increases. The inventors have devised a unique deposition scheme that compensates for etch performance degradation in deep trenches by a novel plasma-enhanced chemical vapor deposition (PECVD) film deposition method. The inventors have found that by grading various properties (e.g., refractive index, stress of the film, dopant concentration in the film) of the as-deposited films (e.g., silicon nitride) a more uniform etch profile can be achieved by compensating for variations in both dry and wet etch rates.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: June 21, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Praket P. Jha, Allen Ko, Xinhai Han, Thomas Jongwan Kwon, Bok Hoen Kim, Byung Ho Kil, Ryeun Kim, Sang Hyuk Kim
  • Patent number: 11362193
    Abstract: A method of fabricating air gap spacers is provided. The method includes forming gate structures to extend upwardly from a substrate with source or drain (S/D) regions disposed between the gate structures and with contact trenches defined above the S/D regions and between the gate structures. The method further includes disposing contacts in the contact trenches. The method also includes configuring the contacts to define open-ended air gap spacer trenches with the gate structures. In addition, the method includes forming a cap over the open-ended air gap spacer trenches to define the open-ended air gap spacer trenches as air gap spacers. The gate structures have an initial structure prior to and following the disposing and the configuring of the contacts and prior to and following the forming of the cap.
    Type: Grant
    Filed: October 24, 2019
    Date of Patent: June 14, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Choonghyun Lee, Juntao Li, Heng Wu, Peng Xu
  • Patent number: 11355395
    Abstract: A semiconductor device includes several first cell rows extending in a first direction, each of the first cell rows having a first row height; several second cell rows extending in the first direction, each of the second cell rows having a second row height smaller than the first row height, wherein the first cell rows and the second cell rows are interlaced; a first cell arranged in a first row of the first cell rows; and at least one second cell arranged in at least one row of the second cell rows, wherein the at least one second cell abuts the first cell in a second direction different from the first direction, wherein the at least one second cell and at least one circuit component included in the first cell have the same operation configuration.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jerry Chang-Jui Kao, Hui-Zhong Zhuang, Li-Chung Hsu, Sung-Yen Yeh, Yung-Chen Chien, Jung-Chan Yang, Tzu-Ying Lin
  • Patent number: 11355630
    Abstract: Semiconductor devices and methods of forming a semiconductor device that includes a polysilicon layer that may improve device reliability and/or a functioning of the device. An example device may include a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; and a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench.
    Type: Grant
    Filed: September 11, 2020
    Date of Patent: June 7, 2022
    Assignee: Wolfspeed, Inc.
    Inventors: Woongsun Kim, Daniel J. Lichtenwalner, Naeem Islam, Sei-Hyung Ryu
  • Patent number: 11342178
    Abstract: A method of manufacturing a low temperature polysilicon thin film, including: forming a buffer layer on a substrate; forming a silicon layer on the buffer layer; providing a mask; patterning the silicon layer through the mask, wherein the patterned silicon layer includes a plurality of recrystallization growth spaces; and annealing the silicon layer to form a polysilicon layer, and a partial silicon material of the polysilicon layer is formed on the recrystallization growth space.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: May 24, 2022
    Assignee: HKC CORPORATION LIMITED
    Inventor: Jianfeng Shan
  • Patent number: 11322620
    Abstract: Described herein are apparatuses, systems, and methods associated with metal-assisted transistors. A single crystal semiconductor material may be seeded from a metal. The single crystal semiconductor material may form a channel region, a source, region, and/or a drain region of the transistor. The metal may form the source contact or drain contact, and the source region, channel region, and drain region may be stacked vertically on the source contact or drain contact. Alternatively, a metal-assisted semiconductor growth process may be used to form a single crystal semiconductor material on a dielectric material adjacent to the metal. The portion of the semiconductor material on the dielectric material may be used to form the transistor. Other embodiments may be described and claimed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 3, 2022
    Assignee: Intel Corporation
    Inventors: Van H. Le, Ashish Agrawal, Seung Hoon Sung, Abhishek A. Sharma, Ravi Pillarisetty
  • Patent number: 11315946
    Abstract: A vertical semiconductor layer includes a common source semiconductor layer on a substrate, a support layer on the common source semiconductor layer, gates and interlayer insulating layers alternately stacked on the support layer, a channel pattern extending in a first direction perpendicular to an upper surface of the substrate while penetrating the gates and the support layer, a sidewall of the support layer facing the channel pattern being offset relative to sidewalls of the gates facing the channel pattern, and an information storage layer extending between the gates and the channel pattern, the information storage layer extending at least to the sidewall of the support layer facing the channel pattern.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bongyong Lee, Taehun Kim, Minkyung Bae, Myunghun Woo, Doohee Hwang
  • Patent number: 11267699
    Abstract: A modification to rough polysilicon using ion implantation and silicide is provided herein. A method can comprise depositing a hard mask on a single crystal silicon, patterning the hard mask, and depositing metal on the single crystal silicon. The method also can comprise forming silicide based on causing the metal to react with exposed silicon of the single crystal silicon. Further, the method can comprise removing unreacted metal and stripping the hard mask from the single crystal silicon. Another method comprises forming a MEMS layer, wherein the forming comprises fusion bonding a handle layer with a device layer. The method also can comprise implanting rough polysilicon on the device layer. Implanting the rough polysilicon can comprise performing ion implantation of the rough polysilicon. Further, the method can comprise performing high temperature annealing. The high temperature can comprise a temperature in a range between around 700 and 1100 degrees Celsius.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: March 8, 2022
    Assignee: INVENSENSE, INC.
    Inventors: Alan Cuthbertson, Daesung Lee
  • Patent number: 11264460
    Abstract: The present disclosure provides methods for forming a channel structure in a film stack for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and a channel structure formed in the film stack, wherein the channel structure is filled with a channel layer and a protective blocking layer, wherein the channel layer has a gradient dopant concentration along a vertical stacking of the film stack.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: March 1, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Arvind Kumar, Sanjeev Manhas, Mahendra Pakala, Ellie Y. Yieh
  • Patent number: 11257954
    Abstract: Provided are a thin film transistor including: a base cushion layer having a recessed portion, base insulating layer, source-drain layer and active layer. The base insulating layer is located on a side of the base cushion layer where the recessed portion is located, and has a first and second partition walls that are spaced apart, and an orthographic projection region of a gap region between the first and second partition walls onto the base cushion layer is located at a region where the recessed portion is located; and both orthographic projection regions of the first and second partition walls onto the base cushion layer partially overlap with the recessed portion region; and both the source-drain layer and the active layer are located on the side of the base insulating layer away from the base cushion layer.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: February 22, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaochen Ma, Guangcai Yuan, Ce Ning, Xin Gu, Hehe Hu
  • Patent number: 11257932
    Abstract: A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming an isolation structure surrounding the fin structure. The method also includes cleaning sidewalls of the fin structure. The method also includes depositing a silicon cap layer over the fin structure. The method also includes growing an oxide layer over the silicon cap layer. The silicon cap layer is thinned after growing an oxide layer over the silicon cap layer. The method also includes forming a gate structure over the oxide layer across the fin structure. The method also includes growing a source/drain epitaxial structure beside the gate structure. The method also includes forming a contact structure electrically connected to the gate structure.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: February 22, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ta-Chun Ma, Yee-Chia Yeo
  • Patent number: 11250750
    Abstract: A shift register circuit, a driving method thereof, a gate drive circuit and a display device are provided. The shift register circuit includes an input sub-circuit, an output sub-circuit, a discharge sub-circuit and a noise reduction sub-circuit. The input sub-circuit is connected to an input signal terminal, a first power source terminal and a pull-down node, and configured to, under the control of an input signal, output a first power source terminal signal to the pull-down node. In the shift register circuit, the discharge sub-circuit may control the potential of the pull-down node to be an ineffective potential at the input stage, thereby preventing the noise reduction sub-circuit from affecting the potentials of the pull-up node and the output terminal under the control of the pull-down node, and ensuring normal output of the shift register circuit.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: February 15, 2022
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zhichong Wang, Haoliang Zheng, Seungwoo Han, Guangliang Shang, Mingfu Han, Lijun Yuan, Xing Yao
  • Patent number: 11245016
    Abstract: A semiconductor apparatus has a silicon carbide substrate heavily doped with the first conductivity type and a lightly doped silicon carbide drift region of the first conductivity type over the silicon carbide substrate. A first body region in the drift region is doped with second conductivity type opposite the first. A first source region in the first body region is heavily doped with the first conductivity type. A gate trench is formed in the first source region and first body region. At least one sidewall of the gate trench is parallel to a crystal plane of the silicon carbide structure having greater carrier mobility than a C-face thereof. The gate trench extends a length of the first body region and the source region to a separation region laterally adjacent to the first region wherein the separation region is in the drift region.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: February 8, 2022
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR (CAYMAN) LTD.
    Inventors: David Sheridan, Vipindas Pala, Madhur Bobde
  • Patent number: 11236017
    Abstract: Glass articles and methods for modifying a composition of a surface portion of the glass article are disclosed. The method includes heating the surface portion of the glass article with a laser beam to a temperature within a range of about 1100?C to about 2200?C such that the heating evaporates one or more metalloids and/or one or more alkali metals present at the surface portion, and modifies the composition of the surface portion such that the surface portion has a lower alkali metals concentration and/or a lower metalloids concentration as compared to a portion of the glass article that is not heated by the laser beam.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: February 1, 2022
    Assignee: CORNING INCORPORATED
    Inventors: Matthew John Dejneka, Stuart Gray
  • Patent number: 11227879
    Abstract: A semiconductor device includes an insulating substrate, a polysilicon layer formed on the insulating substrate, a first-gate-insulating layer formed on the polysilicon layer, a first metal layer formed on the first-gate-insulating layer, an oxide-semiconductor layer formed on the first-gate-insulating layer, a second-gate-insulating layer formed on the oxide-semiconductor layer, a second metal layer formed on the second-gate-insulating layer, a first insulating interlayer formed on the second metal layer, a third metal layer formed on the first insulating interlayer, a first top gate planar type thin film transistor in which the polysilicon layer serves as a channel and which has a source, a drain and a gate, and a second top gate planar self-aligned type thin film transistor in which the oxide-semiconductor layer serves as a channel and which has a source, a drain and a gate, wherein the gate of the first top gate planar type thin film transistor is made of a first metal layer, the gate of the second top ga
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: January 18, 2022
    Assignee: TIANMA MICROELECTRONICS CO., LTD.
    Inventor: Kazushige Takechi
  • Patent number: 11221359
    Abstract: Techniques regarding determining device operability via a metal-induced layer exchange are provided. For example, one or more embodiments described herein can comprise an apparatus, which can comprise a dielectric membrane positioned between an amorphous semiconductor resistor layer and an electrically conductive metal layer. The dielectric membrane can facilitate a metal induced layer exchange that can experiences catalyzation by heat generated from operation of a semiconductor device positioned adjacent to the apparatus.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: January 11, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dexin Kong, Kangguo Cheng
  • Patent number: 11205660
    Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. The strings of memory cells in the stack comprise channel-material strings and storage-material strings extending through the insulative tiers and the conductive tiers. At least some of the storage material of the storage-material strings in individual of the insulative tiers are intrinsically less charge-transmissive than is the storage material in the storage-material strings in individual of the conductive tiers. Other aspects, including method, are disclosed.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: December 21, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Manzar Siddik, Chris M. Carlson, Terry H. Kim, Kunal Shrotri, Srinath Venkatesan
  • Patent number: 11201147
    Abstract: A composite power element and a method for manufacturing the same are provided. The power element includes a substrate structure, an insulation layer, a dielectric layer, a metal-oxide-semiconductor field-effect transistor (MOSFET), and a zener diode. The MOSFET is formed in a transistor formation region of the substrate structure. The zener diode is formed in a circuit element formation region of the substrate structure, and includes a zener diode doped structure formed on the insulation layer and covered by the dielectric layer. The zener diode doped structure includes a P-type doped region and an N-type doped region. The zener diode includes a zener diode metal structure formed on the dielectric layer and partially passes through the dielectric layer to be electrically connected to the P-type doped region and the N-type doped region. The zener diode is configured to receive a reverse bias voltage when the power element is energized.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: December 14, 2021
    Assignee: CYSTECH ELECTRONICS CORP.
    Inventors: Hsin-Yu Hsu, Chen-Huang Wang, Shih-Chieh Hung
  • Patent number: 11201214
    Abstract: A semiconductor device includes a stack structure including conductive layers and insulating layers that are alternately stacked with each other, a first channel layer passing through the stack structure and including a metal oxide-based semiconductor, and a second channel layer adjacent to the first channel layer and including the metal oxide-based semiconductor, wherein the first channel layer has a higher oxygen content than the second channel layer and has a different thickness from the second channel layer.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: December 14, 2021
    Assignees: SK hynix Inc., Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Young Jun Tak, Tae Soo Jung, Won Gi Kim
  • Patent number: 11195862
    Abstract: A thin film transistor includes an active layer on a substrate, a gate electrode configured to be spaced from the active layer and partially overlapped with the active layer, and a gate insulating layer, at least a part of the gate insulating layer being disposed between the active layer and the gate electrode, wherein the gate insulating layer includes a first gate insulating layer between the active layer and the gate electrode, and a second gate insulating layer configured to have a dielectric constant (k) which is different from a dielectric constant of the first gate insulating layer, and disposed in a same layer as the first gate insulating layer, and wherein at least a part of the second gate insulating layer is disposed between the active layer and the gate electrode.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: December 7, 2021
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Jaeman Jang, InTak Cho
  • Patent number: 11189681
    Abstract: An OLED display according to an exemplary embodiment includes: a substrate; a gate insulation layer that is disposed on the substrate; and a gate wire that is disposed on the gate insulation layer, and includes a gate electrode, wherein the gate wire includes a single layer of aluminum or an aluminum alloy, and an angle formed by side surfaces of the gate wire and the gate insulation layer is less than 65°.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: November 30, 2021
    Inventors: Kyeong Su Ko, Joon Geol Lee, Shin Il Choi, Sang Gab Kim, Hyun Min Cho, Hyun Eok Shin
  • Patent number: 11189566
    Abstract: In accordance with an embodiment of the present invention, a photolithographic mask is provided. The photolithographic mask includes at least one merged via pattern in the photolithographic mask for printing a merged via opening in a resist layer, wherein the at least one merged via pattern includes a compound shape having a first rectangular opening portion and a second rectangular opening portion that intersect at an angle.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: November 30, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dongbing Shao, Lawrence A. Clevenger, Shyng-Tsong Chen, Hao Tang, Jing Sha
  • Patent number: 11189629
    Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include conductive structures. Channel material extends vertically through the stack. The conductive structures have proximal regions near the channel material, and have distal regions further from the channel material than the proximal regions. The insulative levels have first regions vertically between the proximal regions of neighboring conductive structures, and have second regions vertically between the distal regions of the neighboring conductive structures. Voids are within the insulative levels and extend across portions of the first and second regions. Some embodiments include methods for forming integrated assemblies.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: November 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shyam Surthi, Richard J. Hill
  • Patent number: 11177279
    Abstract: In an example, a method of forming a stacked memory array includes forming a stack of alternating first and second dielectrics, forming a termination structure through the stack, the termination structure comprising a dielectric liner around a conductor, forming a set of contacts concurrently with forming the termination structure, forming a third dielectric over an upper surface of the stack and an upper surface of the termination structure, forming a first opening through the third dielectric and the stack between first and second groups of semiconductor structures so that the first opening exposes an upper surface of the conductor, and removing the conductor from the termination structure to form a second opening lined with the dielectric liner. In some examples, the dielectric liner can include a rectangular or a triangular tab or a pair of prongs that can have a rectangular profile or that can be tapered.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: November 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Matthew J. King, Anilkumar Chandolu, Indra V. Chary, Darwin A. Clampitt, Gordon Haller, Thomas George, Brett D. Lowe, David A. Daycock
  • Patent number: 11171207
    Abstract: A transistor includes a body of semiconductor material with a gate structure in contact with a portion of the body. A source region contacts the body adjacent the gate structure and a drain region contacts the body adjacent the gate structure such that the portion of the body is between the source region and the drain region. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: November 9, 2021
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Cheng-Ying Huang, Matthew V. Metz, Nicholas G. Minutillo, Sean T. Ma, Anand S. Murthy, Jack T. Kavalieros, Tahir Ghani, Gilbert Dewey
  • Patent number: 11158697
    Abstract: A display device includes: a substrate; a buffer layer on the substrate; a first active pattern and a second active pattern on the buffer layer and spaced apart from each other; a first gate insulation layer on the first active pattern and the second active pattern; a first gate electrode and a second gate electrode on the first gate insulation layer, the first gate electrode and the second gate electrode respectively overlapping the first active pattern and the second active pattern; a second gate insulation layer on the first gate electrode and the second gate electrode; and a capacitor electrode on the second gate insulation layer, the capacitor electrode overlapping the first gate electrode, wherein a permittivity of the first gate insulation layer is greater than a permittivity of the buffer layer.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: October 26, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin Woo Lee, Jintaek Kim, Yeonhong Kim, Pilsuk Lee
  • Patent number: 11158547
    Abstract: A semiconductor device including a first source/drain region at a lower portion thereof, a second source/drain region at an upper portion thereof, a channel region between the first source/drain region and the second source/drain region and close to peripheral surfaces thereof, and a body region inside the channel region. The semiconductor device may further include a gate stack formed around a periphery of the channel region.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: October 26, 2021
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventor: Huilong Zhu
  • Patent number: 11150140
    Abstract: An apparatus includes a substrate, a nested enclosure assembly including an outer enclosure and an inner enclosure, wherein the outer enclosure encloses the inner enclosure and the inner enclosure encloses at least the electronic assembly. An insulating medium is disposed within a cavity between the outer surface of the inner enclosure and the inner surface of the outer enclosure and the system includes a sensor assembly communicatively coupled to the electronic assembly. The sensor assembly includes one or more sensors that are configured to acquire one or more measurement parameters at one or more locations of the substrate. The electronic assembly is configured to receive the one or more measurement parameters from the one or more sensors.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: October 19, 2021
    Assignee: KLA Corporation
    Inventors: Mei Sun, Vaibhaw Vishal
  • Patent number: 11145833
    Abstract: A stretchable display according to one embodiment of the present invention comprises: a hybrid stretchable substrate divided into a low stretchable region and a high stretchable region having a modulus lower than that of the low stretchable region; a driving element layer including a driving element on the low stretchable region so as to control a light emitting layer, and wiring on the high stretchable region so as to be electrically connected to a part of the driving element to apply an electrical signal; and the light emitting layer provided on the driving element layer, and electrically connected to the driving element layer to emit light, wherein, between the driving element and the wiring, the wiring can overlap a stretchable mask pattern having a shape corresponding to either the low stretchable region or high stretchable region.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: October 12, 2021
    Assignee: Korea University Research and Business Foundation, Sejong Campus
    Inventors: Sang Il Kim, Mun Pyo Hong, Dong Hyeok Lee, Ho Won Yoon, Min Hyun Jung
  • Patent number: 11121143
    Abstract: Some embodiments include an integrated assembly having a conductive expanse over conductive nodes. The conductive nodes include a first composition. A bottom surface of the conductive expanse includes a second composition which is different composition than the first composition. A stack is over the conductive expanse. The stack includes alternating first and second levels. Pillar structures extend vertically through the stack. Each of the pillar structures includes a post of conductive material laterally surrounded by an insulative liner. At least one of the posts extends through the conductive expanse to directly contact one of the conductive nodes. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shuangqiang Luo, Indra V. Chary, Justin B. Dorhout, Rita J. Klein
  • Patent number: 11114469
    Abstract: The present disclosure is in the field of display technologies, and provides an array substrate including an IGZO film layer, a gate layer, and a gate insulating layer. The gate layer is provided with broken lines at a position thereof overlapping the IGZO film layer to form a first gate line and a second gate line. The gate insulating layer is disposed between the IGZO film layer and the gate layer, and is provided with at least two through holes thereon, in which the first gate line is connected with the IGZO film layer through one of the through holes, and the second gate line is connected with the IGZO film layer through another through hole, thus, connecting the IGZO film layer in series into the gate layer.
    Type: Grant
    Filed: April 28, 2019
    Date of Patent: September 7, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Bin Zhou, Binbin Cao, Liangchen Yan, Dongfang Wang, Ce Zhao, Luke Ding, Jun Liu
  • Patent number: 11101387
    Abstract: A low temperature polysilicon layer, a thin film transistor, and a method for manufacturing same are provided. The low temperature polysilicon layer includes a substrate, at least one buffer layer, and a polysilicon layer. The polysilicon layer is disposed on the at least one buffer layer. The polysilicon layer includes a channel region, two low doped regions disposed on two sides of the channel region, and two high doped regions disposed on an outer side of the low doped regions. Thicknesses of an edge of the channel region and at least one portion of the low doped regions are less than a thickness of another position of the polysilicon layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: August 24, 2021
    Inventors: Lisheng Li, Peng He, Yuan Yan
  • Patent number: 11094822
    Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall cavities formed in the semiconductor substrate on opposite sides of the gate structure. In this example, each of the first and second overall cavities comprise a substantially vertically oriented upper epitaxial cavity and a lower insulation cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower insulation cavity. The transistor also includes an insulation material positioned in at least a portion of the lower insulation cavity of each of the first and second overall cavities and epitaxial semiconductor material positioned in at least the substantially vertically oriented upper epitaxial cavity of each of the first and second overall cavities.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: August 17, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Arkadiusz Malinowski, Baofu Zhu, Judson R. Holt, Shiv Kumar Mishra
  • Patent number: 11043653
    Abstract: Optoelectronic devices that include a composite film in a multilayered encapsulation stack are provided. Also provided are methods of forming the light reflection-modifying structures, as well as other polymeric device layers, using inkjet printing. The composite films include a first, lower refractive index domain and a second, higher refractive index domain.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 22, 2021
    Assignee: KATEEVA, INC.
    Inventors: Florian Pschenitzka, Christopher D. Favaro
  • Patent number: 11022757
    Abstract: Embodiments herein describe a photonic platform where an AR coating is disposed between an optical grating and a semiconductor substrate. In one embodiment, the optical grating is disposed within an insulative layer. A first side of the insulative layer provides an optical interface where an external optical source can transmit an optical signal into, or a receive an optical signal from, the grating. A second, opposite side of the insulative layer contacts the AR coating. When the external optical source transmits light through the first side of the insulative layer, some of the light passes through the grating and reaches the AR coating. The AR coating prevents this light from being reflected back to the grating by the semiconductor layer which can cause interference that varies the coupling efficiency of the grating.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: June 1, 2021
    Assignee: Cisco Technology, Inc.
    Inventors: Xunyuan Zhang, Shiyi Chen, Tao Ling, Prakash B. Gothoskar
  • Patent number: 11004954
    Abstract: Integrated circuit transistor structures are disclosed that include a single crystal buffer structure that is lattice matched to the underlying single crystal silicon substrate. The buffer structure may be used to reduce sub-fin leakage in non-planar transistors, but can also be used in planar configurations. In some embodiments, the buffer structure is a single continuous layer of high bandgap dielectric material that is lattice matched to silicon. The techniques below can be utilized on NMOS and PMOS transistors, including any number of group IV and III-V semiconductor channel materials.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Glenn A. Glass, Anand S. Murthy, Jack T. Kavalieros, Seung Hoon Sung, Benjamin Chu-Kung, Tahir Ghani
  • Patent number: 10978355
    Abstract: A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
  • Patent number: 10978564
    Abstract: The present disclosure relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor layer; a source electrode, a drain electrode and a gate electrode located between the source electrode and the drain electrode disposed on a side of the semiconductor layer; at least two dielectrics located between the gate electrode and the drain electrode, wherein a dielectric coefficient of a dielectric adjacent to the gate electrode is greater than that of a dielectric away from the gate electrode and adjacent to the drain electrode.
    Type: Grant
    Filed: November 23, 2018
    Date of Patent: April 13, 2021
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventor: Yuan Li
  • Patent number: 10971512
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: April 6, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Hidenobu Nagashima
  • Patent number: 10964268
    Abstract: The present disclosure provides a shift register, a driving method thereof, a scan driving circuit and a display device. The shift register includes: a first node control module configured to control level at the first node based on an input signal and a second clock signal; a second node control module configured to control level at a second node based on the input signal, the first clock signal, the second clock signal, a low level signal and a high level signal; and an output control module configured to control the output terminal to output high level or low level based on level at the first node, level at the second node and the second clock signal. The second node can be provided with a relatively low level, which is conductive to maintaining a normal output of the shift register.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: March 30, 2021
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventors: Renyuan Zhu, Yue Li, Dongxu Xiang, Yana Gao, Xingyao Zhou
  • Patent number: 10957754
    Abstract: A display device includes a display panel including a flexible region and a low flexibility region, wherein the flexible region may include a first transistor including a first semiconductor layer and a first gate electrode, a first conductor connected to the first semiconductor layer, and a first interlayer insulating layer between the first transistor and the first conductor. The low flexibility region may include a second transistor including a second semiconductor layer and a second gate electrode, a second conductor connected to the second semiconductor layer, and a second interlayer insulating layer between the second transistor and the second conductor. The first interlayer insulating layer may include an organic insulating material, the second interlayer insulating layer includes an inorganic insulating material, and a ratio of channel width to channel length of the first transistor may be different from that of the second transistor.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 23, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: June Woo Lee, Shin Moon Kang, Byoung Ki Kim, Hee Kyung Kim, Hyun Chui Son, Yun-Mo Chung, Jae Beom Choi
  • Patent number: 10950677
    Abstract: The present disclosure provides an array substrate and a manufacturing method of the array substrate, and a display panel. The array substrate includes a flexible substrate; an active layer disposed on the flexible substrate; a first gate insulating layer disposed on the active layer; a first gate layer disposed on the first gate insulating layer; a second gate insulating layer disposed on the first gate insulating layer and the first gate layer; and a second gate layer disposed on the second gate insulating layer. The array substrate of the present disclosure replaces molybdenum wires of a gate layer and a second gate layer with a multi-layered composite metal layer. The bending tolerance of gate wires in the display panel is enhanced and increase of impedance of the first gate layer is prevented.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: March 16, 2021
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Yun Yu, Weiwei Yang