Field Effect Device In Non-single Crystal, Or Recrystallized, Semiconductor Material Patents (Class 257/66)
  • Patent number: 10777464
    Abstract: A method of forming a semiconductor device that includes forming a vertically orientated channel in a semiconductor fin structure that is present on a supporting substrate; and depositing a doped amorphous semiconductor material on an upper surface of the semiconductor fin structure that is opposite a base surface of the semiconductor fin structure that is in contact with the supporting substrate. The method further includes recrystallizing the doped amorphous semiconductor material with an anneal duration for substantially a millisecond duration or less to provide a doped polycrystalline source and/or drain region at the upper surface of the semiconductor fin structure.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Shogo Mochizuki, Oleg Gluschenkov
  • Patent number: 10770480
    Abstract: Systems, methods and apparatus for coexistence of high voltage and low voltage devices and circuits on a same integrated circuit fabricated in silicon-on-insulator (SOI) technology are described. In particular, techniques for mitigating back gate effects are described, including using of resistive and/or capacitive couplings to control surface potentials at regions of a substrate used for the SOI fabrication proximate the high voltage and low voltage devices and circuits. In one case, an N-type implant is used to provide a high potential differential with respect to a substrate potential.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: September 8, 2020
    Assignee: pSemi Corporation
    Inventors: Buddhika Abesingha, Simon Edward Willard, Alain Duvallet, Merlin Green, Sivakumar Kumarasamy
  • Patent number: 10768731
    Abstract: A display device and method of manufacturing the same are provided. A display device includes: a device substrate, a light-emitting element on the device substrate, an encapsulating structure on the light-emitting element, a touch structure on the encapsulating structure, an elastic insulating layer on the touch structure, the elastic insulating layer including an elastic material, and a high-permittivity particles dispersed in the elastic insulating layer.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: September 8, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Young-Sub Shin, Byong-Hoo Kim
  • Patent number: 10756132
    Abstract: The present technology relates to a solid-state imaging device capable of protecting a photoelectric conversion film with a sealing film that has excellent sealing properties and coverage, a method of manufacturing the solid-state imaging device, and an electronic apparatus. A solid-state imaging device includes: a photoelectric conversion film formed on the upper side of a semiconductor substrate; and a sealing film that is formed on the upper layer of the photoelectric conversion film and has a lower etching rate than that of silicon oxide. The present technology can be applied to solid-state imaging devices having a photoelectric conversion film on the upper side of a semiconductor substrate, and the like, for example.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: August 25, 2020
    Assignee: SONY CORPORATION
    Inventors: Shigehiro Ikehara, Masahiro Joei
  • Patent number: 10700165
    Abstract: A doped diamond semiconductor and method of production using a laser is disclosed herein. As disclosed, a dopant and/or a diamond or sapphire seed material may be added to a graphite based ablative layer positioned below a confinement layer, the ablative layer also being graphite based and positioned above a backing layer, to promote formation of diamond particles having desirable semiconductor properties via the action of a laser beam upon the ablative layer. Dopants may be incorporated into the process to activate the reaction sought to produce a material useful in production of a doped semiconductor or a doped conductor suitable for the purpose of modulating the electrical, thermal or quantum properties of the material produced. As disclosed, the diamond particles formed by either the machine or method of confined pulsed laser deposition disclosed may be arranged as semiconductors, electrical components, thermal components, quantum components and/or integrated circuits.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: June 30, 2020
    Assignee: Adamantite Technologies LLC
    Inventor: Eric David Bauswell
  • Patent number: 10700182
    Abstract: By using at least one of a processor device and model transistor cells, a set of design parameters for at least one of a transistor cell and a drift structure of a wide band-gap semiconductor device is determined, wherein an on state failure-in-time rate and an off state failure-in-time rate of a gate dielectric of the transistor cell are within a same order of magnitude for a predefined on-state gate-to-source voltage, a predefined off-state gate-to-source voltage, and a predefined off-state drain-to-source voltage.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Wolfgang Bergner, Romain Esteve, Daniel Kueck, Dethard Peters, Ralf Siemieniec, Bernd Zippelius
  • Patent number: 10700082
    Abstract: A semiconductor storage device includes a base body, a stacked body, a plurality of columns, and a plurality of first contacts. The base body includes a substrate, a semiconductor element on the substrate, a lower wiring layer above the semiconductor element in a thickness direction of the base body and connected to the semiconductor element, and a lower conductive layer above the lower wiring layer in the thickness direction. The stacked body is above the lower conductive layer and including an alternating stack of conductive layers and insulating layers. Each of the columns includes a semiconductor body extending through the stacked body and electrically connected to the lower conductive layer. The plurality of first contacts extend through the stacked body and electrically connected to the lower conductive layer. The lower conductive layer is separately provided under each of the plurality of first contacts.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: June 30, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Go Oike
  • Patent number: 10685958
    Abstract: Disclosed herein is a composite transistor which includes a first transistor including a control electrode, a first active region, a first A extending part, and a first B extending part, and a second transistor including a control electrode, a second active region, a second A extending part, and a second B extending part. The first active region, the second active region, and the control electrode overlap one another. Both the first A extending part, and the first B extending part extend from the first active region and both the second A extending part and the second B extending part extend from the second active region. The first electrode is connected to the first A extending part, the second electrode is connected to the second A extending part, and the third electrode is connected to the first B extending part and the second B extending part.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 16, 2020
    Assignee: Sony Corporation
    Inventor: Koichi Matsumoto
  • Patent number: 10679861
    Abstract: A manufacturing method of a semiconductor device comprises forming an ohmic electrode on a surface of a semiconductor substrate, the ohmic electrode including an aluminum layer in a side opposite to a side in contact with the semiconductor substrate, performing a heat treatment on the ohmic electrode, performing an acid treatment on a surface of the aluminum layer in the ohmic electrode that has been subjected to the heat treatment and forming a wiring electrode in the side of the aluminum layer opposite to the side where the semiconductor substrate is provided after the acid treatment.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: June 9, 2020
    Assignee: TOYODA GOSEI CO., LTD.
    Inventor: Kota Yasunishi
  • Patent number: 10656491
    Abstract: A liquid-crystal display including: a gate line extending in a first direction; a gate electrode protruding from the gate line; a gate insulating layer arranged on the gate electrode; an active layer arranged on the gate insulating layer while being insulated from the gate electrode; a data line arranged on the active layer and extending in a second direction; a source electrode protruding from the data line, having a portion overlapping the gate electrode on a plane, and including a plurality of source electrode branches that are separate from each other; a drain electrode being separate from the source electrode, and including a plurality of drain electrode branches, each being arranged between two of the plurality of source electrode branches, and a drain electrode connecting part connecting the plurality of drain electrode branches; a pixel electrode defining a pixel region; a liquid-crystal layer arranged on the pixel electrode.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: May 19, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gichang Lee, Yongjo Kim, Cholho Kim, Gunwoo Yang, Jihoon Yang, Yongwoo Lee
  • Patent number: 10651190
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: May 12, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Hidenobu Nagashima
  • Patent number: 10650731
    Abstract: The disclosure provides a display apparatus. The display apparatus of the disclosure includes a substrate having a plurality of pixel regions, a plurality of active elements, a plurality of first signal lines and second signal lines, a plurality of ground signal lines and a plurality of light emitting diodes (LEDs). The plurality of ground signal lines are disposed on the substrate and arranged to alternate with the first signal lines. At least one LED has first and second electrodes. The first electrode of at least one LED is electrically connected with a corresponding active element. A second electrode of at least one LED is electrically connected with a corresponding ground signal line. At least two LEDs disposed in an identical pixel region is electrically connected with an identical ground signal line between two first signal lines adjacent to each other. The display apparatus of the disclosure has high resolution.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: May 12, 2020
    Assignee: Innolux Corporation
    Inventors: Chun-Hsien Lin, Chih-Yung Hsieh, Tsau-Hua Hsieh, Shu-Ming Kuo
  • Patent number: 10641957
    Abstract: In integrated optical structures (e.g., silicon-to-silicon-nitride mode converters) implemented in semiconductor-on-insulator substrates, wire waveguides whose sidewalls substantially consist of portions coinciding with crystallographic planes and do not extend laterally beyond the top surface of the wire waveguide may provide benefits in performance and/or manufacturing needs. Such wire waveguides may be manufactured, e.g., using a dry-etch of the semiconductor device layer down to the insulator layer to form a wire waveguide with exposed sidewalls, followed by a smoothing crystallographic wet etch.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: May 5, 2020
    Assignee: Juniper Networks, Inc.
    Inventors: Avi Feshali, John Hutchinson, Jared Bauters
  • Patent number: 10636914
    Abstract: A crystalline oxide semiconductor thin film that is composed mainly of indium oxide and comprises surface crystal grains having a single crystal orientation.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: April 28, 2020
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Kazuyoshi Inoue, Futoshi Utsuno, Yuki Tsuruma, Shigekazu Tomai, Kazuaki Ebata
  • Patent number: 10629626
    Abstract: A display apparatus including a first thin film transistor disposed on a substrate and including a first active layer, a second thin film transistor disposed on the first thin film transistor and including a second active layer overlapping the first thin film transistor, a first planarization layer disposed between the first thin film transistor and the second thin film transistor, the first planarization layer including a first insulating layer and a second insulating layer disposed on the first insulating layer, and a first buffer layer disposed between the first planarization layer and the second thin film transistor, in which an upper surface of the second insulating layer and an upper surface of the first insulating layer are substantially flush with each other.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: April 21, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yunmo Chung, Daewoo Lee, Ilhun Seo, Hojin Yoon
  • Patent number: 10622484
    Abstract: The present invention provides a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer, which are laminated on a substrate. The semiconductor layer is a polysilicon thin film. The polysilicon thin film in regions corresponding to the source electrode and the drain electrode has a smaller crystal grain size than that of the polysilicon thin film in a channel region between the source electrode and the drain electrode.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: April 14, 2020
    Assignee: V TECHNOLOGY CO., LTD.
    Inventors: Michinobu Mizumura, Makoto Hatanaka, Tetsuya Kiguchi
  • Patent number: 10580902
    Abstract: A transistor may include a semiconductor, a source electrode, a drain electrode, and a gate electrode. The semiconductor may include a first doped region, a second doped region, a source region, a drain region, and a channel region. The channel region is positioned between the source region and the drain region. The first doped region is positioned between the channel region and the source region. The second doped region is positioned between the channel region and the drain region. A doping concentration of the first doped region is lower than a doping concentration of the source region. A doping concentration of the second doped region is lower than a doping concentration of the drain region. The source electrode is electrically connected to the source region. The drain electrode is electrically connected to the drain region. The gate electrode overlaps the channel region.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: March 3, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji Hun Lim, Joon Seok Park, Jay Bum Kim, Jun Hyung Lim, Kyoung Seok Son
  • Patent number: 10580801
    Abstract: The purpose of the invention is to form a flexible display device where the substrate is made of resin, wherein the TFT can be annealed in high temperature; consequently, a reliability of the TFT is improved. The concrete measure is as follows. A display device having a pixel electrode and a TFT including a semiconductor layer on a substrate comprising: a source region of the semiconductor layer connects with a source electrode, a drain region of the semiconductor layer connects with a drain electrode; the pixel electrode connects with the source electrode; the drain electrode connects with a video signal line; a distance between the drain electrode and the substrate is smaller than a distance between the semiconductor and the substrate, the semiconductor layer is formed between the pixel electrode and the substrate.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: March 3, 2020
    Assignee: Japan Display Inc.
    Inventors: Isao Suzumura, Hajime Watakabe, Akihiro Hanada, Hirokazu Watanabe, Yohei Yamaguchi, Marina Shiokawa, Ryotaro Kimura
  • Patent number: 10566400
    Abstract: A display device includes a substrate having flexibility, a transistor having a gate insulating film and further having a semiconductor layer and a gate electrode that sandwich the gate insulating film, the transistor formed in an area where the substrate is bent, and a gate wiring line so formed on the substrate as to be connected to the gate electrode, and the gate electrode has an area that is present in an area where the gate electrode overlaps with the semiconductor layer and is thinner than at least part of the gate wiring line.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: February 18, 2020
    Assignee: Japan Display Inc.
    Inventors: Yasukazu Kimura, Masato Hiramatsu, Takuma Nishinohara, Toshihiko Itoga
  • Patent number: 10559645
    Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a substrate and an active pattern formed over the substrate and including first to fourth regions. A gate insulation layer is formed over the active pattern and the substrate, and a first gate electrode is formed over the gate insulation layer and partially overlapping the active pattern. The first gate electrode, the first region and the second region define a first transistor. A second gate electrode is formed on the same layer as the first gate electrode. The second gate electrode, the third region and the fourth region define a second transistor, and the second gate electrode, the second region and the fourth region define a third transistor. A first insulating interlayer is formed over the first gate electrode, the second gate electrode, and the gate insulation layer.
    Type: Grant
    Filed: March 16, 2017
    Date of Patent: February 11, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sun-Ja Kwon, Jae-Yong Lee, Ji-Eun Lee, So-Young Kang, Sang-Ho Seo
  • Patent number: 10559592
    Abstract: Methods and structures of a three-dimensional memory device are disclosed. In an example, the memory device includes a substrate and a first alternating conductor/dielectric stack disposed on the substrate and a dielectric layer disposed over the first alternating conductor/dielectric stack. A second alternating conductor/dielectric stack is disposed on the dielectric layer. The NAND memory device includes one or more array common source contacts extending orthogonally with respect to the surface of the substrate through the first layer stack and the second layer stack, wherein at least one of the one or more array common source contacts includes a first conductive contact and a second conductive contact that is disposed over and electrically connected with the first conductive contact.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: February 11, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jun Liu, Zongliang Huo
  • Patent number: 10541254
    Abstract: A thin film transistor substrate according to an embodiment comprises: a support substrate; a bonding layer disposed on the support substrate; a thin film transistor disposed on the bonding layer, wherein the thin film transistor includes a channel layer containing a nitride-based semiconductor layer, a source electrode electrically connected to a first region of the channel layer, a drain electrode electrically connected to a second region of the channel layer, a gate electrode disposed below the channel layer, and a depletion forming layer disposed between the channel layer and the gate electrode; and a pixel electrode disposed on the thin film transistor and electrically connected to the drain electrode of the thin film transistor. The thin film transistor substrate according to the embodiment, and a display panel and a display device including the same have an advantage of implementing high resolution and reproducing a soft moving image by providing a high carrier mobility.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: January 21, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Sang Youl Lee, Chung Song Kim, Ji Hyung Moon, Sun Woo Park, June O Song
  • Patent number: 10541375
    Abstract: A display device with a narrow bezel is provided. The display device includes a pixel circuit and a driver circuit which are provided on the same plane. The driver circuit includes a selection circuit and a buffer circuit. The selection circuit includes a first transistor. The buffer circuit includes a second transistor. The first transistor has a region overlapping with the second transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. One of a source and a drain of the second transistor is electrically connected to the pixel circuit.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: January 21, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hideaki Shishido, Naoto Kusumoto
  • Patent number: 10539844
    Abstract: Discussed are a liquid crystal display (LCD) device and a method of manufacturing the LCD device. The LCD device can include a plurality of pixel areas defined by intersections of a plurality of gate lines and a plurality of data lines, a gate disposed in each of the plurality of pixel areas, a gate insulator disposed to cover the gate, an active layer disposed on only the gate with the gate insulator therebetween, a thin film transistor (TFT) configured to include a source, which is disposed at a first side of the active layer, and a drain disposed at a second side of the active layer, a pixel electrode connected to the drain of the TFT and configured to supply a data voltage to a corresponding pixel area, a common electrode configured to supply a common voltage to the corresponding pixel area, and a lightly doped drain (LDD) disposed between the active layer and the source and between the active layer and the drain. At least a portion of the LDD can be disposed on the gate.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: January 21, 2020
    Assignee: LG DISPLAY CO., LTD.
    Inventors: Kum Mi Oh, In Sang Jung, Sung Hoon Kim
  • Patent number: 10522781
    Abstract: An electroluminescence device and a display device including an electroluminescence device are provided. The electroluminescence device includes an anode including silver, wherein at least a portion of the anode substantially extends in a horizontal direction; a first layer provided over the anode; an organic layer including a luminescent layer; a cathode provided over the organic layer; and an insulating layer provided over an end portion of the anode and an end portion of the first layer, wherein at least a portion of the cathode substantially extends in the horizontal direction in a light emission region, wherein a surface of the insulating layer has a curved portion, and wherein at least a portion of the cathode within a region of the insulating layer above the curved portion extends along a first angled upward direction between the horizontal direction and the thickness direction of the anode.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: December 31, 2019
    Assignee: Sony Corporation
    Inventors: Koji Hanawa, Jiro Yamada, Takashi Hirano
  • Patent number: 10504939
    Abstract: This disclosure relates generally to the three-dimensional (3D) integrated thin-film transistors (TFTs) with silicon and metal-oxide (MO) semiconductors as the active layers. In one or more embodiments, an apparatus is provided that comprises a first transistor comprising a silicon active layer, and a second transistor comprising a metal oxide active layer. The second transistor is vertically stacked on the first transistor, and the first transistor and the second transistor share a gate electrode formed between the silicon active layer and the metal oxide active layer. With these embodiments, the gate electrode corresponds to a top gate of the first transistor and a bottom gate of the second transistor.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: December 10, 2019
    Assignee: The Hong Kong University of Science and Technology
    Inventors: Lei Lu, Wei Zhou, Man Wong, Hoi Sing Kwok
  • Patent number: 10504573
    Abstract: A circuit comprises an array of programmable memory elements fabricated on a substrate, each memory element having one or more processable regions which, when processed by an external process in which a material is applied to at least partially cover one or more of the regions, are configured to program that memory element to one of multiple states; a first set of control lines connected to the array of memory elements, by which the contents of each individual memory element are capable of being accessed by control signals applied to a respective combination of at least two control lines in the first set of control lines; and an array of second circuit elements, different to the memory elements, each connected to a control line of the first set of control lines and to another control line of a second set of control lines, different to the first set of control lines, so as to provide access to second circuit elements in the array.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: December 10, 2019
    Assignee: ARM Limited
    Inventors: James Edward Myers, David William Howard, John Philip Biggs
  • Patent number: 10504916
    Abstract: A three-dimensional memory device and method of manufacturing the same, an isolation structure is embedded between the common source region and the substrate thereunder, which can inhibit the undesired diffusion of impurities during the implantation of the common source region, avoiding operation failure due to excessive diffusion of impurities. In programming and reading states of the three-dimensional memory device, electrons flow from the common source region to bit line; while in erase states, holes are injected from the substrate. Due to the isolation structure, the three-dimensional memory device achieves spatial separation of electrons from holes required for programming/erasing, improving the erasing efficiency and the integration as well.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: December 10, 2019
    Assignee: INSTITUTE OF MICROELECTRONICS, CHINESE ACADEMY OF SCIENCES
    Inventors: Zongliang Huo, Tianchun Ye
  • Patent number: 10490760
    Abstract: The present disclosure provides a thin-film transistor having a plurality of carbon nanotubes in its active layer, its manufacturing method, and an array substrate. The manufacturing method as such comprises: forming an insulating layer to at least substantially cover a channel region of the active layer between a source electrode and a drain electrode of the thin-film transistor, wherein the insulating layer is configured to substantially insulate from an environment, and have substantially little influence on, the plurality of carbon nanotubes in the active layer.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: November 26, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., PEKING UNIVERSITY
    Inventors: Xuelei Liang, Guanbao Hui, Jiye Xia, Fangzhen Zhang, Boyuan Tian, Qiuping Yan, Lianmao Peng
  • Patent number: 10490669
    Abstract: The present disclosure discloses a TFT, a manufacturing method, an array substrate, a display panel, and a device. The TFT includes a hydrogen-containing buffer layer located on a substrate; an oxide semiconductor layer located on the buffer layer, wherein the oxide semiconductor layer includes a conductor region and a semiconductor region; a source or drain located on the conductor region, and electrically connected to the conductor region; and a gate structure located on the semiconductor region.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: November 26, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yuankui Ding, Ce Zhao, Guangcai Yuan, Yingbin Hu, Leilei Cheng, Jun Cheng, Bin Zhou
  • Patent number: 10461142
    Abstract: The present inventive concept relates to a display device. A display device according to an exemplary embodiment of the present inventive concept include: a base layer including a plurality of islands in which a pixel is disposed, a plurality of bridges disposed around each of the plurality of islands, a plurality of first wires disposed in a bridge of the plurality of bridges connected to the pixel is disposed; an inorganic insulating layer disposed on the base layer and having an opening exposing a portion of the bridge; and an organic material layer covering the opening, wherein adjacent islands of the plurality of islands are connected to each other through at least the bridge of the plurality of bridges, and the plurality of first wires are disposed on the organic material layer.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: October 29, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jong Ho Hong, Gun Mo Kim, Jae Min Shin, Hye Jin Joo, Min Woo Kim, Seung Bae Kang
  • Patent number: 10459264
    Abstract: According to one embodiment, a display device includes a first substrate including a first area and a second area, the first area including a display area where pixels are arranged, and the second area being adjacent to the first area and where wirings are arranged, wherein the wirings are covered with a protection layer, the second area includes a peripheral area and a central area in an arrangement direction of the wirings, and a thickness of at least one of the first substrate and the protection layer varies between the peripheral area and the central area.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: October 29, 2019
    Assignee: Japan Display Inc.
    Inventors: Yasushi Tomioka, Hajime Yamaguchi
  • Patent number: 10446657
    Abstract: A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: October 15, 2019
    Assignee: ROHM CO., LTD.
    Inventors: Yuki Nakano, Ryota Nakamura, Katsuhisa Nagao
  • Patent number: 10446769
    Abstract: A display device includes: a flexible substrate including a bending area bent in one direction; an insulating layer on the flexible substrate and comprising a plurality of opening patterns spaced apart from each other at the bending area; and a wavy line extending through the plurality of opening patterns.
    Type: Grant
    Filed: September 9, 2015
    Date of Patent: October 15, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tae Woong Kim, Hyun Woo Koo, Ki Hyun Kim, Young Gug Seol
  • Patent number: 10446545
    Abstract: A bi-directional semiconductor switching device includes first and second vertical field effect transistors (FETs) formed in tandem from a semiconductor substrate. A source for the first FET is on a first side of the substrate and a source for the second FET is on a second side of the substrate opposite the first side. Gates for both the first and second FETs are disposed in tandem in a common set of trenches formed a drift region of the semiconductor substrate that is sandwiched between the sources for the first and second FETs. The drift layer acts as a common drain for both the first FET and second FET.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 15, 2019
    Assignee: ALPHA AND OMEGA SEMICONDUCTOR INCORPORATED
    Inventor: Sik Lui
  • Patent number: 10438970
    Abstract: According to an embodiment, a semiconductor memory device comprises control gate electrodes and a semiconductor layer. The control gate electrodes are stacked above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate. The semiconductor memory device further comprises first and second control gate electrodes and third and fourth control gate electrodes stacked sequentially above the substrate and first through fourth via contacts connected to these first through fourth control gate electrodes. The third and fourth control gate electrodes face the first and second control gate electrodes. Positions of the first and second via contacts are far from each other. Positions of the third and fourth via contacts are close to each other.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: October 8, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Sonehara, Masaru Kito
  • Patent number: 10424672
    Abstract: An oxide semiconductor transistor according to an exemplary embodiment of the present invention includes: a substrate; a first gate electrode disposed on the substrate; a gate insulating layer disposed on the substrate and the first gate electrode; an oxide semiconductor layer disposed on the gate insulating layer; an etch stopper layer disposed on the oxide semiconductor layer; and a source electrode and a drain electrode disposed on the oxide semiconductor layer and the etch stopper layer and spaced apart from each other.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: September 24, 2019
    Assignee: SILICON DISPLAY TECHNOLOGY
    Inventors: Suhui Lee, Sung-ryong Moon, Jaemin Kim
  • Patent number: 10424670
    Abstract: A display panel with reduced power consumption is described. An example of the display panel includes an array of light emitting elements that are controllable to form an image, and a Thin-Film-Transistor (TFT) backplane comprising circuitry to drive the array of light emitting elements. The TFT backplane includes a plurality of field effect transistors (FETs). Each FET includes a source electrode, a drain electrode, a channel layer contacting the source electrode and the drain electrode, and a gate electrode adjacent to the channel layer and separated from the channel layer by an insulator. The channel layer includes a layer of metal phosphide.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Khaled Ahmed, Dong Yeung Kwak, Ramon C. Cancel Olmo
  • Patent number: 10418475
    Abstract: A semiconductor structure, device, or vertical field effect transistor is comprised of a drain, a drift layer disposed in a first direction relative to the drain and in electronic communication with the drain, a barrier layer disposed in the first direction relative to the drift layer and in electronic communication with the drain, the barrier layer comprising a current blocking layer and an aperture region, a two-dimensional hole gas-containing layer disposed in the first direction relative to the barrier layer, a gate electrode oriented to alter an energy level of the aperture region when a gate voltage is applied to the gate electrode, and a source in ohmic contact with the two-dimensional hole gas-containing layer. At least one of an additional layer, the drain, the drift region, the current blocking layer, the two-dimensional hole gas-containing layer, and the aperture region comprises diamond.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: September 17, 2019
    Assignees: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY, THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Srabanti Chowdhury, Maitreya Dutta, Robert Nemanich, Franz Koeck
  • Patent number: 10403638
    Abstract: A vertical memory device includes a first structure having a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate, the lower semiconductor pattern structure including a first undoped semiconductor pattern, a doped semiconductor pattern, and a second undoped semiconductor pattern sequentially stacked, and a lower surface of the doped semiconductor pattern being lower than the upper surface of the substrate, and an upper semiconductor pattern extending in the first direction on the lower semiconductor pattern structure, and a plurality of gate electrodes surrounding a sidewall of the first structure, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joon-Suk Lee, Hong-Suk Kim, Jae-Young Ahn, Han-Jin Lim
  • Patent number: 10360834
    Abstract: A display substrate includes a first substrate having a display area and a non-display area, a plurality of pixels at the display area, and a gate driving circuit at the non-display area and including an output transistor including a channel region, an insulation layer covering the output transistor, and a capacitor on the insulation layer, electrically connected to the output transistor, and including a first capacitor electrode on the insulation layer, overlapping the channel region of the output transistor, and electrically connected to a first electrode of the output transistor, a first protection layer covering the first capacitor electrode, and a second capacitor electrode on the first protection layer, overlapping the channel region of the output transistor, and electrically connected to a gate electrode of the output transistor.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: July 23, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Wonho Kim, Sungman Kim, Hyeonhwan Kim, Seongsu Lim, Sangjin Jeon
  • Patent number: 10355022
    Abstract: A thin film transistor, a method for fabricating the same, an array substrate, and a display device are provided. The method comprises forming an active layer on a substrate, wherein source-and-drain-to-be-formed regions of the active layer are thicker than a semiconductor region between the source-and-drain-to-be-formed regions, and by a patterning process, forming a gate on the active layer, and forming a pattern of source and drain in the source-and-drain-to-be-formed regions of the active layer.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: July 16, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jian Min, Xiaolong Li, Zhengyin Xu, Tao Gao, Dong Li, Shuai Zhang
  • Patent number: 10355034
    Abstract: The present disclosure provides a low-temperature polycrystalline silicon array substrate which includes a substrate, a groove disposed on the substrate, a buffer layer disposed on the substrate, and a polycrystalline silicon active layer disposed on the buffer layer, the groove is located at a channel of a thin film transistor, and the buffer layer covers the groove to form an air layer in the groove. The present disclosure further provides a manufacturing method of a low-temperature polycrystalline silicon array substrate, mainly including: manufacturing a groove at a channel of a thin film transistor on a substrate; depositing a metal sacrificial layer on the substrate, and etching the metal sacrificial layer except the groove through an etching process; sequentially forming a buffer layer and an amorphous silicon layer on the substrate; and removing the metal sacrificial layer in the groove to form an air layer in the groove.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: July 16, 2019
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Tao Wang
  • Patent number: 10340351
    Abstract: A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: July 2, 2019
    Assignee: ROHM CO., LTD
    Inventors: Yuki Nakano, Ryota Nakamura, Katsuhisa Nagao
  • Patent number: 10340387
    Abstract: A manufacturing method of a LTPS-TFT is provided, including: providing a substrate, sequentially forming a buffer layer, a low temperature poly-silicon layer, a source contact region, a drain contact region, a gate insulator layer, a gate layer, and a dielectric layer on the substrate, respectively forming a first and a second contact holes through the dielectric layer and the gate insulator layer by dry etching to expose the source and the drain contact regions; and on the dielectric layer, forming a source electrode to contact the source contact region through the first contact hole and a drain electrode to contact the drain contact region through the second contact hole. A LTPS-TFT and an array substrate are also provided.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: July 2, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Songshan Li
  • Patent number: 10326089
    Abstract: The disclosure relates to a logic circuit. The logic circuit includes a n-type thin film transistor and a p-type thin film transistor. Each thin film transistor includes a substrate; a semiconductor layer including nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer covering the semiconductor layer, wherein the dielectric layer includes a normal dielectric layer and an abnormal dielectric layer stacked on one another, and the abnormal dielectric layer is an oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the abnormal dielectric layer. The n-type thin film transistor and the p-type thin film transistor share the same substrate and the same gate.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: June 18, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Dan Zhao, Yu-Jia Huo, Xiao-Yang Xiao, Ying-Cheng Wang, Tian-Fu Zhang, Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 10325930
    Abstract: A display device is disclosed, which includes: a first substrate; a first transistor disposed over the first substrate, wherein the first transistor includes an oxide semiconductor layer; and a second transistor disposed over the first substrate, wherein the second transistor includes a silicon semiconductor layer, wherein the oxide semiconductor layer includes indium, gallium, and oxygen; and a ratio of an atomic percentage of oxygen to a sum of atomic percentages of indium and gallium in the oxide semiconductor layer is greater than or equal to 1 and less than or equal to 3.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: June 18, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Chandra Lius, Nai-Fang Hsu
  • Patent number: 10326024
    Abstract: A thin film transistor, an array substrate, a manufacturing method and a display device are provided. The thin film transistor includes a substrate and a gate layer, a source layer and a drain layer disposed on the substrate. The source layer and the drain layer are disposed in different layers and the drain layer and the gate layer are disposed in same and one layer.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: June 18, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Qingchao Meng, Qiangqiang Luo
  • Patent number: 10326088
    Abstract: An organic thin film transistor includes a substrate, a hydrophobic layer, an oxide layer, a hydrophilic layer, a semiconductor layer, and a source/drain layer. The hydrophobic layer covers a surface of the substrate. The oxide layer is located on the hydrophobic layer and has plural segments. The hydrophilic layer is located on the segments of the oxide layer, and the oxide layer is located between the hydrophilic layer and the hydrophobic layer. The semiconductor layer is located on the hydrophilic layer, and the hydrophilic layer is located between the semiconductor layer and the oxide layer. The source/drain layer connects across the semiconductor layer on the segments of the oxide layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: June 18, 2019
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Chun-Chih Chen, Hung-Chuan Liu, Zong-Xuan Li, Wei-Tsung Chen
  • Patent number: 10319824
    Abstract: A MOS gate is provided on a front surface side of a silicon carbide substrate. The silicon carbide substrate includes silicon carbide layers sequentially formed on an n+-type starting substrate by epitaxial growth. Of the silicon carbide layers, a p+-type silicon carbide layer is a p+-type high-concentration base region and is separated into plural regions by a trench. A p-type silicon carbide layer among the silicon carbide layers covers the p+-type silicon carbide layer and is embedded in the trench. A p-type silicon carbide layer among the silicon carbide layers is a p-type base region. From a substrate front surface, a gate trench penetrates the p-type base region in the trench and the n+-type source region to reach an n?-type drift region. Between the p+-type high-concentration base region and a gate insulating film at a sidewall of the gate trench, the p-type base region is embedded in the trench.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: June 11, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Akimasa Kinoshita, Yasuhiko Oonishi