Field Effect Device In Non-single Crystal, Or Recrystallized, Semiconductor Material Patents (Class 257/66)
  • Patent number: 10418475
    Abstract: A semiconductor structure, device, or vertical field effect transistor is comprised of a drain, a drift layer disposed in a first direction relative to the drain and in electronic communication with the drain, a barrier layer disposed in the first direction relative to the drift layer and in electronic communication with the drain, the barrier layer comprising a current blocking layer and an aperture region, a two-dimensional hole gas-containing layer disposed in the first direction relative to the barrier layer, a gate electrode oriented to alter an energy level of the aperture region when a gate voltage is applied to the gate electrode, and a source in ohmic contact with the two-dimensional hole gas-containing layer. At least one of an additional layer, the drain, the drift region, the current blocking layer, the two-dimensional hole gas-containing layer, and the aperture region comprises diamond.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: September 17, 2019
    Assignees: ARIZONA BOARD OF REGENTS ON BEHALF OF ARIZONA STATE UNIVERSITY, THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Srabanti Chowdhury, Maitreya Dutta, Robert Nemanich, Franz Koeck
  • Patent number: 10403638
    Abstract: A vertical memory device includes a first structure having a lower semiconductor pattern structure filling a recess on a substrate and protruding from an upper surface of the substrate in a first direction substantially perpendicular to the upper surface of the substrate, the lower semiconductor pattern structure including a first undoped semiconductor pattern, a doped semiconductor pattern, and a second undoped semiconductor pattern sequentially stacked, and a lower surface of the doped semiconductor pattern being lower than the upper surface of the substrate, and an upper semiconductor pattern extending in the first direction on the lower semiconductor pattern structure, and a plurality of gate electrodes surrounding a sidewall of the first structure, the plurality of gate electrodes being at a plurality of levels, respectively, so as to be spaced apart from each other in the first direction.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: September 3, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Joon-Suk Lee, Hong-Suk Kim, Jae-Young Ahn, Han-Jin Lim
  • Patent number: 10360834
    Abstract: A display substrate includes a first substrate having a display area and a non-display area, a plurality of pixels at the display area, and a gate driving circuit at the non-display area and including an output transistor including a channel region, an insulation layer covering the output transistor, and a capacitor on the insulation layer, electrically connected to the output transistor, and including a first capacitor electrode on the insulation layer, overlapping the channel region of the output transistor, and electrically connected to a first electrode of the output transistor, a first protection layer covering the first capacitor electrode, and a second capacitor electrode on the first protection layer, overlapping the channel region of the output transistor, and electrically connected to a gate electrode of the output transistor.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: July 23, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Wonho Kim, Sungman Kim, Hyeonhwan Kim, Seongsu Lim, Sangjin Jeon
  • Patent number: 10355022
    Abstract: A thin film transistor, a method for fabricating the same, an array substrate, and a display device are provided. The method comprises forming an active layer on a substrate, wherein source-and-drain-to-be-formed regions of the active layer are thicker than a semiconductor region between the source-and-drain-to-be-formed regions, and by a patterning process, forming a gate on the active layer, and forming a pattern of source and drain in the source-and-drain-to-be-formed regions of the active layer.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: July 16, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Jian Min, Xiaolong Li, Zhengyin Xu, Tao Gao, Dong Li, Shuai Zhang
  • Patent number: 10355034
    Abstract: The present disclosure provides a low-temperature polycrystalline silicon array substrate which includes a substrate, a groove disposed on the substrate, a buffer layer disposed on the substrate, and a polycrystalline silicon active layer disposed on the buffer layer, the groove is located at a channel of a thin film transistor, and the buffer layer covers the groove to form an air layer in the groove. The present disclosure further provides a manufacturing method of a low-temperature polycrystalline silicon array substrate, mainly including: manufacturing a groove at a channel of a thin film transistor on a substrate; depositing a metal sacrificial layer on the substrate, and etching the metal sacrificial layer except the groove through an etching process; sequentially forming a buffer layer and an amorphous silicon layer on the substrate; and removing the metal sacrificial layer in the groove to form an air layer in the groove.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: July 16, 2019
    Assignee: Wuhan China Star Optoelectronics Technology Co., Ltd.
    Inventor: Tao Wang
  • Patent number: 10340351
    Abstract: A semiconductor device includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: July 2, 2019
    Assignee: ROHM CO., LTD
    Inventors: Yuki Nakano, Ryota Nakamura, Katsuhisa Nagao
  • Patent number: 10340387
    Abstract: A manufacturing method of a LTPS-TFT is provided, including: providing a substrate, sequentially forming a buffer layer, a low temperature poly-silicon layer, a source contact region, a drain contact region, a gate insulator layer, a gate layer, and a dielectric layer on the substrate, respectively forming a first and a second contact holes through the dielectric layer and the gate insulator layer by dry etching to expose the source and the drain contact regions; and on the dielectric layer, forming a source electrode to contact the source contact region through the first contact hole and a drain electrode to contact the drain contact region through the second contact hole. A LTPS-TFT and an array substrate are also provided.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: July 2, 2019
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Songshan Li
  • Patent number: 10326088
    Abstract: An organic thin film transistor includes a substrate, a hydrophobic layer, an oxide layer, a hydrophilic layer, a semiconductor layer, and a source/drain layer. The hydrophobic layer covers a surface of the substrate. The oxide layer is located on the hydrophobic layer and has plural segments. The hydrophilic layer is located on the segments of the oxide layer, and the oxide layer is located between the hydrophilic layer and the hydrophobic layer. The semiconductor layer is located on the hydrophilic layer, and the hydrophilic layer is located between the semiconductor layer and the oxide layer. The source/drain layer connects across the semiconductor layer on the segments of the oxide layer.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: June 18, 2019
    Assignee: E Ink Holdings Inc.
    Inventors: Hsiao-Wen Zan, Chuang-Chuang Tsai, Chun-Chih Chen, Hung-Chuan Liu, Zong-Xuan Li, Wei-Tsung Chen
  • Patent number: 10326089
    Abstract: The disclosure relates to a logic circuit. The logic circuit includes a n-type thin film transistor and a p-type thin film transistor. Each thin film transistor includes a substrate; a semiconductor layer including nano-scaled semiconductor materials; a source and a drain, wherein the source and the drain are spaced apart from each other, and electrically connected to the semiconductor layer; a dielectric layer covering the semiconductor layer, wherein the dielectric layer includes a normal dielectric layer and an abnormal dielectric layer stacked on one another, and the abnormal dielectric layer is an oxide dielectric layer grown by magnetron sputtering; and a gate in direct contact with the abnormal dielectric layer. The n-type thin film transistor and the p-type thin film transistor share the same substrate and the same gate.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: June 18, 2019
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yu-Dan Zhao, Yu-Jia Huo, Xiao-Yang Xiao, Ying-Cheng Wang, Tian-Fu Zhang, Yuan-Hao Jin, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 10326024
    Abstract: A thin film transistor, an array substrate, a manufacturing method and a display device are provided. The thin film transistor includes a substrate and a gate layer, a source layer and a drain layer disposed on the substrate. The source layer and the drain layer are disposed in different layers and the drain layer and the gate layer are disposed in same and one layer.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: June 18, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Qingchao Meng, Qiangqiang Luo
  • Patent number: 10325930
    Abstract: A display device is disclosed, which includes: a first substrate; a first transistor disposed over the first substrate, wherein the first transistor includes an oxide semiconductor layer; and a second transistor disposed over the first substrate, wherein the second transistor includes a silicon semiconductor layer, wherein the oxide semiconductor layer includes indium, gallium, and oxygen; and a ratio of an atomic percentage of oxygen to a sum of atomic percentages of indium and gallium in the oxide semiconductor layer is greater than or equal to 1 and less than or equal to 3.
    Type: Grant
    Filed: April 13, 2017
    Date of Patent: June 18, 2019
    Assignee: INNOLUX CORPORATION
    Inventors: Chandra Lius, Nai-Fang Hsu
  • Patent number: 10319824
    Abstract: A MOS gate is provided on a front surface side of a silicon carbide substrate. The silicon carbide substrate includes silicon carbide layers sequentially formed on an n+-type starting substrate by epitaxial growth. Of the silicon carbide layers, a p+-type silicon carbide layer is a p+-type high-concentration base region and is separated into plural regions by a trench. A p-type silicon carbide layer among the silicon carbide layers covers the p+-type silicon carbide layer and is embedded in the trench. A p-type silicon carbide layer among the silicon carbide layers is a p-type base region. From a substrate front surface, a gate trench penetrates the p-type base region in the trench and the n+-type source region to reach an n?-type drift region. Between the p+-type high-concentration base region and a gate insulating film at a sidewall of the gate trench, the p-type base region is embedded in the trench.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: June 11, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Makoto Utsumi, Akimasa Kinoshita, Yasuhiko Oonishi
  • Patent number: 10312311
    Abstract: The disclosed subject matter provides a thin film transistor and a fabricating method thereof. The thin film transistor includes a substrate, a source electrode and a drain electrode on the substrate, an active layer on the source and drain electrodes, a gate insulating layer on the active layer, and a gate electrode on the gate insulating layer. The active layer extends from the source electrode towards the drain electrode along a non-linear path.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: June 4, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD
    Inventors: Zheng Liu, Xiaolong Li, Lujiang Huang Fu
  • Patent number: 10297694
    Abstract: A semiconductor device includes a first thin film transistor (101) on a substrate (10), the first thin film transistor including: a sub-gate electrode (12); a first insulating layer (14) covering the sub-gate electrode; a main gate electrode (16) formed on the first insulating layer; a second insulating layer (18) covering the main gate electrode; an oxide semiconductor layer (20) having a layered structure of a first layer (20A) and a second layer (20B), the second layer having a larger band gap than the first layer; a first source electrode (22); and a first drain electrode (24), wherein as seen from a direction normal to the substrate, the oxide semiconductor layer (20) includes: a gate opposing region (20g) that overlaps the main gate electrode; a source contact region that is in contact with the first source electrode (22); a drain contact region that is in contact with the first drain electrode; and an offset region (30s, 30d) that is provided at least one of between the gate opposing region and the sou
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: May 21, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Kazuatsu Ito
  • Patent number: 10290822
    Abstract: A thin film transistor and its manufacturing method, an array substrate and a display device are disclosed, the thin film transistor is of a gate bottom contact type, and includes a gate electrode (3) and a gate insulation layer (2), the gate insulation layer (2) is provided with a recess (4) at a position corresponding to the gate electrode (3). With the thin film transistor, the problem of wire breakage in the active layer at the channel between the source/drain electrodes can be avoided, the performance and stability of the thin film transistor is improved, and the production cost is lowered down.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: May 14, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Honhang Fong, Yingtao Xie, Shihong Ouyang, Shucheng Cai, Qiang Shi, Ze Liu
  • Patent number: 10276662
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate stack and a second gate stack over a substrate. Each of them has gate spacers disposed along its respective sidewalls. The method also includes forming a source/drain (S/D) feature disposed between the first and second gate stacks. The gate spacers and a top surface of the S/D feature define a space. The method also includes forming a first dielectric layer over the S/D feature in the space, forming a capping layer along the gate spacers in the space, forming a second dielectric layer over the first dielectric layer in the space and forming a contact trench extending through the second dielectric layer, the first dielectric layer and the capping layer to expose the top surface of the S/D feature.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chih-Han Lin
  • Patent number: 10276730
    Abstract: A stacked Schottky-diode having a stack with a top side and a bottom side. The stack has at least three semiconductor layers, and a first connection contact layer materially connected to the bottom side of the stack. A second connection contact layer is connected to the top side of the stack, wherein the second connection contact layer forms a Schottky contact. The second connection contact layer is disposed in a partial region of the top side and the second connection contact layer is bounded by edges. The first semiconductor layer, formed as an n+ layer, is placed on the bottom side of the stack and the first semiconductor layer. A second semiconductor layer, formed as an n? layer, is placed on the first semiconductor layer. A third semiconductor layer formed as a p? layer is placed on the second semiconductor layer.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: April 30, 2019
    Assignee: 3-5 Power Electronics GmbH
    Inventor: Volker Dudek
  • Patent number: 10269913
    Abstract: A thin film transistor includes a gate electrode on a semiconductor layer, a first insulation layer between the semiconductor layer and the gate electrode, a second insulation layer on the gate electrode, and a source and drain electrode on the semiconductor layer. The gate electrode includes a first part and a second part adjacent to the first part. A width of the second part is greater than a width of the first part. The source electrode and the drain electrode are on the semiconductor layer and arranged such that the first part of the gate electrode is between the source electrode and the drain electrode. The source electrode and the drain electrode are electrically connected to the semiconductor layer through the first insulation layer and the second insulation layer, respectively. A space between the source electrode and the drain electrode is greater than the width of the first part.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: April 23, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Suk Gyu Hahm, Jeong Il Park, Youngjun Yun, Joo Young Kim, Yong Uk Lee
  • Patent number: 10269939
    Abstract: A method includes forming a dummy gate stack on a top surface and a sidewall of a middle portion of a semiconductor fin, and forming a spacer layer. The spacer layer includes a first portion on a sidewall of the dummy gate stack, and a second portion on a top surface and a sidewall of a portion of the semiconductor fin. The method further includes performing an implantation on the spacer layer. After the implantation, an anneal is performed. After the anneal, the second portion of the spacer layer is etched, wherein the first portion of the spacer layer remains after the etching. A source/drain region is formed on a side of the semiconductor fin.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi On Chui, Yee-Chia Yeo
  • Patent number: 10236393
    Abstract: A TFT, a method for driving TFT, an array substrate, and a display device are disclosed. The TFT comprises a first gate on a base plate, an active layer insulated from the first gate, a source and a drain, and a second gate arranged on a side of the active layer away from the first gate and insulated from the active layer. The second gate comprises at least two sub-gates. An orthographic projection of each sub-gate overlaps that of a channel region. The first gate is capable of controlling the complete channel region, and the second gate is capable of controlling a portion of the channel region. The first and second gates maintain an energy band of the channel region at a relatively stable state, and thus maintain stable switching characteristics. This increases reliability and electrical performance of TFT.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: March 19, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Hehe Hu
  • Patent number: 10224548
    Abstract: An object is to improve the characteristics of a power storage device such as a charging and discharging rate or a charge and discharge capacity. The grain size of particles of a positive electrode active material is nano-sized so that a surface area per unit mass of the active material is increased. Specifically, the grain size is set to greater than or equal to 10 nm and less than or equal to 100 nm, preferably greater than or equal to 20 nm and less than or equal to 60 nm. Alternatively, the surface area per unit mass is set to 10 m2/g or more, preferably 20 m2/g or more. Further, the crystallinity of the active material is increased by setting an XRD half width to greater than or equal to 0.12° and less than 0.17°, preferably greater than or equal to 0.13° and less than 0.16°.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: March 5, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takahiro Kawakami, Masaki Yamakaji
  • Patent number: 10217775
    Abstract: A display substrate, a manufacturing method thereof, and a display device are disclosed. The display substrate includes a display region and a peripheral region, a display device including the display substrate further includes a gate driving circuit, the gate driving circuit includes a capacitor (C), the capacitor (C) includes a first electrode and a second electrode with an electrical insulation layer provided therebetween. The first electrode and the second electrode are remaining portions of films for forming conductive layers in the display region left in the peripheral region, and the electrical insulation layer is a remaining portion of a film for forming an insulation layer in the display region left in the peripheral region.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: February 26, 2019
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Shijun Wang, Wenbo Jiang, Zhenhua Lv, Zhiying Bao
  • Patent number: 10211209
    Abstract: Methods of operating semiconductor memory devices with floating body transistors, using a silicon controlled rectifier principle are provided, as are semiconductor memory devices for performing such operations.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: February 19, 2019
    Assignee: Zeno Semiconductor, Inc.
    Inventor: Yuniarto Widjaja
  • Patent number: 10204779
    Abstract: The present invention provides a thin film transistor and a manufacturing method thereof, an array substrate comprising the thin film transistor and a manufacturing method thereof, and a display apparatus comprising the array substrate. The manufacturing method of the thin film transistor comprises steps of forming a gate, a gate insulating layer, a semiconductor active layer, a source and a drain on a substrate, wherein the steps of forming the gate insulating layer and the semiconductor active layer comprise: preparing an insulating film, the insulating film comprises metal oxide insulating material; performing ion implantation on a predefined region of the insulating film, so that the metal oxide insulating material of partial-thickness of the insulating film in the predefined region is transformed into metal oxide semiconductor material to form the semiconductor active layer, and the rest of the insulating film forms the gate insulating layer.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: February 12, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Liu, Chunsheng Jiang
  • Patent number: 10199001
    Abstract: An increase in power consumption is suppressed even in a case of applying a precharge signal to all data lines at the same time. A voltage output selection circuit that is connected to a data line drive circuit in an input stage and is connected to data lines in an output stage is provided. The voltage output selection circuit selects connection and non-connection between the data lines and the data line drive circuit when a precharge voltage is applied. A control circuit controls the voltage output selection circuit such that connection between the data lines and the data line drive circuit is selected in a first region in which an image is displayed, and non-connection between the data lines and the data line drive circuit is selected in a second region covered with a light shielding layer.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: February 5, 2019
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Shinta Enami
  • Patent number: 10199481
    Abstract: A method for manufacturing a semiconductor device includes carrying out a first heat treatment accompanied by nitration on a first insulating film and a silicon carbide substrate in a first gas atmosphere, after the carrying out of the first heat treatment and after a temperature of the silicon carbide substrate has become 700° C. or less, removing the silicon carbide substrate from a processing apparatus and exposing the silicon carbide substrate to air in an atmosphere outside of the processing apparatus, and after the exposing of the silicon carbide substrate to air in the atmosphere, carrying out a second heat treatment on the first insulating film and the silicon carbide substrate in a second gas atmosphere which is an inert gas.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: February 5, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Masaki Hama, Yasuaki Kagotoshi
  • Patent number: 10192747
    Abstract: A semiconductor device having a first gate stack on a substrate is disclosed. The first gate stack may include a first gate conductor over a first gate dielectric structure. A dielectric structure can be formed over the first gate stack and the substrate. The dielectric structure layer can include four or more layers of two or more dielectric films disposed in an alternating manner. The dielectric structure can be selectively etched to form an inter-gate dielectric structure. A second gate conductor can be formed over a second gate dielectric structure, adjacent to the integrate dielectric structure. A dielectric layer can be formed over the substrate, the first and second gate conductors, and the inter-gate dielectric structure. The first gate conductor may be used to make a memory gate and the second gate conductor can be used to make a select gate of a split-gate memory cell.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: January 29, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Chun Chen, Shenqing Fang
  • Patent number: 10192935
    Abstract: A display device includes a substrate, a light shielding layer on the substrate, first to fourth subpixels sequentially arranged on the substrate including the light shielding layer in a horizontal direction, a first power line disposed on one side of the first subpixel and shared by the first and second subpixels, a sensing line disposed between the second subpixel and the third subpixel and shared by the first to fourth subpixels, a second power line disposed on one side of the fourth subpixel and shared by the third and fourth subpixels, first and second data lines between the first and second subpixels and third and fourth data lines between the third and fourth subpixels; and a scan line extended on the first to fourth subpixels in the horizontal direction.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: January 29, 2019
    Assignee: LG Display Co., Ltd.
    Inventors: Jongsik Shim, Byeonguk Gang, Hyunjin Kim, Seonghwan Hwang
  • Patent number: 10192889
    Abstract: A display device includes a first substrate including a display area and a non-display area. A gate line and a gate electrode are in the display area. A data line is connected to the gate line. A gate insulating layer is on the gate line and the gate electrode. A semiconductor layer is on the gate insulating layer. A drain electrode and a source electrode are on the semiconductor layer. A first passivation layer is on the drain electrode and the source electrode. A color filter is on the first passivation layer. A common electrode is on the first passivation layer. A second passivation layer is on the common electrode. A pixel electrode is on the second passivation layer. The gate insulating layer has substantially a same shape as a shape of the gate electrode. The gate insulating layer has a width wider than a width of the gate electrode.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: January 29, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jisun Kim, Chongchul Chai
  • Patent number: 10186610
    Abstract: On a front surface of a semiconductor base, a first n?-type drift region, a second n-type drift region, and a third n+-type drift region are provided. In the front surface of the semiconductor base, a gate trench is provided penetrating the n+-type source region and the p-type base region, and reaching the second n-type drift region. Between adjacent gate trenches, a contact trench is provided that penetrates the n+-type source region, the p-type base region, and the second and third n-type drift regions, and that reaches the p-type semiconductor region. A source electrode embedded in the contact trench is in contact with the p-type semiconductor region at the bottom and the corners of the contact trench and forms a Schottky junction with the third n+-type drift region and the second n-type drift region at a side wall of the contact trench.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: January 22, 2019
    Assignees: FUJI ELECTRIC CO., LTD., NATIONAL INSTITUTE ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY
    Inventors: Yusuke Kobayashi, Manabu Takei, Shinsuke Harada
  • Patent number: 10186505
    Abstract: An electrostatic discharge (ESD) protection device includes a substrate including a plurality of fins extending in a first direction, with an insulation layer on the fins. A gate electrode extending in a second direction, an electrode pattern of a capacitor, and a resistor are on the insulation layer. A drain is on a first side of the gate electrode, and a source is on a second side of the gate electrode. A connection structure electrically connects the electrode pattern, the gate electrode and the resistor. The electrode pattern is on the first side or the second side of the gate electrode, and the resistor is on the other of the first side or the second side. At least a portion of the resistor extends in the second direction.
    Type: Grant
    Filed: May 24, 2017
    Date of Patent: January 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae-Hyun Yoo, Jin-Tae Kim, Jong-Sung Jeon
  • Patent number: 10181477
    Abstract: According to the embodiment, a semiconductor device includes: a substrate; a stacked body provided on the substrate and including a plurality of electrode layers stacked with an insulator interposed; a semiconductor pillar provided on the substrate and in the stacked body; a semiconductor body provided in the stacked body; and an insulating film including a charge storage film provided between the plurality of electrode layers and the semiconductor body, and extending in the stacking direction. The semiconductor body includes a first portion and a second portion. The first portion is surrounded with the plurality of electrode layers and extends in a stacking direction of the stacked body. The second portion is in contact with an upper surface of the semiconductor pillar.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: January 15, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hirokazu Ishigaki, Tatsuya Okamoto, Masao Shingu
  • Patent number: 10155323
    Abstract: A SiC wafer producing method produces an SiC wafer from a single crystal SiC ingot. The method includes a separation layer forming step of setting a focal point of a pulsed laser beam having a transmission wavelength to single crystal SiC inside the ingot at a predetermined depth from an end surface of the ingot, the predetermined depth corresponding to the thickness of the wafer to be produced, and next applying the pulsed laser beam to the ingot, thereby forming a plurality of modified portions on a c-plane present in the ingot at the predetermined depth and also forming cracks isotropically on the c-plane so as to extend from each modified portion, each modified portion being a region where SiC has been decomposed into Si and C, the modified portions and the cracks constituting a separation layer along which the wafer is to be separated from the ingot.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: December 18, 2018
    Assignee: Disco Corporation
    Inventor: Kazuya Hirata
  • Patent number: 10147774
    Abstract: A method of manufacturing a thin film transistor (TFT) comprises forming a buffer layer, an amorphous silicon layer, and an insulating layer on a substrate; crystallizing the amorphous silicon layer as a polycrystalline silicon layer; forming a semiconductor layer and a gate insulating layer which have a predetermined shape by simultaneously patterning the polycrystalline silicon layer and the insulating layer; forming a gate electrode including a first portion and a second portion by forming and patterning a metal layer on the gate insulating layer. The first portion is formed on the gate insulating layer and overlaps a channel region of a semiconductor layer, and the second portion contacts the semiconductor layer. A source region and a drain region are formed on the semiconductor layer by doping a region of the semiconductor layer. The region excludes the channel region overlapping the gate electrode and constitutes a region which does not overlap the gate electrode.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: December 4, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byoung-Keon Park, Jong-Ryuk Park, Dong-Hyun Lee, Jin-Wook Seo, Ki-Yong Lee
  • Patent number: 10134907
    Abstract: Disclosed is a low temperature polysilicon array substrate and its manufacturing method. The method includes: forming a light-shielding layer, a buffer layer and U-type polysilicon patterns successively on a glass substrate; doping channels of the U-type polysilicon patterns in the active area and then heavily N+ doping these U-type polysilicon patterns; forming a gate insulation layer and etching first via holes; forming a gate line, a source and lightly-doped regions of the N-type double-gate transistor; and heavily P+ doping U-type polysilicon patterns in the non-active area.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: November 20, 2018
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Yuan Guo
  • Patent number: 10134765
    Abstract: A method for manufacturing an oxide semiconductor TFT array substrate is provided, which including: successively depositing an oxide semiconductor active layer and a transparent conductive layer on a base substrate without breaking vacuum; and forming patterns of an active layer and a transparent conductive layer. An oxide semiconductor TFT array substrate is further provided.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: November 20, 2018
    Assignees: BOE Technology Group Co., Ltd., Hefei Xinsheng Optoelectronics Technology Co., Ltd.
    Inventors: Bingkun Yin, Junhao Han
  • Patent number: 10128354
    Abstract: The present disclosure provides a thin film transistor, a method for manufacturing the same, an array substrate and a display device. The method for manufacturing a thin film transistor includes providing a substrate, forming a gate electrode, a gate insulating layer, an amorphous silicon material active layer and a cap layer on the substrate successively, wherein The cap layer is provided with a pattern on a side of the cap layer away from the amorphous silicon material active layer, and the pattern is composed of at least one groove along a length direction of the active layer and at least one groove along a width direction of the active layer, subjecting the amorphous silicon material active layer to laser annealing treatment to transform the amorphous silicon material active layer into a low temperature polycrystalline silicon material active layer, and removing the cap layer.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: November 13, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Zuqiang Wang, Yuqing Yang
  • Patent number: 10128162
    Abstract: A method of manufacturing a semiconductor device, the method may include: forming a SOG film on a wafer, the wafer including a semiconductor substrate and a polyimide film exposed on a surface of the wafer, and the SOG film being formed so as to cover the polyimide film; applying a protection tape on a surface of the SOG film; processing the wafer on which the protection tape is applied; and peeling the protection tape from the wafer.
    Type: Grant
    Filed: September 6, 2017
    Date of Patent: November 13, 2018
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Masaru Okuda
  • Patent number: 10121980
    Abstract: A thin film transistor array panel and a manufacturing method are disclosed herein. The thin film transistor array panel includes a data line, a first block of a source electrode, a third block of a drain electrode, and an electrode layer which are formed by a first metal layer disposed on a baseplate; a second block of the source electrode, a fourth block of the drain electrode are formed by a second metal layer which is disposed on the first metal layer. The first block and the second block overlap to combine integrally. The third block and the fourth block overlap to combine integrally. The present invention can decrease the electrical resistance of each of the source electrode and the drain electrode.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: November 6, 2018
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Hongyuan Xu
  • Patent number: 10115326
    Abstract: A display device according to an exemplary embodiment of the present disclosure includes: a substrate that includes a display area and a peripheral area around the display area; a plurality of data lines on the substrate; and a crack sensing line disposed in the peripheral area and that is connected to a first data line of the plurality of data lines, where the crack sensing line includes a first layer disposed under an insulating layer and a second layer disposed on the insulating layer, the first layer and the second layer each include overlapping parts where the first layer and the second layer overlap via the insulating layer, and a voltage applied to the first layer and a voltage applied to the second layer have different magnitudes.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: October 30, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Min Woo Byun
  • Patent number: 10094867
    Abstract: A method of evaluating a semiconductor device having an insulated gate formed of a metal-oxide film semiconductor. The semiconductor device has a high potential side and a low potential side, and a threshold voltage that is a minimum voltage for forming a conducting path between the high and low potential sides. The method includes determining a variation of the threshold voltage at turn-on of the semiconductor device by continuously applying an alternating current (AC) voltage to the gate of the semiconductor device, a maximum voltage of the AC voltage being equal to or higher than the threshold voltage of the semiconductor device.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: October 9, 2018
    Assignees: FUJI ELECTRIC CO., LTD., National Institute of Advanced Industrial Science and Technology
    Inventors: Mitsuru Sometani, Manabu Takei, Shinsuke Harada
  • Patent number: 10090373
    Abstract: It is an object of the present invention to prevent an influence of voltage drop due to wiring resistance, trouble in writing of a signal into a pixel, and trouble in gray scales, and provide a display device with higher definition, represented by an EL display device and a liquid crystal display device. In the present invention, a wiring including Cu is provided as an electrode or a wiring used for the display device represented by the EL display device and the liquid crystal display device. Besides, sputtering is performed with a mask to form the wiring including Cu. With such structure, it is possible to reduce the voltage drop and a deadened signal.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: October 2, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Mitsuaki Osame
  • Patent number: 10074328
    Abstract: An active matrix substrate includes a display region in which a plurality of pixels are provided and a frame region lying outside the display region. The frame region includes a plurality of peripheral circuit TFTs which are supported by a substrate and which are constituents of a driving circuit. Each of the plurality of peripheral circuit TFTs includes a gate electrode, an oxide semiconductor layer arranged so as to at least partially extend over the gate electrode but to be insulated from the gate electrode, and source and drain electrodes connected with the oxide semiconductor layer.
    Type: Grant
    Filed: April 10, 2017
    Date of Patent: September 11, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Masahiro Tomida, Naoki Ueda
  • Patent number: 10068543
    Abstract: A unit shift register circuit constitutes each stage of a shift register circuit. The unit shift register circuit includes an output transistor (T1) configured to input a prescribed clock signal (CK) to a drain terminal, and output an output signal (OUT) from a source terminal. The unit shift register circuit includes a setting transistor (T2) in which a source terminal is connected to a gate electrode of the output transistor (T1), is configured to input an input signal (S) to the drain terminal, and is configured to input to a gate electrode an input signal (VS) in a case of charging a gate electrode (node (VC)) of the output transistor (T1). The input signal (VS) having a voltage higher than that of the input signal (S).
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: September 4, 2018
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Kaoru Yamamoto, Yasuyuki Ogawa
  • Patent number: 10062784
    Abstract: A method includes forming a metal gate in a first inter-layer dielectric, performing a treatment on the metal gate and the first inter-layer dielectric, selectively growing a hard mask on the metal gate without growing the hard mask from the first inter-layer dielectric, depositing a second inter-layer dielectric over the hard mask and the first inter-layer dielectric, planarizing the second inter-layer dielectric and the hard mask, and forming a gate contact plug penetrating through the hard mask to electrically couple to the metal gate.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: August 28, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Hsuan Lee, Bo-Yu Lai, Sheng-Chen Wang, Sai-Hooi Yeong, Yen-Ming Chen, Chi On Chui
  • Patent number: 10056365
    Abstract: A semiconductor device incudes a cell region and a contact region, the cell region including a functional unit including a gate electrode, a source and a drain electrode, and the contact region including a gate pad. The gate electrode, the gate pad and the source electrode are disposed on a first main surface of a semiconductor substrate, and the drain electrode is disposed on a second main surface of the semiconductor substrate, the second main surface being opposite to the first main surface. A shielding member is disposed between the gate pad and the drain electrode, the shielding member being electrically connected to the source electrode.
    Type: Grant
    Filed: February 23, 2015
    Date of Patent: August 21, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Daniel Kueck, Rudolf Elpelt
  • Patent number: 10048551
    Abstract: A semiconductor device includes a thin-film transistor (101), a terminal portion (102), an interlevel insulating layer (14) including a first insulating layer (12) which contacts with the surface of a drain electrode (11d), and a first transparent conductive layer (15), a first dielectric layer (17) and a second transparent conductive layer (19a) formed on the interlevel insulating layer (14). The terminal portion (102) includes a lower conductive layer (3t), a second semiconductor layer (7t) arranged on a gate insulating layer (5), and lower and upper transparent connecting layers (15t, 19t). The gate insulating layer (5) and the second semiconductor layer (7t) have a contact hole (CH2), and their side surfaces located on a side of the contact hole (CH2) are aligned with each other. The lower transparent connecting layer (15t) contacts with the lower conductive layer (3t) in the contact hole (CH2).
    Type: Grant
    Filed: January 8, 2013
    Date of Patent: August 14, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tetsuo Fujita, Yoshihito Hara, Yukinobu Nakata
  • Patent number: 10049884
    Abstract: A bi-directional bipolar junction transistor (BJT) structure, comprising: a base region of a first conductivity type, wherein said base region constitutes a drift region of said structure; first and second collector/emitter (CE) regions, each of a second conductivity type adjacent opposite ends of said base region; wherein said base region is lightly doped relative to said collector/emitter regions; the structure further comprising: a base connection to said base region, wherein said base connection is within or adjacent to said first collector/emitter region.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: August 14, 2018
    Inventor: John Wood
  • Patent number: 10032799
    Abstract: Provided is a semiconductor device including: a first transistor over a substrate, the first transistor having a gate electrode, an oxide semiconductor film, and a gate insulating film between the gate electrode and the oxide semiconductor film; an insulating film over the first transistor, the insulating film having a first film and a second film over the first film; and a terminal electrically connected to the oxide semiconductor film through an opening portion in the insulating film. The insulating film has a first region in contact with the terminal, and the first region has an oxygen composition larger than that in another region of the insulating film.
    Type: Grant
    Filed: February 9, 2017
    Date of Patent: July 24, 2018
    Assignee: Japan Display Inc.
    Inventor: Hiroki Ohara
  • Patent number: 10020205
    Abstract: A display apparatus includes a pixel having a first area emitting light and a second area transmitting light. A pixel circuit unit is in the first area and includes a thin film transistor. An inorganic insulation layer is in the second area. A first insulation layer covers the pixel circuit unit in the first area, and has an opening exposing the inorganic insulation layer in the second area. A first electrode is on the first insulation layer in the first area. The first electrode is electrically connected to the pixel circuit unit. A second insulation layer covers edges of the first electrode and is outside the opening formed in the first insulation layer. A second electrode is in the first area. An intermediate layer, including an emissive layer, is between the first electrode and the second electrode.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: July 10, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Chungi You, Gwanggeun Lee