Field Effect Device In Non-single Crystal, Or Recrystallized, Semiconductor Material Patents (Class 257/66)
  • Patent number: 11121143
    Abstract: Some embodiments include an integrated assembly having a conductive expanse over conductive nodes. The conductive nodes include a first composition. A bottom surface of the conductive expanse includes a second composition which is different composition than the first composition. A stack is over the conductive expanse. The stack includes alternating first and second levels. Pillar structures extend vertically through the stack. Each of the pillar structures includes a post of conductive material laterally surrounded by an insulative liner. At least one of the posts extends through the conductive expanse to directly contact one of the conductive nodes. Some embodiments include methods of forming integrated assemblies.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: September 14, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shuangqiang Luo, Indra V. Chary, Justin B. Dorhout, Rita J. Klein
  • Patent number: 11114469
    Abstract: The present disclosure is in the field of display technologies, and provides an array substrate including an IGZO film layer, a gate layer, and a gate insulating layer. The gate layer is provided with broken lines at a position thereof overlapping the IGZO film layer to form a first gate line and a second gate line. The gate insulating layer is disposed between the IGZO film layer and the gate layer, and is provided with at least two through holes thereon, in which the first gate line is connected with the IGZO film layer through one of the through holes, and the second gate line is connected with the IGZO film layer through another through hole, thus, connecting the IGZO film layer in series into the gate layer.
    Type: Grant
    Filed: April 28, 2019
    Date of Patent: September 7, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Bin Zhou, Binbin Cao, Liangchen Yan, Dongfang Wang, Ce Zhao, Luke Ding, Jun Liu
  • Patent number: 11101387
    Abstract: A low temperature polysilicon layer, a thin film transistor, and a method for manufacturing same are provided. The low temperature polysilicon layer includes a substrate, at least one buffer layer, and a polysilicon layer. The polysilicon layer is disposed on the at least one buffer layer. The polysilicon layer includes a channel region, two low doped regions disposed on two sides of the channel region, and two high doped regions disposed on an outer side of the low doped regions. Thicknesses of an edge of the channel region and at least one portion of the low doped regions are less than a thickness of another position of the polysilicon layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: August 24, 2021
    Inventors: Lisheng Li, Peng He, Yuan Yan
  • Patent number: 11094822
    Abstract: One illustrative transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall cavities formed in the semiconductor substrate on opposite sides of the gate structure. In this example, each of the first and second overall cavities comprise a substantially vertically oriented upper epitaxial cavity and a lower insulation cavity, wherein the substantially vertically oriented upper epitaxial cavity extends from an upper surface of the semiconductor substrate to the lower insulation cavity. The transistor also includes an insulation material positioned in at least a portion of the lower insulation cavity of each of the first and second overall cavities and epitaxial semiconductor material positioned in at least the substantially vertically oriented upper epitaxial cavity of each of the first and second overall cavities.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: August 17, 2021
    Assignee: GLOBALFOUNDRIES U.S. INC.
    Inventors: Arkadiusz Malinowski, Baofu Zhu, Judson R. Holt, Shiv Kumar Mishra
  • Patent number: 11043653
    Abstract: Optoelectronic devices that include a composite film in a multilayered encapsulation stack are provided. Also provided are methods of forming the light reflection-modifying structures, as well as other polymeric device layers, using inkjet printing. The composite films include a first, lower refractive index domain and a second, higher refractive index domain.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 22, 2021
    Assignee: KATEEVA, INC.
    Inventors: Florian Pschenitzka, Christopher D. Favaro
  • Patent number: 11022757
    Abstract: Embodiments herein describe a photonic platform where an AR coating is disposed between an optical grating and a semiconductor substrate. In one embodiment, the optical grating is disposed within an insulative layer. A first side of the insulative layer provides an optical interface where an external optical source can transmit an optical signal into, or a receive an optical signal from, the grating. A second, opposite side of the insulative layer contacts the AR coating. When the external optical source transmits light through the first side of the insulative layer, some of the light passes through the grating and reaches the AR coating. The AR coating prevents this light from being reflected back to the grating by the semiconductor layer which can cause interference that varies the coupling efficiency of the grating.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: June 1, 2021
    Assignee: Cisco Technology, Inc.
    Inventors: Xunyuan Zhang, Shiyi Chen, Tao Ling, Prakash B. Gothoskar
  • Patent number: 11004954
    Abstract: Integrated circuit transistor structures are disclosed that include a single crystal buffer structure that is lattice matched to the underlying single crystal silicon substrate. The buffer structure may be used to reduce sub-fin leakage in non-planar transistors, but can also be used in planar configurations. In some embodiments, the buffer structure is a single continuous layer of high bandgap dielectric material that is lattice matched to silicon. The techniques below can be utilized on NMOS and PMOS transistors, including any number of group IV and III-V semiconductor channel materials.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: May 11, 2021
    Assignee: Intel Corporation
    Inventors: Karthik Jambunathan, Glenn A. Glass, Anand S. Murthy, Jack T. Kavalieros, Seung Hoon Sung, Benjamin Chu-Kung, Tahir Ghani
  • Patent number: 10978564
    Abstract: The present disclosure relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor layer; a source electrode, a drain electrode and a gate electrode located between the source electrode and the drain electrode disposed on a side of the semiconductor layer; at least two dielectrics located between the gate electrode and the drain electrode, wherein a dielectric coefficient of a dielectric adjacent to the gate electrode is greater than that of a dielectric away from the gate electrode and adjacent to the drain electrode.
    Type: Grant
    Filed: November 23, 2018
    Date of Patent: April 13, 2021
    Assignee: GPOWER SEMICONDUCTOR, INC.
    Inventor: Yuan Li
  • Patent number: 10978355
    Abstract: A device includes a semiconductor substrate, isolation regions in the semiconductor substrate, and a Fin Field-Effect Transistor (FinFET). The FinFET includes a channel region over the semiconductor substrate, a gate dielectric on a top surface and sidewalls of the channel region, a gate electrode over the gate dielectric, a source/drain region, and an additional semiconductor region between the source/drain region and the channel region. The channel region and the additional semiconductor region are formed of different semiconductor materials, and are at substantially level with each other.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Kuo, Yuan-Shun Chao, Hou-Yu Chen, Shyh-Horng Yang
  • Patent number: 10971512
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: April 6, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Hidenobu Nagashima
  • Patent number: 10964268
    Abstract: The present disclosure provides a shift register, a driving method thereof, a scan driving circuit and a display device. The shift register includes: a first node control module configured to control level at the first node based on an input signal and a second clock signal; a second node control module configured to control level at a second node based on the input signal, the first clock signal, the second clock signal, a low level signal and a high level signal; and an output control module configured to control the output terminal to output high level or low level based on level at the first node, level at the second node and the second clock signal. The second node can be provided with a relatively low level, which is conductive to maintaining a normal output of the shift register.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: March 30, 2021
    Assignee: SHANGHAI TIANMA AM-OLED CO., LTD.
    Inventors: Renyuan Zhu, Yue Li, Dongxu Xiang, Yana Gao, Xingyao Zhou
  • Patent number: 10957754
    Abstract: A display device includes a display panel including a flexible region and a low flexibility region, wherein the flexible region may include a first transistor including a first semiconductor layer and a first gate electrode, a first conductor connected to the first semiconductor layer, and a first interlayer insulating layer between the first transistor and the first conductor. The low flexibility region may include a second transistor including a second semiconductor layer and a second gate electrode, a second conductor connected to the second semiconductor layer, and a second interlayer insulating layer between the second transistor and the second conductor. The first interlayer insulating layer may include an organic insulating material, the second interlayer insulating layer includes an inorganic insulating material, and a ratio of channel width to channel length of the first transistor may be different from that of the second transistor.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: March 23, 2021
    Assignee: Samsung Display Co., Ltd.
    Inventors: June Woo Lee, Shin Moon Kang, Byoung Ki Kim, Hee Kyung Kim, Hyun Chui Son, Yun-Mo Chung, Jae Beom Choi
  • Patent number: 10950677
    Abstract: The present disclosure provides an array substrate and a manufacturing method of the array substrate, and a display panel. The array substrate includes a flexible substrate; an active layer disposed on the flexible substrate; a first gate insulating layer disposed on the active layer; a first gate layer disposed on the first gate insulating layer; a second gate insulating layer disposed on the first gate insulating layer and the first gate layer; and a second gate layer disposed on the second gate insulating layer. The array substrate of the present disclosure replaces molybdenum wires of a gate layer and a second gate layer with a multi-layered composite metal layer. The bending tolerance of gate wires in the display panel is enhanced and increase of impedance of the first gate layer is prevented.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: March 16, 2021
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Yun Yu, Weiwei Yang
  • Patent number: 10943984
    Abstract: The present disclosure provides a thin film transistor and a manufacturing method thereof, a display substrate and a manufacturing method thereof, and a display device. The thin film transistor of the embodiments of the present disclosure comprises an active layer pattern disposed on a base substrate, a gate electrode insulating pattern disposed on the active layer pattern, and a gate electrode disposed on the gate electrode insulating pattern, wherein a conductive pattern is disposed between the gate electrode and the gate electrode insulating pattern, the conductive pattern being electrically connected to the gate electrode, and an orthographic projection of the conductive pattern on the base substrate being overlapped with an orthographic projection of the gate electrode insulating pattern on the base substrate.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: March 9, 2021
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wei Liu
  • Patent number: 10930663
    Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: February 23, 2021
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Lidong Song, Yongna Li, Feng Pan, Steve Weiyi Yang, Wenguang Shi
  • Patent number: 10930197
    Abstract: A display apparatus includes a display panel, a display panel driver and a first connection wire. The display panel includes a substrate and a display layer disposed on a first surface of the substrate. The display panel driver applies a driving signal to the display panel. The display panel driver is disposed on a second surface opposite to the first surface of the substrate. The first connection wire is disposed at a first side surface connecting the first and second surfaces of the substrate. The first connection wire connects electrically the display panel with the display panel driver.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: February 23, 2021
    Inventors: Se-Ho Lee, Tae-Hyung Kim, Je-Hyun Song
  • Patent number: 10930720
    Abstract: One embodiment of the invention is characterized as follows. A display device comprising: a display area including a plurality of pixels, each of the pixels has a first TFT and a second TFT, the first TFT and the second TFT comprise an oxide semiconductor, the first TFT and the second TFT are covered by an interlayer insulating film, a first through hole is formed in the in the interlayer insulating film to connect a drain of the first TFT, wherein a distance d1 between a center of the first through hole and an edge of a channel of the first TFT is shorter than a distance d2 between a center of the first through hole and an edge of a channel of the second TFT, a channel length of the first TFT is shorter than a channel length of the second TFT.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: February 23, 2021
    Assignee: JAPAN DISPLAY INC.
    Inventors: Miyuki Ishikawa, Masashi Tsubuku
  • Patent number: 10930657
    Abstract: Provided herein may be a semiconductor device. The semiconductor device may include a stack. The semiconductor device may include channel layers including channel patterns passing through the stack, dummy channel patterns passing through the stack, and a coupling pattern which may be disposed below the stack and couples the channel patterns with the dummy channel patterns. The semiconductor device may include a bit line which is disposed on the stack and coupled with the channel patterns. The semiconductor device may include a well pick-up line which is disposed on the stack and coupled with the dummy channel patterns.
    Type: Grant
    Filed: February 14, 2019
    Date of Patent: February 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Patent number: 10923493
    Abstract: A semiconductor device comprises a stack comprising an alternating sequence of dielectric structures and conductive structures, and a channel structure within an opening vertically extending through the stack and comprising a first semiconductor material having a first band gap. The semiconductor device also comprises a conductive plug structure within the opening and in direct contact with the channel region, and a band offset structure within the opening and in direct physical contact with the channel structure and the conductive plug structure. The band offset structure comprises a second semiconductor material having a second band gap different than the first band gap. The semiconductor device further comprises a conductive line structure electrically coupled to the conductive plug structure. A method of forming a semiconductor device and an electronic system are also described.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Albert Fayrushin, Haitao Liu, Mojtaba Asadirad
  • Patent number: 10916563
    Abstract: A semiconductor device includes a substrate having a cell region and an extension region, channel structures disposed in the cell region and extending in a first direction substantially perpendicular to an upper surface of the substrate, gate electrode layers surrounding the channel structures and stacked to be spaced apart from each other in the first direction and to extend in a second direction substantially perpendicular to the first direction, and word line cuts cutting the gate electrode layers in the first direction and continuously extending in the second direction. At least one of the word line cuts is an extension word line cut with an extension portion having an area that is different from those of the remaining word line cuts located at the same level as the at least one word line cut in a predetermined region extending in the second direction.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: February 9, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Woo Kim, Joon Young Kwon, Jung Hwan Lee, Jung Tae Sung, Ji Min Shin
  • Patent number: 10903249
    Abstract: An array substrate including a plurality of terminals, a first conductive layer and a second conductive layer, wherein the first conductive layer and the second conductive layer include an insulating layer therebetween, wherein a plurality of first electrode plates and a plurality of second electrode plates are formed in the first conductive layer and the second conductive layer, respectively, the first electrode plates and the second electrode plates are opposite to each other to constitute a capacitor structure, the terminals are provided in the same layer as the first conductive layer or the second conductive layer, or the terminals are provided in the same layer as a third conductive layer between the first conductive layer and the second conductive layer. A method of manufacturing an array substrate and a display device is provided.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: January 26, 2021
    Assignees: ORDOS YUANSHENG OPTOELECTRONICS CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Zhang, Hui Li, Tianlei Shi, Jonguk Kwak, Yezhou Fang, Wenlong Zhang, Xu Zhang, Zhijun Niu, Ruize Jiang, Yanwei Ren, Yu Liu
  • Patent number: 10902790
    Abstract: A novel semiconductor device with high convenience or high reliability is provided. The semiconductor device includes an arithmetic logic unit and an amplifier. The arithmetic logic unit is configured to generate second data on the basis of an offset adjustment signal or offset data and first data. The amplifier includes an operational amplifier and an offset adjustment circuit including a register. The operational amplifier supplies a predetermined voltage to a node on the basis of a voltage between a first terminal and a second terminal. The register is configured to retain, as the offset data, the offset adjustment signal on the basis of a latch signal. The register is configured to allow the supplied offset adjustment signal to pass therethrough in a passage state and supply the offset adjustment signal. The register is configured to supply the offset data in a non-passage state.
    Type: Grant
    Filed: February 5, 2018
    Date of Patent: January 26, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kei Takahashi
  • Patent number: 10896914
    Abstract: A semiconductor memory device comprises: a substrate; gate electrodes arranged in a first direction crossing a surface of the substrate; a first semiconductor layer including a first portion extending in the first direction and facing the plurality of gate electrodes, and, a second portion nearer to the substrate than the first portion; a gate insulating film provided between the gate electrode and the first portion of the first semiconductor layer, and, including a memory portion; and, a wiring portion provided between the substrate and the plurality of gate electrodes, connected to the second portion of the first semiconductor layer, and, extending in a second direction crossing the first direction. The wiring portion comprises a second semiconductor layer connected to the second portion of the first semiconductor layer. The second semiconductor layer includes a first crystal grain larger than a thickness in the first direction of the second semiconductor layer.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: January 19, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takashi Tachikawa, Hidenori Miyagawa
  • Patent number: 10861931
    Abstract: Semiconductor devices include a semiconductor layer structure comprising a drift region that includes a wide band-gap semiconductor material. A shielding pattern is provided in an upper portion of the drift region in an active region of the device and a termination structure is provided in the upper portion of the drift region in a termination region of the device. A gate trench extends into an upper surface of the semiconductor layer structure. The semiconductor layer structure includes a semiconductor layer that extends above and at least partially covers the termination structure.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: December 8, 2020
    Assignee: Cree, Inc.
    Inventors: Daniel J. Lichtenwalner, Edward R. Van Brunt, Brett Hull
  • Patent number: 10854591
    Abstract: A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt.
    Type: Grant
    Filed: February 24, 2017
    Date of Patent: December 1, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wei-E Wang, Titash Rakshit, Borna J. Obradovic, Chris Bowen, Mark S. Rodder
  • Patent number: 10847531
    Abstract: Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a substrate, an alternating layer stack including a staircase structure on the substrate, and a barrier structure extending vertically through the alternating layer stack. The alternating layer stack includes an alternating dielectric stack and an alternating conductor/dielectric stack. The alternating dielectric stack includes dielectric layer pairs enclosed by at least the barrier structure. The alternating conductor/dielectric stack includes conductor/dielectric layer pairs. The memory device further includes a channel structure and a slit structure each extending vertically through the alternating conductor/dielectric stack, an etch stop layer on an end of the channel structure, and first contacts.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: November 24, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Zhenyu Lu, Lidong Song, Yongna Li, Feng Pan, Steve Weiyi Yang, Wenguang Shi
  • Patent number: 10840087
    Abstract: A boron nitride, boron carbide, or boron carbonitride film can be deposited using a remote plasma chemical vapor deposition (CVD) technique. A boron-containing precursor is provided to a reaction chamber, where the boron-containing precursors has at least one boron atom bonded to a hydrogen atom. Radical species, such as hydrogen radical species, are provided from a remote plasma source and into the reaction chamber at a substantially low energy state or ground state. A hydrocarbon precursor may be flowed along with the boron-containing precursor, and a nitrogen-containing plasma species may be introduced along with the radical species from the remote plasma source and into the reaction chamber. The boron-containing precursor may interact with the radical species along with one or both of the hydrocarbon precursor and the nitrogen-containing precursor to deposit the boron nitride, boron carbide, or boron carbonitride film.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: November 17, 2020
    Assignee: Lam Research Corporation
    Inventors: Matthew Scott Weimer, Bhadri N. Varadarajan
  • Patent number: 10840257
    Abstract: A semiconductor memory device includes: a semiconductor substrate; a memory cell array provided in a first region; a first transistor provided in a second region; a second transistor provided in a third region; and an insulative laminated film. The first and second transistors each include a semiconductor layer, a gate electrode, and a gate insulating film. A concentration of boron (B) in the gate electrode of the second transistor is higher than that of the first transistor. The insulative laminated film includes a first insulating film contacting the surface of the semiconductor substrate, and a second insulating film having a smaller diffusion coefficient of hydrogen (H) than that of the first insulating film. The second insulating film has a first portion contacting the semiconductor portion, and the first portion surrounds the third region.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: November 17, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tetsuya Furukawa, Tomoaki Shino, Mitsuhiro Noguchi, Shinichi Watanabe, Yukio Nishida, Hiroyasu Tanaka
  • Patent number: 10811434
    Abstract: An array substrate and a manufacturing method thereof, a display panel and display device relating to display technology are provided. The array substrate includes: a substrate; a light shielding layer being of electrical conductive over the substrate; a buffer layer over the light shielding layer; an active layer insulated from the light shielding layer by the buffer layer and shielded by the light shielding layer against light radiation; a gate insulating layer disposed over the active layer; and a patterned first electrode layer having a first electrode over the gate insulating layer, the first electrode being a gate electrode; wherein the patterned first electrode layer further comprises a second electrode over the buffer layer, the second electrode having at least a portion in contact with the buffer layer. The buffer layer comprises a first via-hole, and the second electrode is in electrical connection with the light shielding layer through the first via-hole.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: October 20, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wei Liu
  • Patent number: 10809581
    Abstract: Provided is an active matrix substrate 20a in which either a plurality of source lines (data lines) 15S or a plurality of gate lines 13G, as constituent elements of the active matrix substrate 20a, are vertical lines extending in the longitudinal direction, and the other are horizontal lines. Among a plurality of pixel control elements 16T that are provided in correspondence to a plurality of pixels and are connected with the data line 15S and the gate lines 13G so as to control display of the corresponding pixels, respectively, a part of the pixel control elements 16T connected with one same horizontal line are arranged on one side with respect to the respective vertical lines to which the pixel control elements are connected, the side being different from a side on which the other pixel control elements connected with the same horizontal line are arranged.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: October 20, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takayuki Nishiyama, Kohhei Tanaka, Takeshi Noma, Ryo Yonebayashi, Yosuke Iwata
  • Patent number: 10811521
    Abstract: In a top-gate transistor in which an oxide semiconductor film, a gate insulating film, a gate electrode layer, and a silicon nitride film are stacked in this order and the oxide semiconductor film includes a channel formation region, nitrogen is added to regions of part of the oxide semiconductor film and the regions become low-resistance regions by forming a silicon nitride film over and in contact with the oxide semiconductor film. A source and drain electrode layers are in contact with the low-resistance regions. A region of the oxide semiconductor film, which does not contact the silicon nitride film (that is, a region overlapping with the gate insulating film and the gate electrode layer) becomes the channel formation region.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: October 20, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kenichi Okazaki, Junichi Koezuka, Toshinari Sasaki
  • Patent number: 10796993
    Abstract: Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: October 6, 2020
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Jifeng Zhu, Jun Chen, Si Ping Hu, Zhenyu Lu
  • Patent number: 10789906
    Abstract: A gate driving circuit includes a plurality of driving stages, wherein an ith (where i is a natural number of 2 or more) driving stage among the plurality of driving stages includes: a output unit outputting an ith output signal including a high voltage generated based on a clock signal in response to a low voltage at a Q-node; a stabilization unit providing the low voltage to the Q-node in response to a switching signal applied to an A-node after the ith output signal is outputted; and an inverter unit outputting the switching signal for controlling the stabilization unit to the A-node.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: September 29, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Junhyun Park, Jonghee Kim, Sunghwan Kim, Jaekeun Lim, Chongchul Chai
  • Patent number: 10777464
    Abstract: A method of forming a semiconductor device that includes forming a vertically orientated channel in a semiconductor fin structure that is present on a supporting substrate; and depositing a doped amorphous semiconductor material on an upper surface of the semiconductor fin structure that is opposite a base surface of the semiconductor fin structure that is in contact with the supporting substrate. The method further includes recrystallizing the doped amorphous semiconductor material with an anneal duration for substantially a millisecond duration or less to provide a doped polycrystalline source and/or drain region at the upper surface of the semiconductor fin structure.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: September 15, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Shogo Mochizuki, Oleg Gluschenkov
  • Patent number: 10770480
    Abstract: Systems, methods and apparatus for coexistence of high voltage and low voltage devices and circuits on a same integrated circuit fabricated in silicon-on-insulator (SOI) technology are described. In particular, techniques for mitigating back gate effects are described, including using of resistive and/or capacitive couplings to control surface potentials at regions of a substrate used for the SOI fabrication proximate the high voltage and low voltage devices and circuits. In one case, an N-type implant is used to provide a high potential differential with respect to a substrate potential.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: September 8, 2020
    Assignee: pSemi Corporation
    Inventors: Buddhika Abesingha, Simon Edward Willard, Alain Duvallet, Merlin Green, Sivakumar Kumarasamy
  • Patent number: 10768731
    Abstract: A display device and method of manufacturing the same are provided. A display device includes: a device substrate, a light-emitting element on the device substrate, an encapsulating structure on the light-emitting element, a touch structure on the encapsulating structure, an elastic insulating layer on the touch structure, the elastic insulating layer including an elastic material, and a high-permittivity particles dispersed in the elastic insulating layer.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: September 8, 2020
    Assignee: LG Display Co., Ltd.
    Inventors: Young-Sub Shin, Byong-Hoo Kim
  • Patent number: 10756132
    Abstract: The present technology relates to a solid-state imaging device capable of protecting a photoelectric conversion film with a sealing film that has excellent sealing properties and coverage, a method of manufacturing the solid-state imaging device, and an electronic apparatus. A solid-state imaging device includes: a photoelectric conversion film formed on the upper side of a semiconductor substrate; and a sealing film that is formed on the upper layer of the photoelectric conversion film and has a lower etching rate than that of silicon oxide. The present technology can be applied to solid-state imaging devices having a photoelectric conversion film on the upper side of a semiconductor substrate, and the like, for example.
    Type: Grant
    Filed: March 15, 2017
    Date of Patent: August 25, 2020
    Assignee: SONY CORPORATION
    Inventors: Shigehiro Ikehara, Masahiro Joei
  • Patent number: 10700182
    Abstract: By using at least one of a processor device and model transistor cells, a set of design parameters for at least one of a transistor cell and a drift structure of a wide band-gap semiconductor device is determined, wherein an on state failure-in-time rate and an off state failure-in-time rate of a gate dielectric of the transistor cell are within a same order of magnitude for a predefined on-state gate-to-source voltage, a predefined off-state gate-to-source voltage, and a predefined off-state drain-to-source voltage.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Wolfgang Bergner, Romain Esteve, Daniel Kueck, Dethard Peters, Ralf Siemieniec, Bernd Zippelius
  • Patent number: 10700082
    Abstract: A semiconductor storage device includes a base body, a stacked body, a plurality of columns, and a plurality of first contacts. The base body includes a substrate, a semiconductor element on the substrate, a lower wiring layer above the semiconductor element in a thickness direction of the base body and connected to the semiconductor element, and a lower conductive layer above the lower wiring layer in the thickness direction. The stacked body is above the lower conductive layer and including an alternating stack of conductive layers and insulating layers. Each of the columns includes a semiconductor body extending through the stacked body and electrically connected to the lower conductive layer. The plurality of first contacts extend through the stacked body and electrically connected to the lower conductive layer. The lower conductive layer is separately provided under each of the plurality of first contacts.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: June 30, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Go Oike
  • Patent number: 10700165
    Abstract: A doped diamond semiconductor and method of production using a laser is disclosed herein. As disclosed, a dopant and/or a diamond or sapphire seed material may be added to a graphite based ablative layer positioned below a confinement layer, the ablative layer also being graphite based and positioned above a backing layer, to promote formation of diamond particles having desirable semiconductor properties via the action of a laser beam upon the ablative layer. Dopants may be incorporated into the process to activate the reaction sought to produce a material useful in production of a doped semiconductor or a doped conductor suitable for the purpose of modulating the electrical, thermal or quantum properties of the material produced. As disclosed, the diamond particles formed by either the machine or method of confined pulsed laser deposition disclosed may be arranged as semiconductors, electrical components, thermal components, quantum components and/or integrated circuits.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: June 30, 2020
    Assignee: Adamantite Technologies LLC
    Inventor: Eric David Bauswell
  • Patent number: 10685958
    Abstract: Disclosed herein is a composite transistor which includes a first transistor including a control electrode, a first active region, a first A extending part, and a first B extending part, and a second transistor including a control electrode, a second active region, a second A extending part, and a second B extending part. The first active region, the second active region, and the control electrode overlap one another. Both the first A extending part, and the first B extending part extend from the first active region and both the second A extending part and the second B extending part extend from the second active region. The first electrode is connected to the first A extending part, the second electrode is connected to the second A extending part, and the third electrode is connected to the first B extending part and the second B extending part.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: June 16, 2020
    Assignee: Sony Corporation
    Inventor: Koichi Matsumoto
  • Patent number: 10679861
    Abstract: A manufacturing method of a semiconductor device comprises forming an ohmic electrode on a surface of a semiconductor substrate, the ohmic electrode including an aluminum layer in a side opposite to a side in contact with the semiconductor substrate, performing a heat treatment on the ohmic electrode, performing an acid treatment on a surface of the aluminum layer in the ohmic electrode that has been subjected to the heat treatment and forming a wiring electrode in the side of the aluminum layer opposite to the side where the semiconductor substrate is provided after the acid treatment.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: June 9, 2020
    Assignee: TOYODA GOSEI CO., LTD.
    Inventor: Kota Yasunishi
  • Patent number: 10656491
    Abstract: A liquid-crystal display including: a gate line extending in a first direction; a gate electrode protruding from the gate line; a gate insulating layer arranged on the gate electrode; an active layer arranged on the gate insulating layer while being insulated from the gate electrode; a data line arranged on the active layer and extending in a second direction; a source electrode protruding from the data line, having a portion overlapping the gate electrode on a plane, and including a plurality of source electrode branches that are separate from each other; a drain electrode being separate from the source electrode, and including a plurality of drain electrode branches, each being arranged between two of the plurality of source electrode branches, and a drain electrode connecting part connecting the plurality of drain electrode branches; a pixel electrode defining a pixel region; a liquid-crystal layer arranged on the pixel electrode.
    Type: Grant
    Filed: July 5, 2017
    Date of Patent: May 19, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Gichang Lee, Yongjo Kim, Cholho Kim, Gunwoo Yang, Jihoon Yang, Yongwoo Lee
  • Patent number: 10650731
    Abstract: The disclosure provides a display apparatus. The display apparatus of the disclosure includes a substrate having a plurality of pixel regions, a plurality of active elements, a plurality of first signal lines and second signal lines, a plurality of ground signal lines and a plurality of light emitting diodes (LEDs). The plurality of ground signal lines are disposed on the substrate and arranged to alternate with the first signal lines. At least one LED has first and second electrodes. The first electrode of at least one LED is electrically connected with a corresponding active element. A second electrode of at least one LED is electrically connected with a corresponding ground signal line. At least two LEDs disposed in an identical pixel region is electrically connected with an identical ground signal line between two first signal lines adjacent to each other. The display apparatus of the disclosure has high resolution.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: May 12, 2020
    Assignee: Innolux Corporation
    Inventors: Chun-Hsien Lin, Chih-Yung Hsieh, Tsau-Hua Hsieh, Shu-Ming Kuo
  • Patent number: 10651190
    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, memory pillars, first and second insulation layers and an isolation region. The stacked body above a substrate includes conductive layers isolated from each other and stacked along a first direction crossing the substrate surface. The memory pillars extend through the stacked body along the first direction. The first insulation layer is provided above the memory pillars. The isolation region is provided higher than upper surfaces of the memory pillars in the stacked body along the first direction, and isolates the stacked body in a second direction crossing the first direction. The second insulation layer is provided on the first insulation layer and a side wall of the isolation region.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: May 12, 2020
    Assignee: Toshiba Memory Corporation
    Inventor: Hidenobu Nagashima
  • Patent number: 10641957
    Abstract: In integrated optical structures (e.g., silicon-to-silicon-nitride mode converters) implemented in semiconductor-on-insulator substrates, wire waveguides whose sidewalls substantially consist of portions coinciding with crystallographic planes and do not extend laterally beyond the top surface of the wire waveguide may provide benefits in performance and/or manufacturing needs. Such wire waveguides may be manufactured, e.g., using a dry-etch of the semiconductor device layer down to the insulator layer to form a wire waveguide with exposed sidewalls, followed by a smoothing crystallographic wet etch.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: May 5, 2020
    Assignee: Juniper Networks, Inc.
    Inventors: Avi Feshali, John Hutchinson, Jared Bauters
  • Patent number: 10636914
    Abstract: A crystalline oxide semiconductor thin film that is composed mainly of indium oxide and comprises surface crystal grains having a single crystal orientation.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: April 28, 2020
    Assignee: IDEMITSU KOSAN CO., LTD.
    Inventors: Kazuyoshi Inoue, Futoshi Utsuno, Yuki Tsuruma, Shigekazu Tomai, Kazuaki Ebata
  • Patent number: 10629626
    Abstract: A display apparatus including a first thin film transistor disposed on a substrate and including a first active layer, a second thin film transistor disposed on the first thin film transistor and including a second active layer overlapping the first thin film transistor, a first planarization layer disposed between the first thin film transistor and the second thin film transistor, the first planarization layer including a first insulating layer and a second insulating layer disposed on the first insulating layer, and a first buffer layer disposed between the first planarization layer and the second thin film transistor, in which an upper surface of the second insulating layer and an upper surface of the first insulating layer are substantially flush with each other.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: April 21, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Yunmo Chung, Daewoo Lee, Ilhun Seo, Hojin Yoon
  • Patent number: 10622484
    Abstract: The present invention provides a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer, which are laminated on a substrate. The semiconductor layer is a polysilicon thin film. The polysilicon thin film in regions corresponding to the source electrode and the drain electrode has a smaller crystal grain size than that of the polysilicon thin film in a channel region between the source electrode and the drain electrode.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: April 14, 2020
    Assignee: V TECHNOLOGY CO., LTD.
    Inventors: Michinobu Mizumura, Makoto Hatanaka, Tetsuya Kiguchi
  • Patent number: 10580902
    Abstract: A transistor may include a semiconductor, a source electrode, a drain electrode, and a gate electrode. The semiconductor may include a first doped region, a second doped region, a source region, a drain region, and a channel region. The channel region is positioned between the source region and the drain region. The first doped region is positioned between the channel region and the source region. The second doped region is positioned between the channel region and the drain region. A doping concentration of the first doped region is lower than a doping concentration of the source region. A doping concentration of the second doped region is lower than a doping concentration of the drain region. The source electrode is electrically connected to the source region. The drain electrode is electrically connected to the drain region. The gate electrode overlaps the channel region.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: March 3, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ji Hun Lim, Joon Seok Park, Jay Bum Kim, Jun Hyung Lim, Kyoung Seok Son