Abstract: A semiconductor integrated circuit in which the storage capacitor has an increased capacitance and a decreased leakage current. The storage capacitor is formed by the steps of: forming a polysilicon bottom electrode having semispherical silicon crystals formed thereon; performing plasma nitriding on the surface of said bottom electrode at a temperature lower than 550° C., thereby forming a film of silicon nitride having a film thickness smaller than 1.5 nm; and depositing a film of amorphous tantalum pentoxide and then crystallizing said amorphous tantalum pentoxide. The silicon nitride film has improved resistance to oxidation and also has a reduced leakage current. As a result, the polysilicon bottom electrode becomes resistant to oxidation and the storage capacitor increases in capacitance and decreases in leakage current.

Abstract: A semiconductor memory device having a trench capacitor, comprising: a semiconductor substrate of a fist conductivity type, having a trench which is formed from an upper surface of the semiconductor substrate to a predetermined depth; a capacitor formed in a lower portion of the trench and the semiconductor substrate of the fist conductivity type which is adjacent to the lower portion of the trench; a first conductive layer formed in the first trench and right above the first capacitor to which the first conductive layer is electrically connected; a first insulation film formed in the trench and right above the first conductive layer; a first diffusion layer formed in the semiconductor substrate of the fist conductivity type which is adjacent to the first conductive layer and the first insulation film, the first diffusion layer served as a source/drain electrode; a gate insulation film formed on a predetermined portion of the trench, the predetermined portion being located above the first insulation film; a s

Abstract: A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.

Abstract: The invention includes three-dimensional TFT based stacked CMOS inverters. Particular inverters can have a PFET device stacked over an NFET device. The PFET device can be a semiconductor-on-insulator thin film transistor construction, and can be formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic). The thin film of semiconductor material can comprise both silicon and germanium. Further, the thin film can contain two different layers. A first of the two layers can have silicon and germanium present in a relaxed crystalline lattice, and a second of the two layers can be a strained crystalline lattice of either silicon alone, or silicon in combination with germanium. The invention also includes computer systems utilizing such CMOS inverters.

Abstract: A first insulating hydrogen barrier film is filled between lower electrodes of some ferroelectric capacitors arranged along one direction out of a word line direction and a bit line direction among a plurality of ferroelectric capacitors included in a ferroelectric memory of this invention. A common capacitor dielectric film commonly used by the some ferroelectric capacitors arranged along the one direction is formed on the lower electrodes of the some ferroelectric capacitors arranged along the one direction and on the first insulating hydrogen barrier film. A common upper electrode commonly used by the some ferroelectric capacitors arranged along the one direction is formed on the common capacitor dielectric film. A second insulating hydrogen barrier film is formed so as to cover the common upper electrode.

Abstract: The present invention discloses a ferroelectric memory device and a method of forming the same. The ferroelectric memory device includes a semiconductor substrate, a capacitor lower electrode, a ferroelectric layer, and a capacitor upper electrode. The semiconductor substrate has a lower structure. The capacitor lower electrode has a cylindrical shape and a certain height. The ferroelectric layer is conformally stacked over substantially the entire surface of the semiconductor substrate including the capacitor lower electrode. The capacitor upper electrode has a spacer shape and is formed around the sidewall of the ferroelectric layer that surrounds the lower electrode. In the method of forming the ferroelectric memory device, a semiconductor substrate having an interlayer dielectric layer and a lower electrode contact formed through the interlayer dielectric layer is prepared. A cylindrical capacitor lower electrode is formed on the interlayer dielectric layer to cover the contact.

Abstract: The present invention discloses a TFT array substrate (and method for making the same) having the large storage capacitance for use in a liquid crystal display device. In a four-mask process, the conventional storage capacitor of the TFT array substrate includes the capacitor electrodes and the insulation layer and semiconductor layer as a dielectric layer. However, the present invention includes the capacitor electrodes and the insulation layer as a dielectric layer so that the thickness of the dielectric layer becomes thinner. Therefore, much more electric charges can be stored in the storage capacitor. That means the liquid crystal display device can have a high picture quality and a high definition. Moreover, the present invention has a structure that can achieve the high manufacturing yield.

Abstract: A high density MIM capacitor structure and method of manufacturing the same is disclosed for integrated circuits having multiple metal layer interconnections. The capacitor structure is formed between selected first and second metallic interconnections which are separated by an insulating intermetallic oxide layer. A first metal-dielectric-metal layer capacitor is created over and with a portion of the first metallic interconnection and a second metal-dielectric-metal layer capacitor is created under and with a portion of the second metallic interconnection. A first metal via through the insulating intermetallic oxide layer connects the first metal-dielectric-metal layer capacitor and the second metal-dielectric-metal layer capacitor to form a first terminal of the capacitor structure and a second metal via through the insulating intermetallic oxide layer connects the first metallic interconnection portion and the second metallic interconnection portion to form a second terminal of the capacitor structure.

Abstract: In a semiconductor memory including a dynamic random access memory, a memory cell of the dynamic random access memory includes: a semiconductor pillar (a silicon pillar); a capacitor in which one side of the silicon pillar is used as a charge accumulation electrode; and a longitudinal insulated gate static induction transistor in which the other side of the silicon pillar is used as an active region (a source region, a channel formation region and a drain region), and a bit line is connected to the silicon pillar.

Abstract: In one implementation, integrated circuitry includes a first capacitor electrode layer received over a substrate. A capacitor dielectric layer is received over the first capacitor electrode layer. The capacitor dielectric layer has an edge terminus. A second capacitor electrode layer is received over the capacitor dielectric layer. The first capacitor electrode layer and the second capacitor electrode layer, respectively, have opposing lateral edges. The capacitor dielectric layer edge terminus is laterally coincident with at least a portion of one of the opposing lateral edges of the second capacitor electrode layer. An insulative silicon nitride including cap is received over the capacitor dielectric layer edge terminus and the one opposing lateral edge of the second capacitor electrode layer. The cap does not contact any portion of the opposing lateral edges of the first capacitor electrode layer. Other aspects and implementations are disclosed.

Abstract: A capacitor having an equivalent thickness of 3.0 nm or less, with a sufficient static capacitance and less leakage current in a reduced size, constituted by stacking an interfacial film 21 having a physical thickness of 2.5 nm or more for suppressing tunnel leakage current and a high dielectric film 22 comprising tantalum pentaoxide on lower electrode 19, 20 comprising rugged polycrystal silicon film, the interfacial film 21 comprising a nitride film formed by an LPCVD method, for example, from Al2O3, a mixed phase of Al2O3 and SiO2, ZrSiO4, HfSiO4, a mixed phase of Y2O3 and SiO2, and a mixed phase of La2O3 and SiO2.

Abstract: A two-transistor SRAM cell includes a first FET. The first FET is an ultrathin FET of a first polarity type and includes a control electrode, a first load electrode and a second electrode. The first load electrode is coupled to a first control line. The SRAM cell also includes a second FET. The second FET is an ultrathin FET of a second polarity type and includes a gate, a source and a drain. The second FET source is coupled to the first FET gate. The second FET gate is coupled to the first FET drain and the second FET source is coupled to a first potential. The SRAM cell further includes a first load device that is coupled between a second potential and the first FET gate. The SRAM cell additionally includes a second load device coupled between the second FET gate and a second control line.

Abstract: An electro-optical device including an auxiliary capacitance using a pair of transparent conductive films is improved to provide a semiconductor device with high quality. A first transparent conductive film and a capacitance insulating film are formed into a laminate on a leveling film, and an opening portion is formed. An insulating film is formed thereon, and a second transparent conductive film is patterned to form a pixel electrode. At this time, the auxiliary capacitance made of a structure in which the capacitance insulating film is sandwiched between the first transparent conductive film and the pixel electrode is formed.

Abstract: A method of forming a cell memory structure including the step of planarizing an HDP/LDP oxide layer lying over a capacitor area. The method provides for the planarization of the cell storage node, good isolation between the transistor and storage node, reduced step height for the cell-transistor and has the potential for increasing the node capacitance (like DRAM storage node).

Abstract: The stack-type DRAM memory structure of the present invention comprises a plurality of self-aligned thin third conductive islands over shallow heavily-doped source diffusion regions without dummy transistors to obtain a cell size of 6F2 or smaller; a rectangular tube-shaped cavity having a conductive island formed above a nearby transistor-stack being formed over each of the self-aligned thin third conductive islands to offer a larger surface area for forming a high-capacity DRAM capacitor of the present invention; a planarized third conductive island being formed between a pair of first sidewall dielectric spacers and on each of shallow heavily-doped common-drain diffusion regions to offer a larger contact area and a higher contact integrity; and a plurality of planarized conductive contact-islands being formed over the planarized third conductive islands to eliminate the aspect-ratio effect and being patterned and etched simultaneously with a plurality of bit lines.

Abstract: Semiconductor devices and methods of forming semiconductor devices are described. In one embodiment, at least one conductive structure is formed within a plurality of semiconductor substrates. At least portions of one of the conductive structures have oppositely facing, exposed outer surfaces. Individual substrates are stacked together in a die stack such that individual conductive structures on each substrate are in electrical contact with the conductive structures on a next adjacent substrate. In a preferred embodiment, the conductive structures comprise multi-layered, conductive pad structures.

Abstract: A semiconductor device includes a control circuit for carrying out gamma correction of a supplied signal, and a memory for storing data used in the gamma correction. The control circuit and the memory are constituted by TFTs, and are integrally formed on the same insulating substrate. A semiconductor display device includes a pixel region in which a plurality of TFTs are arranged in matrix; a driver for switching the plurality of TFTs; a picture signal supply source for supplying a picture signal; a control circuit for carrying out gamma correction of the picture signal; and a memory for storing data used in the gamma correction of the picture signal. The plurality of TFTs, the driver, the control circuit, and the memory are integrally formed on the same insulating substrate.

Abstract: A storage capacitor of a planar display is disclosed. The storage capacitor includes a substrate, a lower electrode, an insulator layer, and an upper electrode in space order. The lower electrode is made of a semiconductor material such as polysilicon. The upper electrode is made of metal or polysilicon. For the metallic upper electrode, the upper electrode is patterned to have a comb, fishbone or net shape in order to allow dopants penetrating therethrough to reach the lower electrode, thereby increasing the conductivity of the lower electrode. A process for fabricating such storage capacitor is also disclosed. For the case that both the upper and lower electrodes are made of polysilicon, two doping procedures of different doping intensities are performed to provide dopants for the upper and lower electrodes, respectively.

Abstract: Methods of forming integrated circuit devices (e.g., memory devices) include the use of preferred self-aligned contact hole fabrication steps. These steps improve process reliability by reducing the likelihood that contact holes will become misaligned to underlying integrated circuit device structures and thereby potentially expose the structures in an adverse manner. Typical methods include the steps of forming a plurality of interconnection patterns on a substrate and then covering a surface of the interconnection patterns and a portion of the substrate with a capping insulating layer such as silicon nitride layer. The capping insulating layer is then covered with an upper interlayer insulating layer different from the capping insulating layer. The upper interlayer insulating layer and the capping insulating layer are then dry-etched in sequence to form a first narrow contact hole that exposes the substrate, but preferably does not expose the interconnection patterns.

Abstract: To simplify a method for manufacturing a memory device having a multiplicity of MRAM cells in a crossing area of conductor elements, a method for manufacturing a semiconductor circuit system, in particular, a memory device or the like, having a plurality of memory cells includes the step of structuring each of the memory elements simultaneously with the structuring of the first and second conductor elements.

Abstract: The invention includes a method of forming a DRAM cell. A first substrate is formed to include first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate having a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which has a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further includes a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure includes a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.

Abstract: A semiconductor device comprises an SOI substrate, a trench, a trench capacitor, and a conductive layer. The SOI substrate includes a fist semiconductor region, a buried insulating film formed on the first semiconductor region, and a second semiconductor region formed on the buried insulating film. The trench is of a depth to reach the first semiconductor region, extending from a surface of the second semiconductor region on the SOI substrate and passing through the buried insulating film. The trench capacitor is formed within the trench. The conductive layer is formed in a region between a sidewall portion of the trench and the buried insulating film, and electrically connects the first semiconductor region and the second semiconductor region.

Abstract: A process and apparatus directed to forming metal plugs in a peripheral logic circuitry area of a semiconductor device to contact both N+ and P+ doped regions of transistors in the peripheral logic circuitry area. The metal plugs are formed after all high temperature processing used in wafer fabrication is completed. The metal plugs are formed without metal diffusing into the active areas of the substrate. The metal plugs may form an oval slot as seen from a top down view of the semiconductor device.

Abstract: A thermally stable nickel germanosilicide on SiGe integrated circuit device, and a method of making the same, is disclosed. During fabrication of the device iridium or cobalt is added at the Ni/SiGe interface to decrease the sheet resistance of the device. The device comprising nickel silicide with iridium on SiGe shows thermal stability at temperatures up to 800° C. The device comprising nickel silicide with cobalt on SiGe shows a decrease in the sheet resistance with temperature, i.e., the resistance remains low when annealing temperatures extend up to and beyond 800° C.

Abstract: A method for reducing random bit failures of flash memory fabrication processes with an HTO film. The random bit failures are caused by HF acid penetration. The HTO film, which functions as an interface reinforcement layer, is formed on a sacrificial layer and a PL1 layer. With the aid of the HTO film, the flash memory is free of acid-corroded seams.

Abstract: The invention includes a method of forming a DRAM cell. A first substrate is formed to comprise first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate comprising a monocrystalline material is bonded to the first substrate. After the bonding, second DRAM sub-structures are formed in electrical connection with the first DRAM sub-structures. The invention also includes a semiconductor structure which comprises a capacitor structure, and a first substrate defined to encompass the capacitor structure. The semiconductor structure further comprises a monocrystalline silicon substrate bonded to the first substrate and over the capacitor structure. Additionally, the semiconductor structure comprises a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.

Abstract: A structure and a manufacturing method of a semiconductor device composed of 1T1Cs, in which a surface area of a memory cell capacitor part is expanded by forming an uneven surface at the memory cell capacitor part, is provided. Further, an additional photo lithography process is not required at expanding the surface area, and the manufacturing efficiency is not decreased. At the manufacturing method of the semiconductor device, two kinds of spaces whose sizes are different are formed in a conductive layer by that a part of a first oxide film and a part of the conductive layer to its middle part are removed. After this, a second oxide film is formed on the whole surface so that a small space of the spaces is filled with the second oxide film and side walls are formed on the side surfaces of a large space by applying etching back. With this, an exposed part of the conductive layer is formed selectively, and this exposed part of the conductive layer is removed by the etching.

Abstract: A trench capacitor for use in a semiconductor memory cell is formed in a substrate. The trench capacitor includes a trench having an upper region and a lower region, an insulation collar formed in the upper region on a trench wall of the trench, and a buried well, through which the lower region of the trench at least partly extends. The trench capacitor further includes, as an outer capacitor electrode, a conductive layer lining the lower region of the trench and the insulation collar, a dielectric layer lining the conductive layer, and a conductive trench filling which is filled into the trench as an inner capacitor electrode. A method of fabricating a trench capacitor is also provided.

Abstract: A semiconductor device that quickly saves data stored in an area to which power is supplied intermittently. Power is supplied intermittently to a first area. Power is supplied continuously to a second area. A memory is located in the second area. A save circuit saves data used in the first area in the memory before the supply of power being stopped. A restoration circuit restores data which has been saved in the memory to a predetermined circuit in the first area. A power supply control circuit supplies power to the memory if data has been saved in the memory. Otherwise the power supply control circuit stops the supply of power to the memory.

Abstract: A structure and a manufacture method of a DRAM device with deep trench capacitors are described. Each capacitor has a collar oxide layer with different height for electrical isolation and leakage reduction. Further, the DRAM device has strip-type active areas to improve some optical errors and thus reduce sufficiently the contact resistance of a buried strap film of a capacitor.

Abstract: There is provided a semiconductor device including a storage capacitor having sufficient capacity and a minimum area. The storage capacitor of a pixel region has such a structure that a first storage capacitor and a second storage capacitor are stacked one on top of the other and are connected in parallel with each other. At that time, the first storage capacitor comprises a first capacitance electrode formed in the same layer as a drain region, a first dielectric, and a second capacitance electrode formed in the same layer as a gate wiring. The second storage capacitor comprises the second capacitance electrode, a second dielectric, and a third capacitance electrode formed in the same layer as a light-shielding film.

Abstract: A semiconductor device includes a silicon layer. The silicon layer includes a lower silicon layer and an upper silicon layer which is formed on the lower layer. A concentration of impurities in the upper silicon layer is higher than that of the lower silicon layer.

Abstract: The present invention has the object of obtaining a display device with a sufficient storage property without degrading the aperture ratio when high definition is to be achieved for the display device. In the active matrix display device, a good storage property can be obtained without degrading the aperture ratio by disposing the storage element below the pixel TFT area as shown in FIG. 3. Moreover, even when the area of the capacitor element is reduced, a sufficient amount of the capacitor can be obtained by laminating a plurality of capacitor elements.

Abstract: A unique electrochemical process fills oxygen vacancies in dielectrics while reducing oxidation of nearby electrodes and conductors. Preferably, an electromagnetic field or bias is applied to a dielectric. The bias causes oxygen vacancies in the dielectric to migrate to the surface of the dielectric. As the oxygen vacancies migrate toward the surface, oxygen ions fill the oxygen vacancies. In one embodiment, a unique plasma treatment provides the oxygen ions that react with the oxygen vacancies. In another embodiment, a unique electrolysis treatment provides the oxygen ions that react with the oxygen vacancies.

Abstract: The invention encompasses a method of forming a dielectric material. A nitrogen-comprising layer is formed on at least some of the surface of a rugged polysilicon substrate to form a first portion of a dielectric material. After the nitrogen-comprising layer is formed, at least some of the substrate is subjected to dry oxidation with one or both of NO and N2O to form a second portion of the dielectric material. The invention also encompasses a method of forming a capacitor. A layer of rugged silicon is formed over a substrate, and a nitrogen-comprising layer is formed on the layer of rugged silicon. Some of the rugged silicon is exposed through the nitrogen-comprising layer. After the nitrogen-comprising layer is formed, at least some of the exposed rugged silicon is subjected to dry oxidation conditions with one or both of NO and N2O. Subsequently, a conductive material layer is formed over the nitrogen-comprising layer. Additionally, the invention encompasses a capacitor structure.

Abstract: A process is described for semiconductor device integration at chip level or wafer level, in which vertical connections are formed through a substrate. A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.

Abstract: By using a solid solution of tantalum pentoxide and niobium pentoxide as a dielectric film installed between upper electrode and lower electrode in a capacitor which is used in a semiconductor device, the capacitor structure can be simplified to improve reliability of the semiconductor device while reducing the production cost thereof.

Abstract: A method of fabricating a thin film transistor substrate for an X-ray detector reduces the number of steps in etching processes using masks. In the method, a gate line, a gate pad and a gate electrode of a thin film transistor are simultaneously formed on a certain substrate. A gate insulating layer is entirely coated, and then a semiconductor layer of the thin film transistor is formed. A data pad, a data line, source and drain electrodes of the thin film transistor and a ground electrode are simultaneously formed. An electrode for a charging capacitor is formed, and then an insulating film for the charging capacitor is formed. An electrode for preventing an etching of the insulating film for the charging capacitor is formed. A protective film for protecting the thin film transistor is formed. Contact holes are formed in the protective film. Finally, a pixel electrode is provided.

Abstract: According to the present invention, contact plugs are formed by a CVD method without deteriorating the properties of the ferroelectric capacitor in a semiconductor device having a fine ferroelectric capacitor. Adhesive film is formed in a contact hole, which exposes an upper electrode of the ferroelectric capacitor after conducting heat treatment in an oxidizing atmosphere, and a W layer is deposited by the CVD method using such TiN adhesive film as a hydrogen barrier and the contact hole is filled.

Abstract: A flat panel display device comprising a thin film semiconductor switching element formed on a surface of a substrate, a display electrode connected with the switching element, a semiconductor layer for auxiliary capacity which is electrically connected with the display electrode, a dielectric layer formed on a surface of the semiconductor layer for auxiliary capacity, and a metal layer formed on a surface of the dielectric layer, wherein the auxiliary capacity is constituted by the semiconductor layer for auxiliary capacity, the dielectric layer, and the metal layer, and the semiconductor layer for auxiliary capacity is implanted all over the surface thereof with a high concentration of impurity ion.

Abstract: When a driving unit (100) charges gate input capacitance (6) of an IGBT (7), the gate input capacitance (6) accumulates electric charges which are accumulated therein when the driving unit (100) discharges the gate input capacitance (6). Therefore, it is possible to reduce the amount of electric charges to be supplied to the gate input capacitance (6) by the driving unit (100) until the charge of the gate input capacitance (6) is completed. As a result, it is possible to reduce the required power capacity of a control power supply (15a). Further, since the electric charges accumulated in the gate input capacitance (6) are effectively used, it is possible to ensure power savings of a semiconductor device.

Abstract: A test signal generating circuit generates internal test control signals from a small number of signals supplied via an address terminal in a test mode operation. According to the test control signals, the values of internal row address signal bits from an address buffer are set, while a row-related control circuit with test control function controls operations of a row selection circuit and bit line peripheral circuitry according to the test control signals. A plurality of word lines are driven simultaneously into a selected state and an acceleration test is performed according to a small number of control signals in a short period of time. Voltage stress applied between memory cell capacitors and between word lines can be accelerated with a small number of control signals.

Abstract: The invention provides a method for fabricating bitlines, including the following steps: providing a semiconductor substrate having a contact opening, which opening exposed a diffusion region in the substrate or a polysilicon layer of a wordline; forming a polysilicon layer to cover the opening and contacting the exposed surface of the diffusion region or the polysilicon layer of the wordline; forming a tungsten silicide layer to cover the polysilicon layer; performing a ion implantation step with high energy and high dosage to damage a contact surface between the bitline and the wordline or a contact surface between the bitline and the diffusion region; forming a better contact surface between the bitline and the wordline or a better contact surface between the bitline and the diffusion region using thermal annealing in the subsequent steps, thereby reducing contact resistance between the bitline and the wordline or between the bitline and the diffusion region.

Abstract: A DRAM device having improved charge storage capabilities and methods for providing the same. The device includes an array portion having a plurality of memory cells extending from a semiconductor substrate. Each cell includes a storage element for storing a quantity of charge indicative of the state of the memory cell and a valve element that inhibits the quantity of charge from changing during quiescent periods. The storage elements are disposed adjacent a plurality of storage regions of the substrate and the valve elements are disposed adjacent a plurality of valve regions of the substrate. A plurality of dopant atoms are selectively implanted into the array portion so as to increase a threshold voltage which is required to develop a conducting channel through the valve region. The dopant atoms are disposed mainly throughout the valve regions of the substrate and are substantially absent from the storage regions.

Abstract: A semiconductor memory device of the present invention includes: a semiconductor substrate; a memory cell capacitor for storing data, including a first electrode provided above the semiconductor substrate, a capacitance insulating film formed on the first electrode, and a second electrode provided on the capacitance insulating film; a step reducing film covering an upper surface and a side surface of the memory cell capacitor; and an overlying hydrogen barrier film covering the step reducing film.

Abstract: A semiconductor memory device is provided which prevents a lifting phenomenon by improving an adhesive strength between an upper electrode and an interlayer insulating layer. The semiconductor memory device includes a capacitor formed on a semiconductor substrate, wherein the capacitor includes a lower electrode, a dielectric layer and an upper electrode; an adhesion layer formed on the upper electrode; an interlayer insulating layer covering the capacitor, wherein a portion of the interlayer insulating layer is in contact with the adhesion layer; and a contact hole, formed within the interlayer insulating layer, whose bottom exposes the upper electrode and whose sidewalls expose the interlayer insulating layer and the adhesion layer.

Abstract: Method and structure effective for reducing quiescent current drain using a semiconductor structure including a monocrystalline silicon substrate and a plurality of capacitors formed with a monocrystalline perovskite oxide material comprised of a high-k dielectric material, and a monocrystalline compound semiconductor layer including a plurality of logic elements having respective output gates, wherein the logic elements are coupled via their respective output gates to different ones of the capacitors, such that the logic elements use the oxide film as a capacitive storage element.

Abstract: A structure and a manufacturing method of a semiconductor device composed of 1T1Cs, in which a surface area of a memory cell capacitor part is expanded by forming an uneven surface at the memory cell capacitor part, is provided. Further, an additional photo lithography process is not required at expanding the surface area, and the manufacturing efficiency is not decreased. At the manufacturing method of the semiconductor device, two kinds of spaces whose sizes are different are formed in a conductive layer by that a part of a first oxide film and a part of the conductive layer to its middle part are removed. After this, a second oxide film is formed on the whole surface so that a small space of the spaces is filled with the second oxide film and side walls are formed on the side surfaces of a large space by applying etching back. With this, an exposed part of the conductive layer is formed selectively, and this exposed part of the conductive layer is removed by the etching.

Abstract: Storage node plugs are formed on a semiconductor substrate. A silicon nitride film is formed on a silicon oxide film. By etching the silicon oxide film with the silicon nitride film as a mask, storage node openings each exposing a surface of a corresponding storage node plug are formed, followed by forming a capacitor including a storage node, a capacitor dielectric film and a cell plate in a corresponding opening. With such a procedure, there can be obtained a semiconductor device in which electric short-circuit between adjacent elements is prevented from occurring; and a manufacturing method of such a semiconductor device.

Abstract: A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.