Abstract: A semiconductor apparatus which allows for an increase in the surface area of a lower electrode constituting a concave capacitor, and is capable of increasing the capacitance of an MIM structure, and a method of making such a semiconductor apparatus are provided. On a sidewall section of an amorphous silicon, an HSG silicon is selectively formed. A lower electrode is formed by the AL-CVD method in a thickness of 10 nm so as to cover the HSG silicon. Subsequently, a dielectric film is formed such that it covers the lower electrode and a cylinder core layer. Finally, a cell plate which is to constitute an upper electrode is formed on the dielectric film, and a capacitor is thereby completed.

Abstract: The present invention teaches novel electrically programmable read only memory (EPROM) devices for embedded applications. EPROM devices of the present invention utilize existing circuit elements without complicating existing manufacture technologies. They can be manufactured by dynamic random access memory (DRAM) technologies, standard logic technologies, or any type of IC manufacture technologies. Unlike conventional EPROM devices, these novel devices do not require high voltage circuits to support their programming operation. EPROM devices of the present invention are ideal for embedded applications. Typical applications including the redundancy circuits for DRAM, the programmable firmware for logic products, and the security identification circuits for IC products.

Abstract: A semiconductor memory cell has a deep trench capacitor and a vertical transistor formed over the deep trench capacitor. The vertical transistor has a control gate electrode, a source/drain region at opposite sides of the control gate electrode, and a channel region surrounding the sidewall and top of the control gate electrode. This can increase the length of the channel region to reduce leakage current.

Abstract: A substrate device has, on a substrate, a first conductive film, a first insulating film formed thereon, a second insulating film bonded thereon, and a second conductive film formed thereon. A contact hole connecting the first and second conductive films is opened so as to penetrate through a bonding interface thereof. The area of the contact hole penetrating through the bonding interface is not eroded by an etching solution. Thus, where manufacturing a substrate device in which a contact hole penetrating through a bonding interface needs to be formed, it is unlikely that a defect will occur in the area where the contact hole passing through the bonding interface, thereby enhancing device reliability and manufacturing yield.

Abstract: The invention relates to a memory cell that has a trench. A trench capacitor is configured in the trench. In addition, a vertical transistor is formed in the trench, above the trench capacitor. To connect the gate material of the vertical transistor to a word line, a dielectric layer (12) having an internal opening (13) is provided in the trench (3) above the gate material (23). The dielectric layer is in the form of a dielectric ring. The dielectric ring allows self-aligned connection of the word line to the gate material of the vertical transistor.

Abstract: A semiconductor processing method of forming dynamic random access memory circuitry includes, a) providing an electrically conductive capacitor cell plate substrate; b) providing an electrically insulative layer over the cell plate; c) providing a layer of semiconductive material on the insulative layer thereby defining a semiconductor-on-insulator (SOI) layer; d) patterning and etching the SOI layer to define active area region islands and isolation trenches between the islands; e) filling the isolation trenches with insulative material; f) providing capacitor openings through the SOI layer and insulative layer into the cell plate substrate; g) providing a capacitor dielectric layer over the cell plate substrate within the capacitor openings; h) providing respective capacitor storage nodes over the dielectric layer within the capacitor openings, the respective storage nodes being in ohmic connection with the SOI layer; i) after providing the storage nodes, filling any remaining portions of the capacitor cont

Abstract: A non-volatile memory device and a manufacturing method thereof are disclosed. The non-volatile memory device includes a gate insulating film formed on a semiconductor substrate, a floating gate formed on the gate insulating film, a dielectric film comprising a (TaO)1−x(TiO)xN film on the floating gate, and a control gate formed on the dielectric film. Thus, large charge capacitance values can be obtained compared to a similarly sized device using an ONO or Ta2O5 thin film dielectric while simultaneously simplifying the manufacturing process.

Abstract: The present invention provides a method for manufacturing a plurality of buried metal lines on a semiconductor substrate. The method comprises the steps as below. A dielectric layer is formed on a semiconductor substrate. And a plurality of insulator blocks are formed on the dielectric layer, wherein each the insulator block has a width of 3 unit (3×), and each gap between two adjacent the insulator blocks has a width of 5 unit (5×). First sidewall spacers are formed on sidewalls of the insulator blocks, wherein each the first sidewall spacer has a width of 1 unit (1×). Then the plurality of the insulator blocks are removed, and second sidewall spacers are defined on sidewalls of the first sidewall spacers, wherein each the second sidewall spacer has a width of 1 unit (1×). Next studs are formed into gaps between two adjacent the second sidewall spacers, wherein each the stud has a width of 1 unit (1×). And the second sidewall spacers are removed.

Abstract: To provide a semiconductor device having a large aperture ratio, in which an auxiliary capacitance of a large capacity is provided in each pixel.

Abstract: A stacked capacitor which comprises: a dielectric layer; a two-dimensional array of terminal electrodes on at least one of first and second surfaces of the dielectric layer; first internal electrodes stacked in multi-levels in the dielectric layer, and the first internal electrodes being electrically connected to a power line second internal electrodes stacked in multi-levels in the dielectric layer, and the second internal electrodes being electrically connected to a ground line; vias in the dielectric layer, so that the terminal electrodes being electrically connected through the vias to the first and second internal electrodes.

Abstract: A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.

Abstract: A semiconductor device with a semiconductor body (1) provided with a memory capacitor (12, 26) with a lower electrode (11, 23) consisting of a layer of semiconductor material (7, 23) having a rough surface (8, 24) formed by hemispherical grains (9, 25) of the relevant semiconductor material on which a dielectric layer (12, 27) and an upper electrode (13, 28) are provided. The semiconductor material from which the lower electrode is manufactured is Si1−xGex, wherein 0.2<x<1. The semiconductor device can be manufactured in a simple manner because a layer of Si1−xGex having a rough surface formed by hemispherical grains of this material can be simply directly formed through deposition by means of usual CVD (Chemical Vapor Deposition) processes.

Abstract: A semiconductor memory is provided with a memory cell region and a peripheral circuit region. The memory cell region includes semiconductor memory cells arranged in an array and element separating shield electrodes. The element separating shield electrodes extend in a column direction and separate semiconductor memory cells being adjacent to each other in a row direction. Further, a peripheral circuit sending and receiving data to and from the semiconductor memory cell is provided in the peripheral circuit region. Elements in the peripheral circuit are separated by an element separation insulating film. The element separating shield electrodes extend onto the element separation insulating film at a boundary between the memory cell region and the peripheral circuit region.

Abstract: A switched variable capacitor (20), and binary-weighted array (40) of such capacitors (20), are disclosed. The switched variable capacitor (20) includes a switching transistor (14) connected in series with first and second capacitors (12), between the two terminals (A,B). Bias transistors (18) are provided, and of opposite conductivity type as the switching transistor (14) but with their gates connected to the gate of the switching transistor (14). The bias transistors (18), when on, apply a reverse bias voltage to the source/drain regions of the switching transistor (14), to minimize the parasitic junction capacitance, and thus improve the temperature stability of the capacitor (20). A binary-weighted array (40) of switched variable capacitors (20) is also disclosed, as is a voltage-controlled oscillator (50) incorporating such an array (40).

Abstract: A photoelectric conversion device has a non-single-crystal semiconductor laminate member formed on a substrate having a conductive surface, and a conductive layer formed on the non-single-crystal semiconductor laminate member. The non-single-crystal semiconductor laminate member has such a structure that a first non-single-crystal semiconductor layer having a P or N first conductivity type, an I-type second non-single-crystal semiconductor layer and a third non-single-crystal semiconductor layer having a second conductivity type opposite the first conductivity type are laminated in this order. The first (or third) non-single-crystal semiconductor layer is disposed on the side on which light is incident, and is P-type. The I-type non-single-crystal semiconductor layer has introduced thereinto a P-type impurity, such as boron which is distributed so that its concentration decreases towards the third (or first) non-single-crystal semiconductor layer in the thickwise direction of the I-type layer.

Abstract: A capacitor and a method of manufacturing the same are disclosed. The BST dielectric film is disposed between the lower electrode by coating a sidewall of the upper electrode and then forming the lower electrode in a second contact hole defined by the upper electrode and BST film. As such, degradation in the step coverage characteristic caused by forming a BST dielectric film having a desired composition ratio is avoided.

Abstract: A capacitive element structure in a semiconductor device having an interconnection structure. The capacitive element structure includes a capacitive element having a capacitive dielectric film made of an oxide compound. The capacitive element structure is above at least a bottom level interconnection of the interconnection structure.

Abstract: A container capacitor having a recessed conductive layer. The recessed conductive layer is typically made of polysilicon. The recessed structure reduces the chances of polysilicon “floaters,” which are traces of polysilicon that remain on the surface of the substrate, coupling adjacent capacitors together to create short circuits. The disclosed method of creating such a recessed structure uses successive etches. One of these etches selectively isolates a rim of the polysilicon within the container to recess the rim, while the remainder of the polysilicon in the container is protected by photoresist.

Abstract: A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.

Abstract: An SRAM cell and method for fabricating the same including first and second access transistors, first and second drive transistors, and first and second load resistors. A first terminal of the first access transistor, a gate terminal of the second drive transistor, and a first load resistor terminal are connected to one another to form a first cell node terminal. A first terminal of the second access transistor, a gate terminal of the first drive transistor, and a second load resistor terminal are connected to one another to form a second cell node terminal. The SRAM cell includes a gate electrode of each of the first and second drive transistors arranged over a semiconductor substrate in a first direction, and a gate electrode of each of the first and second access transistors arranged in the first direction overlapped with portions of the gate electrodes of the first and second drive transistors.

Abstract: A device for capacitor characteristic evaluation is provided, which enables measurement of the characteristic of a capacitor immediately after the completion of its formation processes, and which improves the fabrication yield.

Abstract: A thin film transistor includes: an insulating substrate; a semiconductor layer of a polycrystalline silicon formed on the insulating substrate; a gate insulator film formed so as to contact the semiconductor layer; a gate electrode formed so as to contact the gate insulator film; an active layer formed in a region of the semiconductor layer corresponding to the gate electrode; a first semiconductor region which is formed in the semiconductor layer outside of the active layer and which has an impurity concentration of higher than or equal to 1×1018 cm−3 and lower than 1×1020 cm−3; and a second semiconductor region which is formed in the semiconductor layer outside of the first semiconductor region and which has an impurity concentration of higher than that of the first semiconductor region, the second semiconductor region having the same conductive type as that of the first semiconductor region. Thus, it is possible to obtain a reliable thin film transistor having small OFF current.

Abstract: A semiconductor device with a semiconductor body (1) provided with a memory capacitor (12, 26) with a lower electrode (11, 23) consisting of a layer of semiconductor material (7, 23) having a rough surface (8, 24) formed by hemispherical grains (9, 25) of the relevant semiconductor material on which a dielectric layer (12, 27) and an upper electrode (13, 28) are provided. The semiconductor material from which the lower electrode is manufactured is Si1-xGex, wherein 0.2<x<1. The semiconductor device can be manufactured in a simple manner because a layer of Si1-xGex having a rough surface formed by hemispherical grains of this material can be simply directly formed through deposition by means of usual CVD (Chemical Vapor Deposition) processes.

Abstract: A dynamic random access memory. The memory includes a write transistor N3 and a read transistor N2. In a preferred embodiment the write transistor has a threshold level higher than the read transistor. A sense amplifier senses and amplifies a difference in voltage between a bit line and a sense node that is developed when the read transistor permits or does not permit current to flow between ground an a bit line. Associated semiconductor device structures and fabrication techniques are also disclosed.

Abstract: A method for annealing amorphous silicon film to produce polycrystalline film suitable for thin-film transistors fabricated on glass substrates is provided. The method involves using the selective location of nickel on a predetermined region of silicon to define the pattern of the lateral growth front as the silicon is crystallized. The method defines the resistivity of the silicide formed. The method also defines a specific range of nickel thicknesses to form the nickel silicide. A minimum thickness ensures that a continuous layer of nickel silicide exists on the growth front to promote an isotropic lateral growth front to form a crystalline film having high electron mobility. A maximum thickness limit reduces the risk of nickel silicide enclaves in the crystalline film to degrade the leakage current. Strategic placement of the nickel helps prevent nickel silicide contamination of the transistor channel regions, which degrade the leakage current.

Abstract: A data processing system having a DRAM and a non-volatile memory, such as a ROM or a programmable ROM (PROM), is implemented on a single integrated circuit using DRAM data processing techniques. The DRAM is manufactured in accordance with known processing techniques. The non-volatile memory is manufactured using the same DRAM manufacturing techniques, with the addition of a processing step in which a first terminal of a stacked capacitor manufactured in accordance with the DRAM process, is coupled to a known-reference voltage. This stacked capacitor structure may be coupled to a known conductor through the formation of a via and the subsequent coupling of a conductor to the stacked capacitor structure through the via. Alternatively, the stacked capacitor structure may be coupled to the known reference voltage through an internal connection to that reference voltage.

Abstract: A trench capacitor structure suitable for use in a semiconductor integrated circuit device and the process sequence used to form the structure. The trench capacitor provides increased capacitance by including a capacitor plate consisting of textured, hemispherical-grained silicon. The trench capacitor also includes a buried plate to reduce depletion of stored charge from the capacitor.

Abstract: An improved method for fabricating DRAM with a thin film transistor can increase reading and writing speed. In this method, a substrate with a transfer transistor, a word line, a bit line and an interlayer dielectric layer is provided. A bit line contact and a terminal contact are formed in the interlayer dielectric layer. The bit line contact couples to the bit line and the terminal contact couples to the transfer transistor. The terminal contact is a T-shaped structure. An oxide layer is formed to cover the interlayer dielectric layer and the terminal contact to expose the bit line contact. A polysilicon layer is formed to cover the oxide layer and the bit line contact. An ion implantation step is performed to form a first doped region and a second doped region in the polysilicon layer. The polysilicon layer is patterned to make the first doped region into a source region and to make the second doped region into a drain region.

Abstract: A trench capacitor having a diffusion region adjacent to the collar to increase the gate threshold voltage of the parasitic MOSFET. This enables the use of a thinner collar while still achieving a leakage that is acceptable. In one embodiment, the diffusion region is self-aligned.

Abstract: A fully recessed device structure and method for low power applications comprises a trenched floating gate, a trenched control gate and a single wrap around buried drain region. The trenched floating gate and the trenched control gate are formed in a single trench etched into a well junction region in a semiconductor substrate to provide a substantially planar topography. The fully recessed structure further comprises a buried source region, and a buried drain region that are each formed in the well junction region laterally separated by the trench. The upper boundaries of the buried source region and the buried drain region are of approximately the same depth as the top surface of the trenched floating gate.

Abstract: A semiconductor device includes a gate electrode (4) formed of a conductive material on a semiconductor substrate (1) of one conductivity type with a gate insulating film (3) therebetween; first and second diffusion regions (5, 10) of another conductivity type formed on the semiconductor substrate (1) so as to sandwich the gate electrode (4); and a contact hole (17) for electrically connecting one (first) (10) of the first and second diffusion regions (5, 10) to a lower electrode (8) of a cell capacitor for storing charge therein, and has a characteristic that when a reverse voltage Vrev is applied as a junction application voltage between semiconductors of different conductivity types of the first diffusion region (10) and the semiconductor substrate (1) (positive potential is applied to the n-type semiconductor side and zero or negative potential, to the p-type semiconductor side), a leakage current Ileak flows between the first diffusion region (10) and the semiconductor substrate (1), and the junction app

Abstract: A semiconductor device includes a substrate having an insulating film on its surface, and an active layer made of a semiconductive thin film on the substrate surface. The thin film contains a mono-domain region formed of multiple columnar and/or needle-like crystals parallel to the substrate surface without including crystal boundaries therein, allowing the active layer to consist of the mono-domain region only. The insulating film underlying the active layer has a specific surface configuration of an intended pattern in profile, including projections or recesses. To fabricate the active layer, form a silicon oxide film by sputtering on the substrate. Pattern the silicon oxide film providing the surface configuration. Form an amorphous silicon film by low pressure CVD on the silicon oxide film. Retain in the silicon oxide film and/or the amorphous silicon film certain metallic element for acceleration of crystallization.

Abstract: In a stack type memory cell of 8F.sup.2, bit line plug electrodes for connecting bit lines to source/drain diffusion layers of active regions in an area between two word lines WL are formed extend from the source/drain diffusion layers in parallel to the word lines WL and formed longer than the minimum element isolation width F and shorter than three times the minimum element isolation width F. Thus, a DRAM which uses stack type memory cells and whose integration density can be easily enhanced can be attained.

Abstract: A semiconductor dynamic random access memory device has a switching transistor fabricated on a first area of a silicon substrate, another switching transistor fabricated on a second area of the silicon substrate and forming a part of a peripheral circuit, a first inter-level insulating structure covering the first and second switching transistors, a bit line formed on the first inter-level insulating structure and electrically connected to the drain region of the first switching transistor, a signal wiring layer formed on the first inter-level insulating structure and electrically connected to the drain region of the second switching transistor, a second inter-level insulating layer covering the bit line and the signal wiring layer and a storage capacitor formed on the second inter-level insulating layer and electrically connected to the drain region of the second switching transistor; parasitic capacitance is the major factor for the signal propagating speed along the bit line, and resistance is the major fa

Abstract: An integrated circuit transistor and a method for making the same are provided. The transistor is resistant to junction shorts due to the overetch of local interconnect trenches. The transistor includes a source/drain region with a first junction and a second junction that is located deeper than the first junction in the portion of the active area susceptible to the overetch junction short phenomena. The second junction is established by ion implantation through a mask that is patterned to create an opening corresponding to the intersection of the layouts of the active area and the local interconnect trench. Using this method, the second junction is only established where needed to prevent shorting and does not impede transistor performance.

Abstract: A structure for forming an ohmic contact to the drain of a MOSFET in a stacked capacitor DRAM cell is described. The contact is formed by making an opening in the upper cell plate of the cells capacitor and contacting the storage plate through this opening with a conductive plug, preferably a tungsten plug. The plug is formed concurrent with the conventional contact and first metal wiring processing of the DRAM. The contact is used in DRAM test arrays for characterizing the quality of MOSFET gate insulator as well as the performance characteristics of the MOSFET itself. Connection to the conductive plug is made with first metal wiring. The test structures can be built at any position within the array and since they are located above the polysilicon bitline/wordline structure, the metal connection lines for the contacts do not interfere with the structure of the test array itself other than the sacrifice of the test cell from the array.

Abstract: A structure and fabrication method for a thin film transistor suitable for a SRAM memory cell. The thin film transistor structure includes a gate electrode formed to have a groove, a gate insulation film formed on the gate electrode, a semiconductor layer formed in the groove of the gate electrode, and impurity regions formed on opposite sides of the semiconductor layer. The method for fabricating the thin film transistor includes forming a gate electrode and a gate insulation film successively on an insulating substrate so as to have a groove, forming a semiconductor layer on the gate insulation film at a part of the groove, and forming source/drain impurity regions by selective injection of impurity ions into opposite sides of the semiconductor layer.

Abstract: An isolation structure providing electrical isolation in two dimensions between memory cells in semiconductor memory devices. The isolation structure comprises a trench formed in a substrate of a semiconductor memory device such as a Dynamic Random Access Memory (DRAM). The trench is lined with an insulating material and filled with polysilicon to form a floating gate. An electrical charge is then injected into the polysilicon floating gate. The isolation structure is located between memory cells in an array to provide isolation between cells in sub-micron spacing by combining the characteristics of trench and field isolation. The electrical charge is injected into the polysilicon floating gate by applying a charging voltage to the wordlines of the memory cell array. The charging voltage is applied periodically as necessary to maintain effective isolation. Two dimensional isolation is achieved by extending the trench to surround each pair of memory cells sharing a common bitline contact.

Abstract: In an open-bit-line type COB structure DRAM, two adjacent rectangular device formation regions included in two different but adjacent rectangular device formation region arrays, respectively, are staggered in a bit line direction along the long side of each rectangular device formation region by one third (2 F) of a pitch (6 F) of the rectangular device formation region in the bit line direction. Two local interconnections connected through local contact holes to source/drain diffused layers formed in opposite end portions of each rectangular device formation region, are provided in parallel to a word line. Bit lines each connected through a bit contact hole to a source/drain diffused layer formed in a center portion of each rectangular device formation region, are located with a pitch of 2 F. A capacitor formed at a level higher than that of the bit line is connected through a capacitor contact hole to an end positioned above a field oxide film, of a corresponding local interconnection.

Abstract: A storage capacitor for use in a liquid crystal display and a method of manufacturing the capacitor are disclosed. The storage capacitor includes a first electrode on a substrate. Then, a first insulating layer is formed over the first electrode. The capacitor also includes a second insulating layer immediately over the first insulating layer. The second insulating layer is formed to have a recess above the first electrode. This recess may extend through the second insulating layer as to expose the first insulating layer. The capacitor further includes a second electrode over the second insulating layer including the recess.

Abstract: A method for forming a contact opening is described and which includes providing a node location to which electrical connection is to be made; forming a conductive line adjacent the node location, the conductive line having a conductive top and sidewall surfaces; forming electrically insulative oxide in covering relation relative to the top surface of the conductive line; forming electrically insulative nitride sidewall spacers over the conductive sidewall surfaces, the nitride sidewall spacers projecting outwardly of the conductive line top conductive surface, the electrically insulative oxide positioned between the nitride sidewall spacers; forming an electrically insulative layer outwardly of the conductive line, and the node location; and etching a contact opening to the node location or the top surface through the electrically insulative layer substantially selective relative to the nitride sidewall spacers.

Abstract: Disclosed herein is a semiconductor memory device including a plurality of memory cells each includes an active region which is defined in a column direction by a pair of trench isolation regions formed in a semiconductor substrate and in a row direction by an isolation gate conductor lines formed on a first gate insulating film covering the substrate, a source and a drain region selectively formed in the active region to define a channel region of a cell transistor, a second gate insulating film formed on the channel region, a word line formed on the second gate insulating film, a first insulating film covering the active region and the word line, a bit line formed on the first insulating film to overlap with the isolation gate conductor, a bit line connection conductor formed in the first insulating film to connect the drain region to the bit line with being in contact with the sidewall surface of the bit line, a second insulating film covering the bit line and the first insulating film, and a storage capac

Abstract: A method of fabricating an integrated circuit with trenches, without parasitic edge transistors, for isolating FET transistors from each other without degrading the FETs operating characteristics by junction leakage, breakdown or shorting when a metal silicide is used in the source/drain regions. A silicon wafer, is formed with a gate electrode material on a gate insulating layer before forming the trenches for isolation. Now, with an etch protective layer on the gate electrode, trenches are etched and filled with an insulating material in the gate electrode material, the gate insulating layer and the silicon wafer to isolate the active regions. After the gate electrode material is etched to define the gate electrodes, the tops of gate electrodes are in essentially the same plane as the tops of the trenches. Preferably in the fabrication process, sidewalls are formed on the walls of the trenches and the gate electrodes.

Abstract: Method and apparatus for reducing current leakage between overlapping conductive structures in a multi-layered integrated circuit device such as a thin film capacitor is described. A conductive structure operating as a raised lower electrode is preferably fashioned by step-like erosion using a photolithographic techniques atop a dielectric substrate. In accordance with this invention, the dielectric substrate itself is allowed to erode as well to space the conductive structure away from the problemmatic inner corners of the step. By so distancing such conductive structures, like electrodes, from these inside corners, even conventional deposition techniques can be used to fabricate a capacitive device of operational tolerance suitable for DRAM application without risk of unwanted electrode current leakage and possible shorting.

Abstract: A large-area electronic device such as, e.g, a large-area image sensor or flat panel display comprises thin-film drive circuitry including inverters each comprising a driver TFT (M1), a load TFT (M2) and a bootstrap capacitor (C.sub.s). Most TFT types which may be used to fabricate the transistors (M1 and M2) have a high parasitic gate capacitance due, inter alia, to overlap of the gate electrode (g) with their source and drain electrodes (21 and 22). This parasitic capacitance degrades the inverter gain Av by coupling between the output line (O/P) of the inverter and the gate electrode (g) of its load device (M2) and an excessively large capacitor (C.sub.s) is required to overcome this degradation. The present invention uses a reduction in the transconductance (gm2) of the load TFT (M2) to permit a reduction in the size of the boot strapping capacitor (C.sub.s) to within practical limits, while still obtaining a desirably high gain Av from the inverter in spite of the parasitic capacitances. A factor .mu..

Abstract: A semiconductor device and fabrication process wherein the device includes a conductive layer with a localized thick region positioned below the contact hole. In one embodiment of the invention, the thick region to which contact is made is formed by means of an opening in an underlayer of material. This embodiment of the device includes an underlayer of material having an opening therein; a layer of thin conductive material formed on the underlayer and in the opening; an overlayer of material having a contact hole therethrough formed on the layer of thin conductive material; a conductor contacting the layer of thin conductive material through the contact hole; and wherein the opening in the underlayer is positioned below the contact hole and sized and shaped to form a localized thick region in the layer of thin conductive material within the opening.

Abstract: An isolation structure providing electrical isolation in two dimensions between memory cells in semiconductor memory devices. The isolation structure comprises a trench formed in a substrate of a semiconductor memory device such as a Dynamic Random Access Memory (DRAM). The trench is lined with an insulating material and filled with polysilicon to form a floating gate. An electrical charge is then injected into the polysilicon floating gate. The isolation structure is located between memory cells in an array to provide isolation between cells in sub-micron spacing by combining the characteristics of trench and field isolation. The electrical charge is injected into the polysilicon floating gate by applying a charging voltage to the wordlines of the memory cell array. The charging voltage is applied periodically as necessary to maintain effective isolation. Two dimensional isolation is achieved by extending the trench to surround each pair of memory cells sharing a common bitline contact.

Abstract: A semiconductor memory device includes a trench formed in a semiconductor substrate. Conductive material is formed in the trench and is insulatively spaced from the semiconductor substrate to form a capacitor. A transfer gate transistor includes source/drain regions formed on a surface of the semiconductor substrate and a control gate which is insulatively spaced from a channel region between the source and drain regions. A buried strap electrically connects the capacitor to one of the source/drain regions of the transfer gate transistor. A portion of the buried strap includes recrystallized silicon.

Abstract: A method for fabricating a dynamic random access memory comprises the steps of forming a diffusion region in a semiconductor substrate, providing an insulation layer on the semiconductor substrate, forming a contact hole in the insulation layer to expose the diffusion region at the contact hole, depositing a semiconductor layer on the insulation layer in the amorphous state such that the semiconductor layer establishes an intimate contact with the exposed diffusion region via the contact hole, patterning the semiconductor layer to form a capacitor electrode, depositing a dielectric film on the capacitor electrode such that said dielectric film covers the capacitor electrode; and depositing a semiconductor material to form an opposing electrode such that the opposing electrode buries the capacitor electrode underneath while establishing an intimate contact with the dielectric film that covers the capacitor electrode.

Abstract: Disclosed is a method of growing hemispherical grained silicon (HSG silicon) over a conductive seed layer. In a preferred embodiment, a contact window is etched in an insulating layer to expose a circuit node, such as an active area of a substrate or a contact plug leading to an active area. A layer of titanium nitride is deposited over the insulating layer and into the contact window. The titanium nitride (TiN) serves as the seed layer for HSG silicon growth to follow. Polysilicon is deposited and grows around nucleation sites on the TiN surface. The TiN provides both electrical and mechanical support for the HSG silicon. Additionally, as TiN is an effective diffusion barrier, the HSG silicon may be heavily doped without undue risk of dopant diffusion to the active area.