Field Effect Transistor In Single Crystal Material, Complementary To That In Non-single Crystal, Or Recrystallized, Material (e.g., Cmos) Patents (Class 257/69)
  • Patent number: 10483287
    Abstract: Transistors formed on semiconductor substrates are not well-suited for integrated circuits employed in media designed to structurally flex to conform to a shaped surface or in response to physical stress. Structural flexing of wearable electronic devices, such as clothing, may cause cracking in the semiconductor substrate, resulting in failure of the integrated circuits. TFTs formed on flexible substrates can withstand structural flexing without failure. CMOS circuits are employed due to cost, performance, and power efficiency considerations. To provide increased drive strength for such applications, a flexible TFT structure for a CMOS circuit disclosed herein includes an exemplary NFET integrated with a complementary PFET on a flexible substrate. By forming a top gate on a semiconductor layer of a FET opposite to a bottom gate formed between the semiconductor layer and the flexible substrate, an effective thickness of an inversion channel layer induced in the semiconductor layer is doubled.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: November 19, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Bin Yang, Gengming Tao
  • Patent number: 10390428
    Abstract: An electrical connection structure is provided in the present invention, which includes a substrate, a plurality of conductive textile layers disposed apart on the substrate, an electrical connection layer disposed on the conductive textile layers, a plurality conductive parts disposed on the electrical connection layer corresponding to the conductive textile layers respectively, an adhesive layer, and a protective layer, wherein the electrical connection layer provides the electrical connection between the conductive textile layers and the conductive parts corresponding to the conductive textile layers, and the conductive textile layers disposed apart from each other are not electrically connected.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: August 20, 2019
    Assignee: Far Eastern New Century Corporation
    Inventors: Yu-Chun Wu, Wei-Che Hung, Hsin-Kai Lai
  • Patent number: 10333007
    Abstract: A short-channel metal oxide semiconductor varactor may include a source region of a first polarity having a source via contact. The varactor may further include a drain region of the first polarity having a drain via contact. The varactor may further include a channel region of the first polarity between the source region and the drain region. The channel region may include a gate. The varactor may further include at least one self-aligned contact (SAC) on the gate and between the source via contact and the drain via contact.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: June 25, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Ye Lu, Yun Yue, Chuan-Hsing Chen, Bin Yang, Lixin Ge, Ken Liao
  • Patent number: 10304957
    Abstract: Selective epitaxial growth is used to form a hetero-structured source/drain region to fill an etched recess in a silicon fin for an n-type FinFET device.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: May 28, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Ukjin Roh, Shashank Ekbote
  • Patent number: 10298119
    Abstract: According to an embodiment, a circuit includes a protection voltage generator coupled to a first voltage node, a second voltage node, and a ground voltage node, the protection voltage generator configured to generate a plurality of protection voltages at a first plurality of nodes based on the first voltage node and the second voltage node, and a voltage protection ladder coupled between the first voltage node and a low voltage circuit, the voltage protection ladder coupled to the plurality of protection voltages at the first plurality of nodes, the voltage protection ladder configured to generate a first low voltage based on the first voltage node and the plurality of protection voltages.
    Type: Grant
    Filed: November 7, 2017
    Date of Patent: May 21, 2019
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Phalguni Bala, Hiten Advani
  • Patent number: 10056445
    Abstract: The present invention provides a manufacture method of an AMOLED pixel driving circuit. The method utilizes the oxide semiconductor thin film transistor to be the switch thin film transistor of the AMOLED pixel driving circuit to reduce the leakage current of the switch thin film transistor, and the P type polysilicon thin film transistor manufactured by utilizing the Solid Phase Crystallization is employed to be the drive thin film transistor of the AMOLED pixel driving circuit to promote the mobility, the equality and the reliability of the drive thin film transistor, and utilizing the P type thin film transistor to be the drive thin film transistor can form the constant current type OLED element, which is more stable than the source follower type OLED formed by the N type thin film transistor, and meanwhile, the parasitic capacitance is decreased with the top gate structure.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: August 21, 2018
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xingyu Zhou, Xiaoxing Zhang, Yuanjun Hsu, Yadi Zhang
  • Patent number: 10008386
    Abstract: Methods are provided to form pure silicon oxide layers on silicon-germanium (SiGe) layers, as well as an FET device having a pure silicon oxide interfacial layer of a metal gate structure formed on a SiGe channel layer of the FET device. For example, a method comprises growing a first silicon oxide layer on a surface of a SiGe layer using a first oxynitridation process, wherein the first silicon oxide layer comprises nitrogen. The first silicon oxide layer is removed, and a second silicon oxide layer is grown on the surface of the SiGe layer using a second oxynitridation process, which is substantially the same as the first oxynitridation process, wherein the second silicon oxide layer is substantially devoid of germanium oxide and nitrogen. For example, the first silicon oxide layer comprises a SiON layer and the second silicon oxide layer comprises a pure silicon dioxide layer.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: June 26, 2018
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Pouya Hashemi, Hemanth Jagannathan, Choonghyun Lee, Vijay Narayanan
  • Patent number: 9953997
    Abstract: Disclosed is a semiconductor memory device including stacks on a substrate, a vertical channel portion connected to the substrate through each of the stacks, and a separation pattern disposed between the stacks. Each of the stacks may include a plurality of gate electrodes stacked on the substrate and insulating patterns interposed between the gate electrodes. Each of the gate electrodes may include a first metal pattern, which is disposed between the insulating patterns to define a recess region recessed toward the vertical channel portion, and a second metal pattern disposed in the recess region. The first and second metal patterns may contain the same metallic material and may have mean grain sizes different from each other.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: April 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Joyoung Park, Hauk Han, Seok-Won Lee, Jeonggil Lee, Jinwoo Park, Kihyun Yoon, Hyunseok Lim, Jooyeon Ha
  • Patent number: 9911574
    Abstract: Provided among other things are a scanning electron microscope, scanning transmission electron microscope, focused ion beam microscope, ion beam micromachining device, or scanning probe nanofabrication device, wherein the microscope or device is configured to move a substrate and a scanning modality relative to one another with an enclosed sinusoidal trajectory, and methods of operation.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: March 6, 2018
    Assignee: The Trustees of Princeton University, Office of Technology and Trademark Licensing
    Inventors: Nan Yao, Wei Cai
  • Patent number: 9871215
    Abstract: A transistor manufacturing method includes: forming a first insulator layer of which formation material is a fluorine-containing resin, on a substrate having a source electrode, a drain electrode, and a semiconductor layer so as to cover the semiconductor layer; forming a second insulator layer to cover the first insulator layer; forming a base film on at least part of a surface of the second insulator layer; and after depositing a metal which is an electroless plating catalyst on a surface of the base film, forming a gate electrode on the surface of the base film by electroless plating, wherein the forming of the base film is performed by applying a liquid substance which is a formation material of the base film to the surface of the second insulator layer, and the second insulator layer has a higher lyophilic property with respect to the liquid substance than the first insulator layer.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: January 16, 2018
    Assignee: NIKON CORPORATION
    Inventors: Shohei Koizumi, Takashi Sugizaki, Yusuke Kawakami
  • Patent number: 9812578
    Abstract: A thin film transistor includes, an insulating substrate, a gate electrode provided on an upper surface of the insulating substrate, a gate insulating film formed so as to cover the gate electrode, an oxide semiconductor layer provided on the gate insulating film, a channel protective layer provided at least on an upper surface of the oxide semiconductor layer, and a source electrode and a drain electrode provided so as to come into contact with the oxide semiconductor layer, wherein the channel protective layer is formed such that the film density of a portion provided so as to come into contact with the oxide semiconductor layer is higher than the film density of a portion distant from the oxide semiconductor layer.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: November 7, 2017
    Assignee: Japan Display Inc.
    Inventors: Norihiro Uemura, Takeshi Noda, Hidekazu Miyake, Isao Suzumura
  • Patent number: 9711534
    Abstract: A device includes a substrate layer, a diamond layer, and a device layer. The device layer is patterned. The diamond layer is to conform to a pattern associated with the device layer.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: July 18, 2017
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Di Liang, Raymond G Beausoleil
  • Patent number: 9595592
    Abstract: A method for forming contact silicide for a semiconductor structure. In one embodiment, a dielectric layer is formed over a p-type region of a semiconductor structure comprising a gate stack and source and drain regions. The source and drain regions are formed within a semiconductor layer. First and second contact trenches are formed within the dielectric layer exposing at least a portion of the source region and a portion of the drain region, respectively. First and second metal layers are formed within the first and second contact trenches. The second metal layer includes a metallic material that is different from a metallic material of the first meal layer. The metallic materials of the first and second metal layers in a lower region of the first and second contact trenches are intermixed. A silicide is formed within the source and drain regions from the semiconductor layer and the intermixed metallic materials.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: March 14, 2017
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan Veera Venkata Satya Surisetty
  • Patent number: 9570409
    Abstract: A semiconductor device includes: a first interconnection line and a second interconnection line which extend apart from each other on a first plane at a first level on a substrate; a bypass interconnection line that extends on a second plane at a second level on the substrate; and a plurality of contact plugs for connecting the bypass interconnection line to the first interconnection line and the second interconnection line. A method includes forming a bypass interconnection line spaced apart from a substrate and forming on a same plane a plurality of interconnection lines connected to the bypass interconnection line via a plurality of contact plugs.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: February 14, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-min Park, Dae-ik Kim
  • Patent number: 9466672
    Abstract: A semiconductor stack includes a substrate; a first semiconductor layer disposed on the substrate; a tensile strained interlayer layer disposed on the first semiconductor layer; and a second semiconductor layer disposed on the strained interlayer; wherein the difference in strain between the first semiconductor layer and the tensile strained interlayer is about 1 to about 2%.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: October 11, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Keith E. Fogel, Pouya Hashemi, John A. Ott, Alexander Reznicek
  • Patent number: 9379254
    Abstract: This disclosure provides systems, methods and apparatus for fabricating thin film transistor (TFT) devices. In one aspect, a substrate having a source area, a drain area, and a channel area is provided. Metal cations are implanted in the oxide semiconductor layer overlying the source area and the drain area of the substrate. The metal cation implantation forms a doped n-type oxide semiconductor in the oxide semiconductor layer overlying the source area and the drain area of the substrate.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: June 28, 2016
    Assignee: QUALCOMM MEMS TECHNOLOGIES, INC.
    Inventors: Cheonhong Kim, Tallis Young Chang, John Hyunchul Hong
  • Patent number: 9299136
    Abstract: A metal element deformation state detection device is provided in which since a plurality of the metal elements are in line contact with each other via a rocking edge and are aligned in an arc shape to form a metal element row, a light source is disposed on the radially inner side or the radially outer side of the arc of the metal element row, and a deformation state of the metal element is detected by observing passed-through light that has been emitted from the light source and has passed through a gap between adjacent metal elements, slight deformation in the metal element can reliably be detected.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: March 29, 2016
    Assignee: HONDA MOTOR CO., LTD.
    Inventor: Shigeru Kanehara
  • Patent number: 9184251
    Abstract: A semiconductor device includes a substrate and a plurality of transistors arranged on the substrate in an array. The transistor includes a first electrode, a plurality of second electrodes, and a gate electrode. The second electrodes are arranged around the first electrode. The gate electrode is located between the first electrode and the second electrodes. The first electrode is a circle or polygon. The gate electrode is around the first electrode, and an edge of the gate electrode facing the first electrode has a shape corresponding to that of the first electrode.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: November 10, 2015
    Assignee: DELTA ELECTRONCIS, INC.
    Inventors: Li-Fan Lin, Hsuan-Wen Chen
  • Patent number: 9135390
    Abstract: To design a power supply network of a 3D semiconductor device employing through-silicon-via (TSV) technology, board wiring of each of boards of the device is determined. An initial network structure is created for the boards. A layout of power bumps and through-silicon-vias, using the initial network structure, is produced such that voltages of all nodes of wiring of the boards are greater than a reference voltage. A semiconductor device having boards, power bumps and through-silicon-vias conforming to the layout is fabricated. Thus, the numbers of the through-silicon-vias and the power bumps of the power supply network of the semiconductor device are minimal.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: September 15, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung-Soo Jang, Jae-Rim Lee, Jong-Wha Chong, Jae-Hwan Kim, Byung-Gyu Ahn, Cheol-Jon Jang
  • Patent number: 9117785
    Abstract: Provided is a display device, including a pixel electrode in each of a plurality of pixels; an auxiliary wiring part including a first auxiliary wiring having a first edge portion, and a second auxiliary wiring having a second edge portion spaced apart from and facing the first edge portion; an insulating layer on the pixel electrode and the auxiliary wiring part, and in which a first opening and a second opening are defined, the first opening overlapping the pixel electrode, and the second opening overlapping the first edge portion and the second edge portion; an organic light-emitting layer on the insulating layer and contacting the pixel electrode through the first opening; and an upper electrode on the organic light-emitting layer and having a connection portion electrically connected with the auxiliary wiring part through the second opening.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: August 25, 2015
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Mitsuhiro Kashiwabara, Toshiyuki Matsuura
  • Patent number: 9112037
    Abstract: A transistor including an oxide semiconductor and having favorable operation characteristics is provided. Further, by using the transistor, a semiconductor having improved operation characteristics can be provided. In planar view, one of a source electrode and a drain electrode of the transistor is surrounded by a ring-shaped gate electrode. Further, in planar view, one of the source electrode and the drain electrode of the transistor is surrounded by a channel formation region. Accordingly, the source electrode is not electrically connected to the drain electrode through a parasitic channel generated in an end portion of an island-shaped oxide semiconductor layer.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: August 18, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Atsuo Isobe, Yuki Hata, Suguru Hondo
  • Publication number: 20150102348
    Abstract: A method of forming a semiconductor structure that includes forming a first recess and a second recess between a first pair of sidewall spacers and a second pair of sidewall spacers respectively, the first and second pair of sidewall spacers surrounding a fin on top of a buried dielectric layer, the fin is formed from a top most semiconductor layer of a semiconductor-on-insulator substrate. A high-k dielectric layer is deposited within the first and second recesses and a dummy titanium nitride layer is deposited on the high-k dielectric layer. The high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess and a silicon cap layer is deposited within the first and second recesses. Next, dopants are implanted into the silicon cap layer in the second recess without implanting dopants into the silicon cap layer in the first recess to form a BJT device.
    Type: Application
    Filed: October 14, 2013
    Publication date: April 16, 2015
    Applicant: International Business Machines Corporation
    Inventors: Jin Cai, Effendi Leobandung, Tak H. Ning
  • Patent number: 8994026
    Abstract: Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventor: Steven H. Voldman
  • Patent number: 8981374
    Abstract: A semiconductor device having a high aperture ratio and including a capacitor capable of increasing the charge capacity is provided. A semiconductor device includes a transistor over a substrate, a first light-transmitting conductive film over the substrate, an oxide insulating film covering the transistor and having an opening over the first light-transmitting conductive film, a nitride insulating film over the oxide insulating film and in contact with the first light-transmitting conductive film in the opening, a second light-transmitting conductive film connected to the transistor and having a depressed portion in the opening, and an organic resin film with which the depressed portion of the second light-transmitting conductive film is filled.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: March 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daisuke Kubota, Ryo Hatsumi, Masami Jintyou, Takumi Shigenobu, Naoto Goto
  • Patent number: 8975635
    Abstract: First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first and second template epitaxial semiconductor material portions, respectively. At least one dielectric bonding material layer is deposited, and a handle substrate is bonded to the at least one dielectric bonding material layer. The single crystalline substrate, the dielectric template material layer, and the first and second template epitaxial semiconductor material portions are subsequently removed. Elemental semiconductor devices and compound semiconductor devices can be formed on the first and second semiconductor portions, which are embedded within the at least one dielectric bonding material layer on the handle substrate.
    Type: Grant
    Filed: November 28, 2012
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tze-Chiang Chen, Cheng-Wei Cheng, Devendra K. Sadana, Kuen-Ting Shiu
  • Patent number: 8975634
    Abstract: An object is to suppress occurrence of oxygen deficiency. An oxide semiconductor film is formed using germanium (Ge) instead of part of or all of gallium (Ga) or tin (Sn). At least one of bonds between a germanium (Ge) atom and oxygen (O) atoms has a bond energy higher than at least one of bonds between a tin (Sn) atom and oxygen (O) atoms or a gallium (Ga) atom and oxygen (O) atoms. Thus, a crystal of an oxide semiconductor formed using germanium (Ge) has a low possibility of occurrence of oxygen deficiency. Accordingly, an oxide semiconductor film is formed using germanium (Ge) in order to suppress occurrence of oxygen deficiency.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Motoki Nakashima
  • Patent number: 8969879
    Abstract: Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the registration mark is read from the back side by use of red light or near infrared rays, and registration of the stepper is accomplished. It is also possible to form a registration mark in a silicon oxide film on the back side (illuminated side) in registry with the registration mark on the wiring side, and to achieve the desired registration by use of the registration mark thus formed.
    Type: Grant
    Filed: April 15, 2011
    Date of Patent: March 3, 2015
    Assignee: Sony Corporation
    Inventors: Takashi Abe, Nobuo Nakamura, Keiji Mabuchi, Tomoyuki Umeda, Hiroaki Fujita, Eiichi Funatsu, Hiroki Sato
  • Patent number: 8969875
    Abstract: The present invention relates to a thin film transistor substrate and method for fabricating the same which can secure an alignment margin and reduce the number of mask steps. A thin transistor substrate according to the present invention includes a gate line and a data line crossing each other to define a pixel, a gate metal pattern under the data line, a thin film transistor having a gate electrode, a source electrode and a drain electrode in the pixel, and a pixel electrode connected to the drain electrode of the thin film transistor by a connection electrode, wherein the data line has a plurality of first slits to disconnect the gate metal pattern from the gate line.
    Type: Grant
    Filed: October 17, 2012
    Date of Patent: March 3, 2015
    Assignee: LG Display Co., Ltd.
    Inventor: Seung Hee Nam
  • Patent number: 8963158
    Abstract: Design structures, structures and methods of manufacturing structures for providing latch-up immunity for mixed voltage integrated circuits. The structure includes a diffused N-Tub structure embedded in a P-wafer and provided below a retrograde N-well to a non-isolated CMOS logic.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventor: Steven H. Voldman
  • Patent number: 8957422
    Abstract: There is provided a thin film transistor having improved reliability. A gate electrode includes a first gate electrode having a taper portion and a second gate electrode with a width narrower than the first gate electrode. A semiconductor layer is doped with phosphorus of a low concentration through the first gate electrode. In the semiconductor layer, two kinds of n?-type impurity regions are formed between a channel formation region and n+-type impurity regions. Some of the n?-type impurity regions overlap with a gate electrode, and the other n?-type impurity regions do not overlap with the gate electrode. Since the two kinds of n?-type impurity regions are formed, an off current can be reduced, and deterioration of characteristics can be suppressed.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: February 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8946722
    Abstract: An organic light emitting display device with enhanced luminous efficiency and color viewing angle and a method of manufacturing the same are disclosed. The method includes forming a first electrode of each of red, green, blue and white sub-pixels on a substrate, forming a white organic common layer on the first electrodes, and forming a second electrode on the white organic common layer, wherein the first electrodes each includes multiple transparent conductive layers and is formed such that a thickness of the first electrode of each of two sub-pixels among the red, green, blue and white sub-pixels is greater than a thickness of the first electrode of each of the other two sub-pixels, and at least two layers excluding the lowermost layer among the multiple transparent conductive layers of each first electrode are formed to cover opposite sides of the lowermost layer.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: February 3, 2015
    Assignee: LG Display Co., Ltd.
    Inventors: Seung-Hyun Kim, Byung-Chul Ahn, Chang-Wook Han, Hee-Suk Pang, Hong-Seok Choi, Yoon-Heung Tak, Mi-Young Han, Tae-Shick Kim
  • Patent number: 8945997
    Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit having a split-gate nonvolatile memory device includes forming a charge storage structure overlying a semiconductor substrate and having a first sidewall and a second sidewall and forming an interior cavity. The method forms a control gate in the interior cavity. Further, the method forms a first select gate overlying the semiconductor substrate and adjacent the first sidewall. A first memory cell is formed by the control gate and the first select gate. The method also forms a second select gate overlying the semiconductor substrate and adjacent the second sidewall. A second memory cell is formed by the control gate and the second select gate.
    Type: Grant
    Filed: June 27, 2013
    Date of Patent: February 3, 2015
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Zufa Zhang, Khee Yong Lim, Elgin Quek
  • Patent number: 8941112
    Abstract: A semiconductor device in which fluctuation in electric characteristics due to miniaturization is less likely to be caused is provided. The semiconductor device includes an oxide semiconductor film including a first region, a pair of second regions in contact with side surfaces of the first region, and a pair of third regions in contact with side surfaces of the pair of second regions; a gate insulating film provided over the oxide semiconductor film; and a first electrode that is over the gate insulating film and overlaps with the first region. The first region is a CAAC oxide semiconductor region. The pair of second regions and the pair of third regions are each an amorphous oxide semiconductor region containing a dopant. The dopant concentration of the pair of third regions is higher than the dopant concentration of the pair of second regions.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: January 27, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8932914
    Abstract: A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: January 13, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takuya Hirohashi, Masahiro Takahashi, Takashi Shimazu
  • Patent number: 8901566
    Abstract: A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: December 2, 2014
    Assignee: International Business Machines Corporation
    Inventors: Huajie Chen, Dureseti Chidambarrao, Omer H. Dokumaci
  • Patent number: 8901559
    Abstract: One object is to provide a new semiconductor device whose standby power is sufficiently reduced. The semiconductor device includes a first power supply terminal, a second power supply terminal, a switching transistor using an oxide semiconductor material and an integrated circuit. The first power supply terminal is electrically connected to one of a source terminal and a drain terminal of the switching transistor. The other of the source terminal and the drain terminal of the switching transistor is electrically connected to one terminal of the integrated circuit. The other terminal of the integrated circuit is electrically connected to the second power supply terminal.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: December 2, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8890164
    Abstract: A metal oxide semiconductor field effect transistor (MOSFET) for an integrated circuit includes a substrate of a first conductivity type, a first well region of a second conductivity type located in the substrate, and a second well region of the second conductivity type located within the substrate. The second well region is functionally connected to the first well region, and the second well region has a surface area greater than a surface area of the first well region. The MOSFET further includes a source of the first conductivity type located in the first well region, a drain of the first conductivity type located in the first well region, a substrate terminal of the second conductivity type located in the first well region, a gate oxide on a top surface of the first well region, and a gate electrode located on a top surface of the gate oxide.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: November 18, 2014
    Assignee: Xilinx, Inc.
    Inventors: Hong-Tsz Pan, Qi Lin, Yun Wu, Bang-Thu Nguyen
  • Patent number: 8889439
    Abstract: The present disclosure involves a method of packaging light-emitting diodes (LEDs). According to the method, a plurality of LEDs is provided over an adhesive tape. The adhesive tape is disposed on a substrate. In some embodiments, the substrate may be a glass substrate, a silicon substrate, a ceramic substrate, and a gallium nitride substrate. A phosphor layer is coated over the plurality of LEDs. The phosphor layer is then cured. The tape and the substrate are removed after the curing of the phosphor layer. A replacement tape is then attached to the plurality of LEDs. A dicing process is then performed to the plurality of LEDs after the substrate has been removed. The removed substrate may then be reused for a future LED packaging process.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: November 18, 2014
    Assignee: TSMC Solid State Lighting Ltd.
    Inventors: Chi-Xiang Tseng, Hsiao-Wen Lee, Min-Sheng Wu, Tien-Min Lin
  • Patent number: 8853746
    Abstract: The present invention relates to improved complementary metal-oxide-semiconductor (CMOS) devices with stressed channel regions. Specifically, each improved CMOS device comprises an field effect transistor (FET) having a channel region located in a semiconductor device structure, which has a top surface oriented along one of a first set of equivalent crystal planes and one or more additional surfaces oriented along a second, different set of equivalent crystal planes. Such additional surfaces can be readily formed by crystallographic etching. Further, one or more stressor layers with intrinsic compressive or tensile stress are located over the additional surfaces of the semiconductor device structure and are arranged and constructed to apply tensile or compressive stress to the channel region of the FET. Such stressor layers can be formed by pseudomorphic growth of a semiconductor material having a lattice constant different from the semiconductor device structure.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Xiangdong Chen, Thomas W. Dyer, Kenneth Settlemyer, Haining S. Yang
  • Patent number: 8841675
    Abstract: A minute transistor and the method of manufacturing the minute transistor. A source electrode layer and a drain electrode layer are each formed in a corresponding opening formed in an insulating layer covering a semiconductor layer. The opening of the source electrode layer and the opening of the drain electrode layer are formed separately in two distinct steps. The source electrode layer and the drain electrode layer are formed by depositing a conductive layer over the insulating layer and in the openings, and subsequently removing the part located over the insulating layer by polishing. This manufacturing method allows for the source electrode later and the drain electrode layer to be formed close to each other and close to a channel forming region of the semiconductor layer. Such a structure leads to a transistor having high electrical characteristics and a high manufacturing yield even in the case of a minute structure.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: September 23, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshihiko Saito, Atsuo Isobe, Kazuya Hanaoka, Sho Nagamatsu
  • Patent number: 8835243
    Abstract: A semiconductor process includes the following steps. A first structure and a second structure are formed on a substrate. An oxide layer is entirely formed to cover the first structure and the second structure. A nitride layer is formed to entirely cover the oxide layer. A dry etching process is performed to remove a part of the nitride layer on the first structure. A wet etching process is performed to entirely remove the nitride layer and the oxide layer on the first structure and the second structure.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: September 16, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Tzung-I Tsai, Shui-Yen Lu
  • Patent number: 8823146
    Abstract: A semiconductor structure having a silicon substrate having a <111> crystallographic orientation, an insulating layer disposed over a first portion of the silicon substrate, a silicon layer having a <100> orientation disposed over the insulating layer, and a non-nitride column III-V semiconductor layer or column II-VI semiconductor layer having the same <111> crystallographic orientation as the silicon substrate, the non-nitride column III-V semiconductor layer or column II-VI semiconductor layer being in direct contact with a second portion of the silicon substrate. A column III-nitride is disposed on the surface of the third portion of the substrate.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: September 2, 2014
    Assignee: Raytheon Company
    Inventor: William E. Hoke
  • Patent number: 8810765
    Abstract: An electroluminescence element includes an electroluminescence substrate including a thin film transistor substrate, and a light-emitting layer provided over the thin film transistor substrate and divided by picture-element separating portions so as to correspond to unit picture elements; and a sealing substrate arranged to hermetically seal the light-emitting layer of the electroluminescence substrate. At least one of the electroluminescence substrate and the sealing substrate is a flexible substrate. Spacers are provided between the electroluminescence substrate and the sealing substrate.
    Type: Grant
    Filed: January 11, 2008
    Date of Patent: August 19, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tohru Okabe, Hirohiko Nishiki
  • Patent number: 8809850
    Abstract: One object is to provide a new semiconductor device whose standby power is sufficiently reduced. The semiconductor device includes a first power supply terminal, a second power supply terminal, a switching transistor using an oxide semiconductor material and an integrated circuit. The first power supply terminal is electrically connected to one of a source terminal and a drain terminal of the switching transistor. The other of the source terminal and the drain terminal of the switching transistor is electrically connected to one terminal of the integrated circuit. The other terminal of the integrated circuit is electrically connected to the second power supply terminal.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: August 19, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8803276
    Abstract: A structure and method of fabricating electrostatic discharge (EDS) circuitry in an integrated circuit chip by integrating a lateral bipolar, either a p-n-p with a NMOSFET or a n-p-n with a PMOSFET within a triple well. The lateral bipolar preferably includes diodes at the I/O and/or the VDDs of the circuitry.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventors: Shunhua Chang, Kiran V. Chatty, Robert J. Gauthier, Mujahid Muhammad
  • Patent number: 8772074
    Abstract: Provided are an organic light emitting display device and a method for manufacturing the same. The organic light emitting display device comprises a transistor on a substrate, a cathode on the transistor and connected to a source or a drain of the transistor, a bank layer on the cathode and having an opening, a metal buffer layer on the cathode, an organic light emitting layer on the metal buffer layer, and an anode on the organic light emitting layer.
    Type: Grant
    Filed: August 12, 2009
    Date of Patent: July 8, 2014
    Assignee: LG Display Co., Ltd.
    Inventors: Jaehee Park, Heeseok Yang, Howon Choi
  • Patent number: 8754417
    Abstract: Vertically stacked Field Effect Transistors (FETs) are created where a first FET and a second FET are controllable independently. The vertically stacked FETs may be connected in series or in parallel, thereby suitable for use as a portion of a NAND circuit or a NOR circuit. Epitaxial growth over a source and drain of a first FET, and having similar doping to the source and drain of the first FET provide a source and drain of a second FET. An additional epitaxial growth of a type opposite the doping of the source and drain of the first FET provides a body for the second FET.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Todd Alan Christensen, Phil Christopher Felice Paone, David Paul Paulsen, John Edward Sheets, II
  • Patent number: 8748222
    Abstract: A method for manufacturing oxide thin film transistors includes steps of: forming a gate, a drain electrode, a source electrode, and an oxide semiconductor layer respectively. The oxide semiconductor layer is formed on the gate electrode; the drain electrode and the source electrode are formed at two opposite sides of the oxide semiconductor layer. The method further includes a step of depositing a dielectric layer of silicon oxide, and a reacting gas for depositing the silicon oxide includes silane and nitrous oxide. A flow rate of nitrous oxide is in a range from 10 to 200 standard cubic centimeters per minute (SCCM). Oxide thin film transistors manufactured by above method has advantages of low leakage, high mobility, and other integrated circuit member can be directly formed on the thin film transistor array substrate of a display device.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: June 10, 2014
    Assignee: E Ink Holdings Inc.
    Inventors: Ted-Hong Shinn, Henry Wang, Fang-An Shu, Yao-Chou Tsai
  • Patent number: 8735194
    Abstract: Provided is a method of manufacturing a display apparatus, including forming a drive circuit and a light-emitting portion on a substrate in which the forming the light-emitting portion includes forming a transparent anode electrode for applying a charge to an emission layer, forming a first coating layer and a second coating layer on the transparent anode electrode, removing the first coating layer by etching using the second coating layer as a mask, and forming a layer including the emission layer on a part of the transparent anode electrode from which the first coating layer is removed. A surface of the transparent anode electrode becomes as clean as a surface cleaned with ultraviolet irradiation.
    Type: Grant
    Filed: October 1, 2008
    Date of Patent: May 27, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Takahashi, Masafumi Sano
  • Patent number: 8686425
    Abstract: A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: April 1, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takuya Hirohashi, Masahiro Takahashi, Takashi Shimazu