Abstract: Provided is a CMOS image sensor with an asymmetric well structure of a source follower. The CMOS image sensor includes: a well disposed in an active region of a substrate; a drive transistor having one terminal connected to a power voltage and a first gate electrode disposed to cross the well; and a select transistor having a drain-source junction between another terminal of the drive transistor and an output node, and a second gate electrode disposed in parallel to the drive transistor. A drain region of the drive transistor and a source region of the select transistor are asymmetrically arranged.

Abstract: Ni silicide is formed through simple steps. After forming a semiconductor film over a substrate, a Ni film is deposited over the semiconductor film while heating the substrate, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, a Ni film is deposited over the semiconductor film while heating the substrate up to 450° C. or higher, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, a Ni film is deposited with a thickness of 10 nm or more over the semiconductor film while heating the substrate to 450° C. or higher, thereby forming Ni silicide on the semiconductor film. Alternatively, after forming a semiconductor film over a substrate, and removing an oxide film on the semiconductor film, a Ni film is deposited over the semiconductor film while heating the substrate up to 450° C. or higher, thereby forming Ni silicide on the semiconductor film.

Abstract: A method for forming a self-aligned, dual stress liner for a CMOS device includes forming a first type stress layer over a first polarity type device and a second polarity type device, and forming a sacrificial layer over the first type nitride layer. Portions of the first type stress layer and the sacrificial layer over the second polarity type device are patterned and removed. A second type stress layer is formed over the second polarity type device, and over remaining portions of the sacrificial layer over the first polarity type device in a manner such that the second type stress layer is formed at a greater thickness over horizontal surfaces than over sidewall surfaces. Portions of the second type stress liner on sidewall surfaces are removed, and portions of the second type stress liner over the first polarity type device are removed.

Abstract: Embodiments of the invention provide a substrate with a device layer having different crystal orientations in different portions or areas. One layer of material having one crystal orientation may be bonded to a substrate having another crystal orientation. Then, a portion of the layer may be amorphized and annealed to be re-crystallized to the crystal orientation of the substrate. N- and P-type devices, such as tri-gate devices, may both be formed on the substrate, with each type of device having the proper crystal orientation along the top and side surfaces of the claimed region for optimum performance. For instance, a substrate may have a portion with a <100> crystal orientation along a top and sidewalls of an NMOS tri-gate transistor and another portion having a <110> crystal orientation along parallel top and sidewall surfaces of a PMOS tri-gate transistor.

Abstract: An apparatus and method for an inverted multilayer silicon over insulator (SOI) device is provided. In the multilayer SOI device, the crystal orientation of at least one active region of a device may be different than the active region of at least another device. Where the multilayer SOI device has a first layer including a PMOS device with a silicon active region having a crystal orientation of [100], the second layer may be an NMOS device with an active region having a silicon layer having a crystal orientation of [110]. The second layer is bonded to the first layer. The method and apparatus can be extended to more than two layers thus forming a multilayer SOI device having a different crystal orientation at each layer. The multiple layer SOI device may form circuits of reduced surface area.

Abstract: A semiconductor device may include a substrate and an insulating layer formed on the substrate. A multi-layer fin may be formed on the insulating layer and may include two semiconducting layers isolated by an insulating layer in vertical direction. A first MOS type device comprising a first source region, a first channel region and a first drain region is arranged on the first semiconducting layer in the multi-layer fin. A second MOS type device comprising a second source region, a second channel region and a second drain region is arranged on the second semiconducting layer in the multi-layer fin. A gate electrode is provided so as to be vertically adjacent to the first and second channel regions.

Abstract: A static random-access memory (SRAM) device may include a bulk MOS transistor on a semiconductor substrate having a source/drain region therein, an insulating layer on the bulk MOS transistor, and a thin-film transistor having a source/drain region therein on the insulating layer above the bulk MOS transistor. The device may further include a multi-layer plug between the bulk MOS transistor and the thin-film transistor. The multi-layer plug may include a semiconductor plug directly on the source/drain region of the bulk MOS transistor and extending through at least a portion of the insulating layer, and a metal plug directly on the source/drain region of the thin-film transistor and the semiconductor plug and extending through at least a portion of the insulating layer. Related methods are also discussed.

Abstract: A semiconductor device includes a laminated substrate; a removal portion; a cavity; a first semiconductor element; and a second semiconductor element. In the laminated substrate, a bulk layer, an insulating layer, and a semiconductor layer are laminated in this order from a bottom. The laminated substrate includes a first area, a second area adjacent to the first area, and a third area adjacent to the second area in each of the layers. The semiconductor layer, the insulating layer, and an upper portion of the bulk layer in the first area are removed to form the removal portion. A part of the bulk layer in the second area is removed to form the cavity adjacent to the removal portion. The first semiconductor element is formed in the bulk layer in the removal portion as an ESD protection element. The second semiconductor element is formed partially in the semiconductor layer in the second area.

Abstract: A process of forming an electronic device can include forming an insulating layer over first and second active regions, and a field isolation region. The process can also include forming a seed layer and exposing the first active region. The process can further include selectively forming a first and second semiconductor layer over the first active region and the seed layer, respectively. The first and second semiconductor layers can be spaced-apart from each other. In one aspect, the process can include selectively forming the first and second semiconductor layers simultaneously at a substantially same point in time. In another aspect, an electronic device can include first and second transistor structures separated by a field isolation region and electrically connected by a conductive member. A semiconductor island, designed to be electrically floating, can lie between the conductive member and the base layer.

Abstract: A semiconductor device such as a DRAM memory device is disclosed. A substrate (12) of semiconductor material is provided with energy band modifying means in the form of a box region (38) and is covered by an insulating layer (14). A semiconductor layer (16) has source (18) and drain (20) regions formed therein to define bodies (22) of respective field effect transistors. The box region (38) is more heavily doped than the adjacent body (22), but less highly doped than the corresponding source (18) and drain (20), and modifies the valence and/or conduction band of the body (22) to increase the amount of electrical charge which can be stored in the body (22).

Abstract: Disclosed are a CMOS image sensor capable of improving the focusing capability of light and a method for manufacturing the same. The CMOS image sensor includes a plurality of first micro-lenses formed in the upper part of the planarization layer, each of the first micro-lenses arranged over a corresponding photodiode, and a plurality of second micro-lenses formed on the planarization layer, each of the plurality of second micro-lenses wrapping a corresponding first micro-lens respectively.

Abstract: A light emitting device is provided which has a structure for preventing degradation of a light emitting element due to water and oxygen contained in an interlayer insulating film formed between a TFT and the light emitting element. A TFT is formed on a substrate, an inorganic insulating film is formed on the TFT from an inorganic material and serves as a first insulating film, an organic insulating film is formed on the first insulating film from an organic material and serves as a second insulating film, and an inorganic insulating film is formed on the second insulating film from an inorganic material and serves as a third insulating film. Thus obtained is a structure for preventing the second insulating film from releasing moisture and oxygen. In order to avoid defect in forming the film, a portion of the third insulating film where a contact hole is formed is removed alone.

Abstract: Phase change Random Access Memory (PRAM) devices include a substrate and a phase change layer pattern on the substrate. The phase change layer pattern includes a sharp tip and at least one wall that extends from the sharp tip in a direction away from the substrate. At least one contact hole node is provided that contacts the phase change material pattern adjacent the sharp tip.

Abstract: A semiconductor integrated circuit includes an n-channel MOS transistor and a p-channel MOS transistor formed respectively in first and second device regions of a substrate, the n-channel MOS transistor including a first gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, the p-channel MOS transistor including a second gate electrode carrying sidewall insulation films on respective sidewall surfaces thereof, wherein there is provided a stressor film on the substrate over the first and second device regions such that the stressor film covers the first gate electrode including the sidewall insulation films thereof and the second gate electrode including the sidewall insulation films thereof, wherein the stressor film has a decreased film thickness in the second device region at least in the vicinity of a base part of the second gate electrode.

Abstract: A gate insulating film is formed using a plasma on a three-dimensional silicon substrate surface having a plurality of crystal orientations. The plasma gate insulating film experiences no increase in interface state in any crystal orientations and has a uniform thickness even at corner portions of the three-dimensional structure. By forming a high-quality gate insulating film using a plasma, there can be obtained a semiconductor device having good characteristics.

Abstract: A CMOS image sensor includes a substrate including silicon, a silicon germanium (SiGe) epitaxial layer formed over the substrate, the SiGe epitaxial layer formed through epitaxial growth and doped with a predetermined concentration level of impurities, an undoped silicon epitaxial layer formed over the SiGe epitaxial layer by epitaxial growth, and a photodiode region formed from a top surface of the undoped silicon epitaxial layer to a predetermined depth in the SiGe epitaxial layer.

Abstract: The present invention provides a method of integrated semiconductor devices such that different types of devices are formed upon a specific crystallographic orientation of a hybrid substrate. In accordance with the present invention, junction capacitance of one of the devices is improved in the present invention by forming the source/drain diffusion regions of the device in an epitiaxial semiconductor material such that they are situated on a buried insulating layer that extends partially underneath the body of the second semiconductor device. The second semiconductor device, together with the first semiconductor device, is both located atop the buried insulating layer. Unlike the first semiconductor device in which the body thereof is floating, the second semiconductor device is not floating. Rather, it is in contact with an underlying first semiconducting layer.

Abstract: In accordance with the invention, there are CMOS devices and semiconductor devices and methods of fabricating them. The CMOS device can include a substrate including a first active region and a second active region and a first transistor device over the first active region, wherein the first transistor device includes a high-K layer over the first active region, a first dielectric capping layer on the high-K layer, and a first metal gate layer over the first dielectric capping layer. The CMOS device can also include a second transistor device over the second active region, wherein the second transistor device includes a high-K layer over the second active region, a second dielectric capping layer on the second high-K layer, and a second metal gate layer over the second dielectric capping layer.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include amorphizing at least one contact area of a source/drain region of a transistor structure by implanting through at least one contact opening, forming a first layer of metal on the at least one contact area, forming a second layer of metal on the first layer of metal, selectively etching a portion of the second metal layer, and annealing the at least one contact area to form at least one silicide.

Abstract: A CMOS image sensor and a method for fabricating the same is disclosed, to enhance the image-sensing efficiency by forming a concave lens area for improving the light-condensing efficiency in a planarization layer formed before a micro-lens array, in which the CMOS image sensor includes a plurality of photosensitive devices on a semiconductor substrate; an insulating interlayer on the plurality of photosensitive devices; a plurality of color filter layers in correspondence with the respective photosensitive devices, to filter the light by respective wavelengths; a planarization layer on the color filter layers, and having first micro-lens by intaglio in correspondence with the respective photosensitive patterns to condense the light secondly; and a plurality of second micro-lens layers on the planarization layer in correspondence with the respective photosensitive devices, to condense the light firstly.

Abstract: An active layer of an NTFT includes a channel forming region, at least a first impurity region, at least a second impurity region and at least a third impurity region therein. Concentrations of an impurity in each of the first, second and third impurity regions increase as distances from the channel forming region become longer. The first impurity region is formed to be overlapped with a side wall. A gate overlapping structure can be realized with the side wall functioning as an electrode.

Abstract: To achieve promotion of stability of operational function of display device and enlargement of design margin in circuit design, in a display device including a pixel portion having a semiconductor element and a plurality of pixels provided with pixel electrodes connected to the semiconductor element on a substrate, the semiconductor element includes a photosensitive organic resin film as an interlayer insulating film, an inner wall face of a first opening portion provided at the photosensitive organic resin film is covered by a second insulating nitride film, a second opening portion provided at an inorganic insulating film is provided on an inner side of the first opening portion, the semiconductor and a wiring are connected through the first opening portion and the second opening portion and the pixel electrode is provided at a layer on a lower side of an activation layer.

Abstract: Regions of an integrated circuit are isolated by a structure that includes at least one isolating trench on the periphery of an active area. The trench is deep, extending at least about 0.5 ?m into the substrate. The isolating structure prevents photons and electrons originating in peripheral circuitry from reaching the active area. Where the substrate has a heavily-doped lower layer and an upper layer on it, the trench can extend through the upper layer to the lower layer. A thermal oxide can be grown on the trench walls. A liner can also be deposited on the sidewalls of each trench. A fill material having a high-extinction coefficient is then deposited over the liner. The liner can also be light absorbent so that both the liner and fill material block photons.

Abstract: The active layer of an n-channel TFT is formed with a channel forming region, a first impurity region, a second impurity region and a third impurity region. In this case, the concentration of the impurities in each of the impurity regions is made higher as the region is remote from the channel forming region. Further, the first impurity region is disposed so as to overlap a side wall, and the side wall is caused to function as an electrode to thereby attain a substantial gate overlap structure. By adopting the structure, a semiconductor device of high reliability can be manufactured.

Abstract: In one embodiment, an intrinsic single crystalline semiconductor plug is formed to pass through a lower insulating layer using a selective epitaxial growth process employing a node impurity region as a seed layer, and a single crystalline semiconductor body pattern is formed on the lower insulating layer using the intrinsic single crystalline semiconductor plug as a seed layer. When the recessed single crystalline semiconductor plug is doped with impurities having the same conductivity type as the node impurity region, a peripheral impurity region is prevented from being counter-doped. As a result, it is possible to implement a high performance semiconductor device that requires a single crystalline thin film transistor as well as a node contact structure with ohmic contact.

Abstract: A thin film transistor with multiple gates is fabricated using a super grain silicon (SGS) crystallization process. The thin film transistor a semiconductor layer formed in a zigzag shape on an insulating substrate, and a gate electrode intersecting with the semiconductor layer. The semiconductor layer has a high-angle grain boundary in a portion of the semiconductor layer that does not cross the gate electrode.

Abstract: Embodiments of the invention provide a substrate with a device layer having different crystal orientations in different portions or areas. One layer of material having one crystal orientation may be bonded to a substrate having another crystal orientation. Then, a portion of the layer may be amorphized and annealed to be re-crystallized to the crystal orientation of the substrate. N- and P-type devices, such as tri-gate devices, may both be formed on the substrate, with each type of device having the proper crystal orientation along the top and side surfaces of the claimed region for optimum performance. For instance, a substrate may have a portion with a <100> crystal orientation along a top and sidewalls of an NMOS tri-gate transistor and another portion having a <110> crystal orientation along parallel top and sidewall surfaces of a PMOS tri-gate transistor.

Abstract: To provide a technique required for purifying the interface between an active layer and an insulating film. On a substrate (101), a gate wiring (103) is formed and the surface thereof is covered with a gate oxide film (104). Then, a first insulating film (105a), a second insulating film (105b), a semiconductor film (106) and a protective film (107) are sequentially formed and layered without exposing them to the air. Further, the semiconductor film (106) is irradiated with laser light through the protective film (107). In this way, a TFT may be given good characteristics by completely purifying the interface of the semiconductor film.

Abstract: A TFT, in which source and drain electrodes having concentric circular shapes are formed, reduces an OFF current caused by a leakage current and optimizes an ON current and a stray capacitance between gate and source electrodes. The TFT includes a gate electrode formed on a substrate; and source and drain electrodes obtained by sequentially forming a gate insulating film, an intrinsic amorphous silicon layer, and an n+ amorphous silicon layer on the gate electrode, wherein the source and drain electrodes have circular shapes. One of the source and drain electrodes is disposed at the center, and the other one of the source and drain electrodes having a concentric circular shape surrounds the former. A channel region may be formed between the source and drain electrodes; and an area of an effective stray capacitance may be less than 150 ?m2. A ratio of a width of a channel to a length of the channel may be more than 4.5 and a filling capacity index to the effective stray capacitance may be less than 50.

Abstract: A fabricating method of a memory cell including the following steps is provided. First, a poly-Si island including a source doped region, a drain doped region, and a channel region located therebetween is formed on a substrate. Then, a dielectric layer is formed on the poly-Si island. Afterward, an amorphous silicon-germanium (?-SiGe) layer is formed on the dielectric layer. Next, a laser annealing process is performed to oxidize the ?-SiGe layer into a silicon oxide layer, so as to separate out Ge atoms from the ?-SiGe layer to form a Ge quantum dot layer between the silicon oxide layer and the dielectric layer. After that, a control gate is formed on the silicon oxide layer.

Abstract: To provide TFT of improved low-temperature polycrystalline layer that has higher electron mobility and assures less fluctuation in manufacture in view of realizing a liquid-crystal display device having a large display area by utilizing a glass substrate. A TFT having higher electron mobility can be realized within the predetermined range of characteristic fluctuation by utilizing the semiconductor thin-film (called quasi single crystal thin-film) formed of poly-crystal grain joined with the {111} twin-boundary of Diamond structure as the channel region (namely, active region) of TFT.

Abstract: A CMOS transistor structure and related method of manufacture are disclosed in which a first conductivity type MOS transistor comprises an enhancer and a second conductivity type MOS transistor comprises a second spacer formed of the same material as the enhancer. The second conductivity type MOS transistor also comprises a source/drain region formed in relation to an epitaxial layer formed in a recess region.

Abstract: A semiconductor laminate containing a light-emitting layer is etched to reveal a side surface. A reflection surface opposite to the side surface of the semiconductor laminate is provided in one and the same chip as the semiconductor laminate. A groove may be formed in the laminate by a dicing saw, and an outer side surface of the groove may be provided as the reflection surface.

Abstract: A semiconductor structure and a method for forming the same. The method includes providing a semiconductor structure which includes (a) substrate, (b) a first semiconductor region on top of the substrate, wherein the first semiconductor region comprises a first semiconductor material and a second semiconductor material, which is different from the first semiconductor material, and wherein the first semiconductor region has a first crystallographic orientation, and (c) a third semiconductor region on top of the substrate which comprises the first and second semiconductor materials and has a second crystallographic orientation. The method further includes forming a second semiconductor region and a fourth semiconductor region on top of the first and the third semiconductor regions respectively. Both second and fourth semiconductor regions comprise the first and second semiconductor materials.

Abstract: After an amorphous semiconductor thin film is crystallized by utilizing a catalyst element, the catalyst element is removed by performing a heat treatment in an atmosphere containing a halogen element. A resulting crystalline semiconductor thin film exhibits {110} orientation. Since individual crystal grains have approximately equal orientation, the crystalline semiconductor thin film has substantially no grain boundaries and has such crystallinity as to be considered a single crystal or considered so substantially.

Abstract: A method for producing a thin film transistor substrate includes the steps of: (i) depositing an amorphous semiconductor film on a transparent insulating substrate; (ii) patterning the amorphous semiconductor film so as to form insular amorphous semiconductor films, the step (ii) including a process (I) for forming, in respective stripe areas each of which is elongate in a first direction in a display area, a plurality of insular semiconductor films whose channel length is in line with the first direction, and a process (II) for forming, in an area including extended portions of the striped areas in a peripheral circuit area, a plurality of insular semiconductor films; (iii) polycrystallizing the insular semiconductor films in the peripheral circuit area so that the insular semiconductor films have high mobility in a second direction and polycrystallizing the insular semiconductor films in the display area so that the insular semiconductor films have high mobility in the first direction; and (iv) forming TFTs

Abstract: The present invention provides a thin-film transistor offering a higher electron (or hole) mobility, a method for manufacturing the thin-film transistor, and a display using the thin-film transistor. The present invention provides a thin-film transistor having a source region, a channel region, and a drain region in a semiconductor thin film with a crystal grown in a horizontal direction, the thin-film transistor having a gate insulating film and a gate electrode over the channel region, wherein a drain edge of the drain region which is adjacent to the channel region is formed in the vicinity of a crystal growth end position.

Abstract: Thin film transistor based three-dimensional CMOS inverters utilizing a common gate bridged between a PFET device and an NFET device. One or both of the NFET and PFET devices can have an active region extending into both a strained crystalline lattice and a relaxed crystalline lattice. The relaxed crystalline lattice can comprise appropriately-doped silicon/germanium. The strained crystalline lattice can comprise, for example, appropriately doped silicon, or appropriately-doped silicon/germanium. The CMOS inverter can be part of an SOI construction formed over a conventional substrate (such as a monocrystalline silicon wafer) or a non-conventional substrate (such as one or more of glass, aluminum oxide, silicon dioxide, metal and plastic).

Abstract: The present invention relates to a semiconductor device including a circuit composed of thin film transistors having a novel GOLD (Gate-Overlapped LDD (Lightly Doped Drain)) structure. The thin film transistor comprises a first gate electrode and a second electrode being in contact with the first gate electrode and a gate insulating film. Further, the LDD is formed by using the first gate electrode as a mask, and source and drain regions are formed by using the second gate electrode as the mask. Then, the LDD overlapping with the second gate electrode is formed. This structure provides the thin film transistor with high reliability.

Abstract: Forming a back-illuminated type CMOS image sensor, includes process for formation of a registration mark on the wiring side of a silicon substrate during formation of an active region or a gate electrode. A silicide film using an active region may also be used for the registration mark. Thereafter, the registration mark is read from the back side by use of red light or near infrared rays, and registration of the stepper is accomplished. It is also possible to form a registration mark in a silicon oxide film on the back side (illuminated side) in registry with the registration mark on the wiring side, and to achieve the desired registration by use of the registration mark thus formed.

Abstract: A semiconductor device includes a transistor of a first conductivity type and a transistor of a second conductivity type. The transistor of the first conductivity type includes a first gate portion formed on a first region of a semiconductor substrate, a first sidewall formed on each side face of the first gate portion, a first protecting film formed between the first sidewall and the first gate portion, and an extension diffusion layer of the first conductivity type. The transistor of the second conductivity type includes a second gate portion formed on a second region of the semiconductor substrate, a second sidewall formed on each side face of the second gate portion, a second protecting film having an L-shaped cross-section and formed between the second sidewall and the second gate portion and between the second sidewall and the semiconductor substrate, and an extension diffusion layer of the second conductivity type.

Abstract: A semiconductor device includes a substrate with an insulating surface and a single crystal semiconductor layer, which is bonded to the insulating surface of the substrate. The device further includes a first insulating layer, which is provided between the insulating surface of the substrate and the single crystal semiconductor layer, and a second insulating layer, which has been deposited on the entire insulating surface of the substrate except an area in which the first insulating layer is present.

Abstract: A semiconductor device includes a thin film transistor including a semiconductor layer that includes a channel region, a source region and a drain region, a gate insulating film provided on the semiconductor layer, and a gate electrode for controlling the conductivity of the channel region, wherein the surface of the semiconductor layer includes a minute protruding portion, and the side surface inclination angle of the gate electrode is larger than the inclination angle of the protruding portion of the semiconductor layer.

Abstract: A display apparatus includes; a switching transistor, a driving transistor, a control terminal of which is connected to an output terminal of the switching transistor, a storage capacitor provided between the output terminal of the switching transistor and an output terminal of the driving transistor, and a complementary metal oxide semiconductor (“CMOS”) transistor connected in parallel with a control terminal of the switching transistor.

Abstract: A semiconductor device is provided with a stressed channel region, where the stresses film causing the stress in the stress channel region can extend partly or wholly under the gate structure of the semiconductor device. In some embodiments, a ring of stress film surround the channel region, and may apply stress from all sides of the channel. Consequently, the stress film better surrounds the channel region of the semiconductor device and can apply more stress in the channel region.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Abstract: A layout structure of a static random access memory (SRAM) cell array includes at least one SRAM cell area, oxide defined (OD) area and strapping cell area. The SRAM cell area has a longitudinal side being at least twice longer than a transverse side thereof. The oxide defined (OD) area is formed on an insulating layer, extending across at least two neighboring SRAM cell areas for construction of a passing gate transistor and a pull-down transistor used in an SRAM cell. The strapping cell area is interposed between the SRAM cell areas, in which a strapping cell is constructed for connecting the OD area to a fixed potential, thereby preventing bodies of the passing gate transistor and the pull-down transistor constructed on the OD area from floating.

Abstract: A double gate silicon over insulator transistor may be formed wherein the bottom gate electrode is formed of a doped diamond film. The doped diamond film may be formed in the process of semiconductor manufacture resulting in an embedded electrode. The diamond film may be advantageous as a heat spreader.

Abstract: Solder ball assembly for a semiconductor device and method of fabricating the same is described. In one example, a solder mask is formed on a substrate having an aperture exposing at least a portion of a conductive pad of the substrate. A solder pillar is formed in the aperture and in electrical communication with the conductive pad. An insulating layer is formed on the solder mask exposing at least a portion of the solder pillar. The exposed portion of the solder pillar is removed to define a mounting surface. A solder ball is formed on the mounting surface in electrical communication with the solder pillar. The solder pillar may include high-temperature solder having a melting point higher than that of the solder ball.

Abstract: According to one embodiment of the invention, a method for integrating low Schottky barrier metal source/drain includes providing a substrate, forming an epitaxial SiGe layer outwardly from the substrate, forming an epitaxial Si layer outwardly from the SiGe layer, and forming a metal source and a metal drain.