Housing Entirely Of Metal Except For Feedthrough Structure Patents (Class 257/699)
  • Patent number: 10231326
    Abstract: A flexible printed circuit board and a display device are disclosed by embodiments of the invention. The flexible printed circuit board has one or more waveform structures disposed on its cross section.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: March 12, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Long Xia
  • Patent number: 9563021
    Abstract: An optical switching device including an optical switching engine may be packaged by omitting an optical bench and disposing optical elements directly on a base of a housing of the optical switching device. The optical switching engine may be disposed on a ceramic portion of the base, and thermally matched to the ceramic base. The base may be reinforced by the housing walls and optional internal rigidity ribs. The optical elements may be thermally matched to the base, and the lid may be strain relieved by thinning lid edges. The housing may be mounted to an external chassis using soft grummets.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: February 7, 2017
    Assignee: Lumentum Operations LLC
    Inventors: Abdul Jaleel K. Moidu, Sheldon McLaughlin, Nenad Duricic
  • Patent number: 9332631
    Abstract: A main object of the invention is to provide a heat dissipating substrate which is excellent in heat dissipating performance, and undergoes neither peel therein nor short circuit. The invention attains this objet by providing a heat dissipating substrate comprising a support base material, an insulating layer formed directly on the support base material, and a wiring layer formed directly on the insulating layer, wherein the insulating layer is formed by non-thermoplastic polyimide resin, and has a thickness in the range of 1 ?m to 20 ?m.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: May 3, 2016
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Shunji Fukuda, Katsuya Sakayori, Toshimasa Takarabe
  • Patent number: 9312817
    Abstract: A single semiconductor device package that reduces electromagnetic coupling between elements of a semiconductor device embodied within the package is provided. For a dual-path amplifier, such as a Doherty power amplifier, an isolation feature that separates carrier amplifier elements from peaking amplifier elements is included within the semiconductor device package. The isolation feature can take the form of a structure that is constructed of a conductive material coupled to ground and which separates the elements of the amplifier. The isolation feature can be included in a variety of semiconductor packages, including air cavity packages and overmolded packages. Through the use of the isolation feature provided by embodiments of the present invention a significant improvement in signal isolation between amplifier elements is realized, thereby improving performance of the dual-path amplifier.
    Type: Grant
    Filed: July 20, 2012
    Date of Patent: April 12, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Peter H. Aaen, David J. Dougherty, Manuel F. Romero, Lakshminarayan Viswanathan
  • Patent number: 9000582
    Abstract: A power semiconductor module includes: a circuit body having a power semiconductor element and a conductor member connected to the power semiconductor element; a case in which the circuit body is housed; and a connecting member which connects the circuit body and the case. The case includes: a first heat dissipating member and a second heat dissipating member which are disposed in opposed relation to each other while interposing the circuit body in between; a side wall which joins the first heat dissipating member and the second heat dissipating member; and an intermediate member which is formed on the periphery of the first heat dissipating member and connected to the side wall, the intermediate member including a curvature that is projected toward a housing space of the case.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: April 7, 2015
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Shinji Hiramitsu, Atsushi Koshizaka, Masato Higuma, Hiroshi Tokuda, Keiji Kawahara
  • Patent number: 8981537
    Abstract: A semiconductor device has a base substrate having a plurality of metal traces and a plurality of base vias. An opening is formed through the base substrate. At least one die is attached to the first surface of the substrate and positioned over the opening. A cover substrate has a plurality of metal traces. A cavity in the cover substrate forms side wall sections around the cavity. The cover substrate is attached to the base substrate so the at least one die is positioned in the interior of the cavity. Ground planes in the base substrate are coupled to ground planes in the cover substrate to form an RF shield around the at least one die.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: March 17, 2015
    Assignee: Amkor Technology, Inc.
    Inventors: David Bolognia, Bob Shih-Wei Kuo, Bud Troche
  • Patent number: 8900996
    Abstract: A method of fabricating a through silicon via (TSV) structure is provided, in which, a first dielectric layer is formed on the substrate, the first dielectric layer is patterned to have at least one first opening, a via hole is formed in the first dielectric layer and the substrate, a second dielectric layer is conformally formed on the first dielectric layer, the second dielectric layer has at least one second opening corresponding to the at least one first opening, and the second dielectric layer covers a sidewall of the via hole. A conductive material layer is formed to fill the via hole and the second opening. The conductive material layer is planarized to form a TSV within the via hole. A TSV structure is also provided, in which, the second dielectric layer is disposed within the first opening and on the sidewall of the via hole.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: December 2, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Hsin-Yu Chen, Home-Been Cheng, Yu-Han Tsai, Ching-Li Yang
  • Patent number: 8890306
    Abstract: A light-emitting diode includes a carrier with a mounting face and includes a metallic basic body and at least two light-emitting diode chips affixed to the carrier at least indirectly at the mounting face, wherein an outer face of the metallic basic body includes the mounting face, the at least two light-emitting diode chips connect in parallel with one another, the at least two light-emitting diode chips are embedded in a reflective coating, the reflective coating covering the mounting face and side faces of the light-emitting diode chips, and the light-emitting diode chips protrude with their radiation exit surfaces out of the reflective coating, and the radiation exit surfaces face away from the carrier.
    Type: Grant
    Filed: May 24, 2011
    Date of Patent: November 18, 2014
    Assignee: OSRAM Opto Semiconductor GmbH
    Inventors: Joachim Reill, Georg Bogner, Stefan Grötsch
  • Patent number: 8872328
    Abstract: An integrated power module includes a substantially planar insulated metal substrate having at least one cut-out region; at least one substantially planar ceramic substrate disposed within the cut-out region, wherein the ceramic substrate is framed on at least two sides by the insulated metal substrate, the ceramic substrate including a first metal layer on a first side and a second metal layer on a second side; at least one power semiconductor device coupled to the first side of the ceramic substrate; at least one control device coupled to a first surface of the insulated metal substrate; a power overlay electrically connecting the at least one semiconductor power device and the at least one control device; and a cooling fluid reservoir operatively connected to the second metal layer of the at least one ceramic substrate, wherein a plurality of cooling fluid passages are provided in the cooling fluid reservoir.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: October 28, 2014
    Assignee: General Electric Company
    Inventors: Eladio Clemente Delgado, John Stanley Glaser, Brian Lynn Rowden
  • Patent number: 8796832
    Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device connects an electrode on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode. The second terminal is connected with the external wiring device. The wiring portion connects the first terminal with the second terminal.
    Type: Grant
    Filed: February 23, 2012
    Date of Patent: August 5, 2014
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Susumu Baba, Masachika Masuda, Hiromichi Suzuki
  • Patent number: 8772818
    Abstract: A radiation-emitting device is provided which comprises a substrate (10), at least one organic functional layer (100) on the substrate (10) and a second electrode (80) on the at least one organic functional layer (100). The substrate (10) includes a plastics film (1) and a metal film (3), and the metal film (3) is arranged between the plastics film (1) and the at least one organic functional layer (100) and is set up as a first electrode. A method is additionally provided for producing such a device.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: July 8, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Markus Klein, Tilman Schlenker, Andrew Ingle
  • Patent number: 8686569
    Abstract: A die arrangement includes a carrier having a first side and a second side opposite the first side, the carrier including an opening leading from the first side of the carrier to the second side of the carrier; a first die disposed over the first side of the carrier and electrically contacting the carrier; a second die disposed over the second side of the carrier and electrically contacting the carrier; and an electrical contact structure leading through the opening in the carrier and electrically contacting the second die.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: April 1, 2014
    Assignee: Infineon Technologies AG
    Inventors: Frank Daeche, Joachim Mahler, Anton Prueckl, Stefan Landau, Josef Hoeglauer
  • Patent number: 8629060
    Abstract: A method of forming a through substrate interconnect includes forming a via into a semiconductor substrate. The via extends into semiconductive material of the substrate. A liquid dielectric is applied to line at least an elevationally outermost portion of sidewalls of the via relative a side of the substrate from which the via was initially formed. The liquid dielectric is solidified within the via. Conductive material is formed within the via over the solidified dielectric and a through substrate interconnect is formed with the conductive material.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: January 14, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Dave Pratt, Andy Perkins
  • Patent number: 8487426
    Abstract: A semiconductor package includes a conductive base, a die disposed adjacent to an upper surface of the conductive base, a patterned conductive layer, and a dielectric layer encapsulating the die. The dielectric layer defines an opening through which the patterned conductive layer is electrically connected to the upper surface of the conductive base. The conductive base has a lateral surface including a first portion adjacent to the upper surface of the conductive base and a second portion adjacent to a lower surface of the conductive base, where the second portion is sloped inwardly with respect to the lower surface of the conductive base.
    Type: Grant
    Filed: March 15, 2011
    Date of Patent: July 16, 2013
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Kay Stephan Essig, Bernd Karl Appelt, Ming Chiang Lee
  • Patent number: 8426253
    Abstract: An integrated circuit device includes a die, a lead, and an electrically-conductive structure that is arranged to facilitate electrical communication between the die and the lead. The device also includes a potting material, in which the electrically conductive structure, the die, and at least part of the lead are embedded. An electrically-conductive housing encases the potting material and forms exterior packaging of the device. During manufacturing, the electrically-conductive structure, the die, and at least part of the lead may be arranged within the electrically-conductive housing either before or after the potting material is disposed in the housing. When the integrated circuit device is operating, heat is removable from the die via a thermal conduction path formed by the electrically-conductive structure, the potting material, and the electrically-conductive housing.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: April 23, 2013
    Assignee: Vishay General Semiconductor LLC
    Inventors: Peter Chou, Lucy Tian, Ivan Fu, Samuel Li, May-Luen Chou
  • Patent number: 8421214
    Abstract: A semiconductor device mountable to a substrate is provided. The device includes a semiconductor package having at least one semiconductor die, an electrically conductive attachment region, and a packaging material in which is embedded the semiconductor die and a first portion of the electrically conductive attachment region contacting the die. A metallic shell encloses the embedded semiconductor die and the first portion of the electrically conductive attachment region.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: April 16, 2013
    Assignee: Vishay General Semiconductor LLC
    Inventors: Ta-Te Chou, Yong-Qi Tian, Xian Li
  • Patent number: 8399774
    Abstract: A substrate for suspension comprises a metallic substrate, an insulating layer formed on the metallic substrate, having an opening for grounding terminal, and a grounding conductor formed on the insulating layer. A grounding-terminal-forming material is placed in the opening for grounding terminal to form a grounding terminal that connects the metallic substrate and the grounding conductor. The grounding conductor does not surround a portion of the circumference of the opening for grounding terminal.
    Type: Grant
    Filed: November 23, 2011
    Date of Patent: March 19, 2013
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Yoichi Hitomi, Hiroaki Miyazawa, Shinji Kumon, Terutoshi Momose
  • Patent number: 8349659
    Abstract: The present invention integrates a shield on a flat, no-lead (FN) semiconductor package, which has multiple rows of contact pads along any side. The FN semiconductor package will have at least one inner row and one outer row of contact pads on at least one side. The inner and outer rows of contact pads and a die attach pad form the foundation for the FN semiconductor package. A die is mounted on the die attach pad and connected by wirebonds to certain contact pads of the inner rows of contact pads. An overmold body is formed over the die, die attach pad, wirebonds, and inner row of contact pads, and substantially encompasses each contact pad of the outer row of contact pads. A conformal coating is applied over the overmold body, including the exposed surfaces of the contact pads of the outer row of contact pads, providing a shield.
    Type: Grant
    Filed: July 21, 2011
    Date of Patent: January 8, 2013
    Assignee: RF Micro Devices, Inc.
    Inventors: Geoff Swan, Waite R. Warren, Jr.
  • Patent number: 8350378
    Abstract: A diode, e.g., a press-fit power diode for a rectifier in a motor vehicle, includes a semiconductor chip which is connected to a head wire and a base via solder layers. A plastic sheathing, which is situated at least in the chip area and includes a plastic sleeve, enables a hard casting compound to be used and establishes a mechanical connection between the base and the head wire and forms a housing together with the base. An undercut, which extends into the casting compound, and a gap between the sleeve and the edge of the base achieve a compact design. Bevels provided on both sides enable the diode to be pressed into the rectifier from two sides.
    Type: Grant
    Filed: November 8, 2004
    Date of Patent: January 8, 2013
    Assignee: Robert Bosch GmbH
    Inventors: Richard Spitz, Alfred Goerlach, Karin Hamsen, Jochen Dietrich
  • Patent number: 8344500
    Abstract: The present invention discloses an integrated circuit module and method of manufacturing the same. The integrated circuit module includes a chip and a carrier supporting the chip. The carrier defines a front side and a back side, and the chip is disposed on the front side. The carrier includes a first insulating layer defining a first opening at the back side, a second insulating layer defining a second opening and a chip accommodation opening at the front side, and a patterned conductive layer sandwiched in between the first insulating layer and the second insulating layer. The patterned conductive layer is formed with an inner contacting portion exposed through the chip accommodation opening and an outer contacting portion exposed through the first opening and the second opening. The inner contacting portion is connected to the chip through the chip accommodation opening.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: January 1, 2013
    Assignee: Mutual-Pak Technology Co., Ltd.
    Inventors: Lu-Chen Hwan, Po Ching Chen
  • Patent number: 8309388
    Abstract: A hermetic MEMS device (100) comprising a carrier (110) having a surface (111) including a device (101) and an attachment stripe (122), the stripe spaced from the device and surrounding the device; a metallic foil (102) having a central bulge portion (103) and a peripheral rim portion (104) meeting the stripe, the bulge cross section parallel to the carrier monotonically decreasing from the rim (104) towards the bulge apex (105); and the foil positioned over the carrier surface so that the bulge arches over the device and the rim forms a seal with the stripe.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: November 13, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Kurt P. Wachtler, Wei-Yan Shih, Gregory E. Howard
  • Patent number: 8253239
    Abstract: In one exemplary embodiment, a multi-chip connector is formed to have a first conductive strip that is suitable for attaching to a first semiconductor die and a second conductive strip that is attached suitable for attaching to a second semiconductor die.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: August 28, 2012
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Francis J. Carney, Phillip Celaya, Joseph K. Fauty, James P. Letterman, Stephen St. Germain, Jay A. Yoder
  • Patent number: 8198709
    Abstract: An integrated circuit device includes a die, a lead, and an electrically-conductive structure that is arranged to facilitate electrical communication between the die and the lead. The device also includes a potting material, in which the electrically conductive structure, the die, and at least part of the lead are embedded. An electrically-conductive housing encases the potting material and forms exterior packaging of the device. During manufacturing, the electrically-conductive structure, the die, and at least part of the lead may be arranged within the electrically-conductive housing either before or after the potting material is disposed in the housing. When the integrated circuit device is operating, heat is removable from the die via a thermal conduction path formed by the electrically-conductive structure, the potting material, and the electrically-conductive housing.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: June 12, 2012
    Assignee: Vishay General Semiconductor LLC
    Inventors: Peter Chou, Lucy Tian, Ivan Fu, Samuel Li, May-Luen Chou
  • Patent number: 8188597
    Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: May 29, 2012
    Assignee: International Business Machines Corporation
    Inventors: Thomas E. Lombardi, Donald Merte, Gregg B. Monjeau, David L. Questad, Son K. Tran
  • Patent number: 8188592
    Abstract: An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a heat sink plate and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the heat sink plate. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range.
    Type: Grant
    Filed: September 8, 2011
    Date of Patent: May 29, 2012
    Assignee: Infineon Technologies AG
    Inventors: Peter Nelle, Matthias Stecher
  • Publication number: 20120126246
    Abstract: According to one embodiment, provided is a package and high frequency terminal structure for the same including: a conductive base plate; a semiconductor device disposed on the conductive base plate; a metal wall disposed on the conductive base plate to house the semiconductor device; a through-hole disposed in input and output units of the metal wall; a lower layer feed through inserted into the through-hole and disposed on the conductive base plate; and an upper layer feed through disposed on the lower layer feed through, and adhered to a sidewall of the metal wall. The lower layer feed through is surrounded by the metal wall.
    Type: Application
    Filed: June 20, 2011
    Publication date: May 24, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kazutaka TAKAGI
  • Patent number: 8155663
    Abstract: A cellular telephone is provided with a wearable housing, desirably in a form which can be concealed in the user's clothing, wallet, or other place. The housing may be devoid of switches or buttons for controlling the cellular telephone, and control inputs can be provided through free space communications such as a short-range radio link. A module for use in portable communications devices includes chips superposed on one another on a stack, and incorporates an interposer for facilitating connections between the chips.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: April 10, 2012
    Assignee: Tessera, Inc.
    Inventors: Stuart E. Wilson, Ilyas Mohammed, Charles White, Hari Chakravarthula
  • Patent number: 8148804
    Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device electrically connects an electrode provided on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The metal substrate is provided on one side of the insulating layer. The copper wiring layer is provided on another side of the insulating layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode provided on the semiconductor chip. The second terminal is connected with the external wiring device.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: April 3, 2012
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Susumu Baba, Masachika Masuda, Hiromichi Suzuki
  • Publication number: 20120074559
    Abstract: An integrated circuit package including a package substrate, a metal lid mounted to the package substrate, and a stack of two or more integrated circuit chips electrically connected to each other by through substrate vias. The stack of two or more integrated circuit chips is disposed within the metal lid and electrically mounted to the package substrate. An inner surface of a top of the metal lid is electrically connected to ground wires in the package substrate by the through substrate vias. The TSVs provide electromagnetic interference shielding. A conductive thermal interface material may also be used. An alternative embodiment includes a single integrated circuit chip using TSVs to ground the metal lid.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy W. Budell, Mark C.H. Lamorey, Peter Slota, JR.
  • Patent number: 8125072
    Abstract: A device includes a semiconductor chip with a ring-shaped metal structure extending along the contour of a first main surface of the semiconductor chip. An encapsulation body encapsulates the semiconductor chip and defines a second main surface. An array of external contact pads attaches to the second main surface of the encapsulation body, and at least one external contact pad of the array of external contact pads electrically couples to the ring-shaped metal structure.
    Type: Grant
    Filed: August 13, 2009
    Date of Patent: February 28, 2012
    Assignee: Infineon Technologies AG
    Inventors: Rudolf Lachner, Josef Boeck, Klaus Aufinger, Herbert Knapp
  • Patent number: 8097811
    Abstract: A substrate for suspension comprises a metallic substrate, an insulating layer formed on the metallic substrate, having an opening for grounding terminal, and a grounding conductor formed on the insulating layer. A grounding-terminal-forming material is placed in the opening for grounding terminal to form a grounding terminal that connects the metallic substrate and the grounding conductor. The grounding conductor does not surround a portion of the circumference of the opening for grounding terminal.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: January 17, 2012
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Yoichi Hitomi, Hiroaki Miyazawa, Shinji Kumon, Terutoshi Momose
  • Patent number: 8053872
    Abstract: The present invention integrates a shield on a flat, no-lead (FN) semiconductor package, which has multiple rows of contact pads along any side. The FN semiconductor package will have at least one inner row and one outer row of contact pads on at least one side. The inner and outer rows of contact pads and a die attach pad form the foundation for the FN semiconductor package. A die is mounted on the die attach pad and connected by wirebonds to certain contact pads of the inner rows of contact pads. An overmold body is formed over the die, die attach pad, wirebonds, and inner row of contact pads, and substantially encompasses each contact pad of the outer row of contact pads. A conformal coating is applied over the overmold body, including the exposed surfaces of the contact pads of the outer row of contact pads, providing a shield.
    Type: Grant
    Filed: June 25, 2007
    Date of Patent: November 8, 2011
    Assignee: RF Micro Devices, Inc.
    Inventors: Geoff Swan, Waite R. Warren, Jr.
  • Patent number: 8053787
    Abstract: A lamp seat includes a metal substrate having opposite first and second surfaces, first and second conductive patterns formed on the first surface, and third and fourth conductive patterns formed on the second surface and connected respectively and integrally to the first and second conductive patterns. A heat-conductive first insulating layer is disposed between the metal substrate and each of the first, second, third and fourth conductive patterns. A heat-conductive second insulating layer is formed over the first insulating layer such that corresponding parts of the first and second conductive patterns are exposed outwardly of the second insulating layer for electrical connection with positive and negative electrodes of a light emitting diode, respectively.
    Type: Grant
    Filed: November 21, 2007
    Date of Patent: November 8, 2011
    Inventor: Wen-Chin Shiau
  • Patent number: 8017434
    Abstract: Various methods and apparatus for holding a semiconductor chip package are disclosed. In one aspect, a method of manufacturing is provided that includes forming a first plate adapted to hold a semiconductor chip package. The semiconductor chip package includes a carrier substrate and at least one semiconductor chip coupled to the carrier substrate. A second plate is formed with a first opening defining an interior peripheral surface adapted to compress an outer edge of the carrier substrate between the first plate and the second plate without engaging the at least one semiconductor chip.
    Type: Grant
    Filed: November 24, 2008
    Date of Patent: September 13, 2011
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Kevin W. Lim, Seah S. Too, Azlina N. Nayan, Kee Hean Keok, Soon Tatt Ow Yong
  • Patent number: 8013433
    Abstract: A virtual wire assembly that includes a substantially electrically-nonconductive substrate and a plurality of hermetic feedthroughs including a conductive region extending transversely through the substrate to form a conductive pathway with accessible surfaces at opposing ends thereof, wherein each conductive pathway is electrically isolated from other conductive pathways. In certain embodiments of this aspect of the invention, the substantially electrically-nonconductive substrate is a semiconductor device, and the conductive regions each include an n-type or a p-type doped semiconductor material.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: September 6, 2011
    Assignee: Cochlear Limited
    Inventors: James Dalton, Peter Single, David Money
  • Patent number: 7982293
    Abstract: A lead frame assembly includes at least one die paddle. The die paddle includes a first landing area for receiving a first semiconductor chip and a second landing area for receiving a second semiconductor chip. One or more steps are provided between the first landing area and the second landing area.
    Type: Grant
    Filed: May 1, 2009
    Date of Patent: July 19, 2011
    Assignee: Infineon Technologies AG
    Inventors: Wei Kee Chan, Weng Shyan Aik
  • Patent number: 7964957
    Abstract: A semiconductor device that includes a metal substrate including a top surface, a bottom surface and four side surfaces, a conductive pattern insulated from the metal substrate, and a semiconductor element mounted on and electrically connected to the conductive pattern. The top surface is insulated. Each of the side surfaces of the metal substrate includes a first inclining side surface and a second inclining side surface so as to form a convex shape protruding outwardly between the top surface and the bottom surface of the metal substrate, and the first inclining side surfaces of a pair of two opposing side surfaces are smaller than corresponding first inclining side surfaces of another pair of two opposing side surfaces.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: June 21, 2011
    Assignees: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.
    Inventors: Mitsuru Noguchi, Sadamichi Takakusaki
  • Patent number: 7948065
    Abstract: A system and method is disclosed for providing an integrated circuit that has increased radiation hardness and reliability. A device active area of an integrated circuit is provided and a layer of radiation resistant material is applied to the device active area of the integrated circuit. In one advantageous embodiment the radiation resistant material is silicon carbide. In another advantageous embodiment a passivation layer is placed between the device active area and the layer of radiation resistant material. The integrated circuit of the present invention exhibits minimal sensitivity to (1) enhanced low dose rate sensitivity (ELDRS) effects of radiation, and (2) pre-irradiation elevated temperature stress (PETS) effects of radiation.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: May 24, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Michael C. Maher
  • Patent number: 7915726
    Abstract: Substrates for mounting microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices are disclosed herein. A method of manufacturing a substrate in accordance with one embodiment of the invention includes forming a conductive trace on a first side of a sheet of non-conductive material, and forming a via through the non-conductive material from a second side of the sheet to the conductive trace. The method further includes removing a section of the non-conductive material to form an edge of the non-conductive material extending across at least a portion of the via. In one embodiment, forming the edge across the via exposes at least a portion of the second conductive trace for subsequent attachment to a terminal on a microelectronic die.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: March 29, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Chin Hui Chong, Choon Kuan Lee, David J. Corisis
  • Patent number: 7906841
    Abstract: A wafer level encapsulation chip and an encapsulation chip manufacturing method. The encapsulation chip includes a device substrate, a circuit module mounted on the device substrate, a bonding layer deposited on a predetermined area of the device substrate, a protection cap forming a cavity over the circuit module and bonded to the device substrate by the bonding layer and encapsulation portions formed on predetermined areas of the bonding layer and the protection cap. Thus, the present invention can minimize damages to a chip upon chip handling and prevent moisture from being introduced into the inside of the chip.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: March 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-gil Jeong, In-sang Song, Woon-bae Kim, Min-seog Choi, Suk-jin Ham, Ji-hyuk Lim
  • Patent number: 7847379
    Abstract: A through-silicon via stack package contains package units. Each package unit includes a semiconductor chip; a through-silicon via formed in the semiconductor chip; a first metal line formed on an upper surface and contacting a portion of a top surface of the through-silicon via; and a second metal line formed on a lower surface of the semiconductor chip and contacting a second portion of a lower surface of the through-silicon via. When package units are stacked, the second metal line formed on the lower surface of the top package unit and the first metal line formed on the upper surface of the bottom package unit are brought into contact with the upper surface of the through-silicon via of the bottom package unit and the lower surface of the through-silicon via of the top package unit, respectively. The stack package is lightweight and compact, and can form excellent electrical connections.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: December 7, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Qwan Ho Chung
  • Patent number: 7772688
    Abstract: The present invention relates to an electronic circuit unit having at least one semiconductor (15), that is situated on a substrate, and whose electrical connections are in electrical contact with printed circuit traces of the substrate, and having a housing, that accommodates the substrate, which has contact paths which are connected to the printed circuit traces of the substrate using electrical connections. It is provided that the electrical connections (20) each have a contact surface (17) situated on the substrate (12) which, when the substrate (12) and the housing (2) are joined together, comes to lie in an opposing position to the counter-contact surfaces (19) of the contact paths (21). The present invention also relates to a corresponding manufacturing method.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: August 10, 2010
    Assignee: Robert Bosch GmbH
    Inventors: Eric Ochs, Christoph Ruf
  • Patent number: 7737463
    Abstract: Disclosed is a light emitting diode (LED) package having multiple molding resins. The LED package includes a pair of lead terminals and a heat sink inserted into a heat sink support ring. At least portions of the pair of lead terminals and the heat sink are embedded in a package main body. The package main body has an opening through which the pair of lead terminals is exposed. An LED die is mounted in the opening and electrically connected to the pair of lead terminals. A first molding resin covers the LED die. A second molding resin with higher hardness than the first molding covers the first molding resin. Therefore, stress to be imposed on the LED die can be reduced and the deformation of the molding resins can be prevented.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: June 15, 2010
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventors: Chung Hoon Lee, Do Hyung Kim, Keon Young Lee
  • Patent number: 7719104
    Abstract: The present invention provides a circuit board structure with an embedded semiconductor chip and a method for fabricating the same. The circuit board structure includes a carrier board having a first surface, a second surface, and a through hole penetrating the carrier board from the first surface to the second surface; a semiconductor chip having an active surface whereon a plurality of electrode pads are formed and a non-active surface, embedded in the through hole; a photosensitive first dielectric layer formed on the first surface of the carrier board and an opening formed thereon to expose the non-active surface of the semiconductor chip; a photosensitive second dielectric layer formed on the second surface of the carrier board and the active surface of the semiconductor chip.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: May 18, 2010
    Assignee: Phoenix Precision Technology Corporation
    Inventors: Shih-Ping Hsu, Shang-Wei Chen
  • Patent number: 7701054
    Abstract: A power semiconductor module 3 for mounting on a cooling element 4 has at least one substrate 2, on which one or more components 5, 6, 7 are mounted and a module housing 40. The module housing 40 surrounds at least partially the at least one substrate 2. The module housing 40 has opposite sides with a first side facing the cooling element 4, and a second side 42 having one or more openings and a surface turned away from the power semiconductor module 3. Each of the one or more openings has a border, which is sealed by an internal contact 16, 17, 18, 27, 28, which is electrically connected to the one or more components 5, 6, 7. The internal contact protrudes the module housing 40, such that the internal contact not extends beyond said surface of the second side 42 of the module housing 40.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: April 20, 2010
    Assignee: Infineon Technologies AG
    Inventors: Thilo Stolze, Klaus Schiess, Peter Kanschat
  • Patent number: 7692299
    Abstract: A semiconductor apparatus having improved thermal fatigue life is provided by lowering maximum temperature on jointing members and reducing temperature change. A jointing member is placed between a semiconductor chip and a lead electrode, and a thermal stress relaxation body is arranged between the chip and a support electrode. Jointing members are placed between the thermal stress relaxation body and the chip and between the thermal stress relaxation body and the support electrode. A second thermal stress relaxation body made from a material having a thermal expansion coefficient between the coefficients of the chip and the lead electrode is located between the chip and the lead electrode. The first thermal stress relaxation body is made from a material which has a thermal expansion coefficient in between the coefficients of the chip and the support electrode, and has a thermal conductivity of 50 to 300 W/(m·° C.).
    Type: Grant
    Filed: August 7, 2007
    Date of Patent: April 6, 2010
    Assignees: Hitachi Haramachi Electronics Co., Ltd., Hitachi, Ltd.
    Inventors: Chikara Nakajima, Takeshi Kurosawa, Megumi Mizuno
  • Patent number: 7659613
    Abstract: A frame-shaped sidewall is provided on a metallic base plate surrounding a semiconductor element arranged on the metallic base plate, which is provided with a stepped surface positioned at lower level at a portion of the base plate than a main surface of the base plate. A first dielectric plate is arranged on one side of the semiconductor element and a first circuit pattern is formed on its surface, a second dielectric plate is arranged on another side of the semiconductor element and a second circuit pattern is formed on the first and the second dielectric plate. An insulator is mounted on the stepped surface of the base plate, which forms a part of the sidewall. Power supply portions are provided including a band-shaped conductor. An interconnection is provided which connects the band-shaped conductor to the circuit pattern.
    Type: Grant
    Filed: June 12, 2008
    Date of Patent: February 9, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 7642640
    Abstract: The semiconductor device according to one of the embodiments of the present invention includes a metal block having first and second main surfaces and defining a recess on the first main surface. It also includes a semiconductor chip received within the recess of the metal block and mounted on the metal block. Further, a first terminal electrically connected with the semiconductor chip is provided, and a second terminal electrically connected with the metal block is also provided.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: January 5, 2010
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Toshiaki Shinohara
  • Publication number: 20090294953
    Abstract: The present invention discloses an integrated circuit module and method of manufacturing the same. The integrated circuit module includes a chip and a carrier supporting the chip. The carrier defines a front side and a back side, and the chip is disposed on the front side. The carrier includes a first insulating layer defining a first opening at the back side, a second insulating layer defining a second opening and a chip accommodation opening at the front side, and a patterned conductive layer sandwiched in between the first insulating layer and the second insulating layer. The patterned conductive layer is formed with an inner contacting portion exposed through the chip accommodation opening and an outer contacting portion exposed through the first opening and the second opening. The inner contacting portion is connected to the chip through the chip accommodation opening.
    Type: Application
    Filed: May 26, 2009
    Publication date: December 3, 2009
    Applicant: MUTUAL-PAK TECHNOLOGY CO., LTD.
    Inventors: Lu-Chen Hwan, Po Ching Chen
  • Patent number: 7598610
    Abstract: A plate structure having a chip embedded therein, comprises an aluminum plate having at least one aluminum oxide layer formed on its surface, and a cavity therein; a chip embedded in the cavity, wherein the chip has an active surface; at least one electrode pad mounted on the active surface; and a build-up structure mounted on the surface of the aluminum plate, the active surface of the chip, and the surface of the electrode pad, wherein the build-up structure comprises at least one conducting to electrically connect to the electrode pad. Besides, a method of manufacturing a plate structure having a chip embedded therein is disclosed. Therefore, the plate structure having a chip embedded therein can be processed by a simple method to achieve the tenacity of aluminum and the rigidity of aluminum oxide.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: October 6, 2009
    Assignee: Phoenix Precision Technology Corporation
    Inventors: Shih-Ping Hsu, Chung-Cheng Lien, Kan-Jung Chia, Shang-Wei Chen