Multiple Contact Layers Separated From Each Other By Insulator Means And Forming Part Of A Package Or Housing (e.g., Plural Ceramic Layer Package) Patents (Class 257/700)
  • Patent number: 11217530
    Abstract: A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer including an inorganic film located on the lower layer Cu line and an organic resin film located on the inorganic film, and a via connection part located in a via connection hole running in an up-down direction through the insulating layer in an area where the lower layer Cu line and the upper layer Cu line overlap each other is provided. The via connection part includes a barrier conductive layer located on a part of the lower layer Cu line exposed to a bottom part of the via connection hole and on an inner wall of the via connection hole.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 4, 2022
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Hiroshi Kudo, Takamasa Takano
  • Patent number: 11217551
    Abstract: A manufacturing method of a chip package structure is provided. A carrier board with an accommodating cavity, a substrate, and a stainless steel layer sputtered on the substrate is disposed. A chip is disposed in the accommodating cavity of the carrier board. The chip has an active surface, a back surface opposite to the active surface, and multiple electrodes disposed on the active surface. A circuit structure layer is formed on the carrier board. The circuit structure layer includes a patterned circuit and multiple conductive vias. The patterned circuit is electrically connected to the electrodes of the chip through the conductive vias. An encapsulant is formed to cover the active surface of the chip and the circuit structure layer. The active surface of the chip and a bottom surface of the encapsulant are coplanar. The carrier board is removed to expose the chip disposed in the accommodating cavity.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: January 4, 2022
    Inventor: Chung W. Ho
  • Patent number: 11183621
    Abstract: A component may include a semiconductor chip, a buffer layer, a connecting layer, and a metal carrier. The semiconductor chip may include a substrate and a semiconductor body arranged thereon. The metal carrier may have a thermal expansion coefficient at least 1.5 times as great as a thermal expansion coefficient of the substrate or of the semiconductor chip. The chip may be fastened on the metal carrier by the connecting layer, and the buffer layer may have a yield stress ranging from 10 MPa. The buffer layer may have a thickness ranging from 2 um to 10 um and adjoin the chip. The substrate and the metal carrier may have a higher yield strength than the buffer layer.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: November 23, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Paola Altieri-Weimar, Ingo Neudecker, Andreas Ploessl, Marcus Zenger
  • Patent number: 11177207
    Abstract: A transistor includes a semiconductor substrate having a first terminal and a second terminal. An interconnect structure is formed on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material. The electrically conductive material of the interconnect structure includes a pillar in electrical contact with the first terminal, a first runner electrically connected to the pillar, a tap interconnect in electrical contact with the second terminal, a second runner electrically connected to the tap interconnect, a shield structure positioned between the pillar and the tap interconnect, and a shield runner electrically connected to the shield structure, the shield runner overlying the second runner in a direction perpendicular to the upper surface of the semiconductor substrate.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: November 16, 2021
    Assignee: NXP USA, Inc.
    Inventors: Vikas Shilimkar, Kevin Kim, Charles John Lessard, Humayun Kabir
  • Patent number: 11164804
    Abstract: An IC device package includes a carrier, one or more IC devices and a lid. The lid includes a lid-ridge. The lid is connected to the carrier by connecting the lid-ridge to the carrier with first nano particle metallic paste, prior to connecting the IC device to the carrier. Subsequent to connecting the IC device to the carrier, the lid is connected to the lid-ridge with second nano particle metallic paste. The nano particle metallic paste may be sintered to form a metallic connection. In multi-IC device packages, the lid-ridge may be positioned between the lid and the carrier and between the IC devices.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Kevin Drummond, Luca Del Carro, Thomas Brunschwiler, Stephanie Allard, Kenneth C. Marston, Marcus E. Interrante
  • Patent number: 11166386
    Abstract: An interposer substrate includes a dielectric portion, a magnetic portion, and a first principal surface and a second principal surface opposite to each other. Connection terminal electrodes are each provided on a corresponding one of first principal surfaces of the dielectric portion and the magnetic portion, and are connected to a cable. Circuit-board terminal electrodes are provided on a second principal surface of the dielectric portion and connected to a circuit board. Wiring electrodes are provided inside a base body, and connecting the connection terminal electrodes to the circuit-board terminal electrodes in a predetermined connection pattern. The wiring electrodes include a first wiring electrode passing through only the dielectric portion, and a second wiring electrode passing through the magnetic portion.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: November 2, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Keito Yonemori, Hirokazu Yazaki, Takanori Tsuchiya, Koji Kamada
  • Patent number: 11147851
    Abstract: A method of fabricating an electronic power module by additive manufacturing, the electronic module including a substrate having an electrically insulating plate presenting opposite first and second faces, with a first metal layer arranged directly on the first face of the insulating plate, and a second metal layer arranged directly on the second face of the insulating plate. At least one of the metal layers is made by a step of depositing a thin layer of copper and a step of annealing the metal layer, and the method further includes a step of forming at least one thermomechanical transition layer on at least one of the first and second metal layers, the at least one thermomechanical transition layer including a material presenting a coefficient of thermal expansion that is less than that of the metal of the metal layer.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: October 19, 2021
    Assignee: SAFRAN
    Inventors: Rabih Khazaka, St├ęphane Azzopardi, Donatien Henri Edouard Martineau
  • Patent number: 11134030
    Abstract: Techniques and mechanisms for interconnecting network circuitry of an integrated circuit (IC) die and physical layer (PHY) circuits of the same IC die. In an embodiment, nodes of the network circuitry include first routers and processor cores, where the first routers are coupled to one another in an array configuration which includes rows and columns. First interconnects each extend to couple both to a corresponding one of the PHY circuits and to a corresponding one of the first routers. For each of one or more of the first interconnects, a respective one or more rows (or one or more columns) of the array configuration extend between the corresponding PHY and the corresponding router. In another embodiment, the network circuitry comprises network clusters which each include a different respective row of the array configuration.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Akhilesh Kumar, Surhud Khare
  • Patent number: 11127706
    Abstract: An electronic package and method includes a substrate including a plurality of pads on a major surface. An electronic component including a plurality of pads on a major surface facing the major surface of the substrate. A stud bump electrically couples one of the plurality of pads of the substrate to one of the plurality of pads of the electronic component.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation
    Inventors: Zhaozhi Li, Sanka Ganesan, Debendra Mallik, Gregory Perry, Kuan H. Lu, Omkar Karhade, Shawna M. Liff
  • Patent number: 11121099
    Abstract: A semiconductor device includes a heat sink, an integrated component in which a ceramic terminal having a microstrip line and a matching circuit are integrated into one unit, a lead fixed to the ceramic terminal, a matching substrate fixed to the heat sink, a semiconductor chip fixed to the heat sink, a plurality of wires configured to connect the matching circuit and the matching substrate and to connect electrically the matching substrate and the semiconductor chip, a frame configured to surround the matching substrate and the semiconductor chip in a plan view, and a cap provided on the frame.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: September 14, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masayasu Ito, Katsumi Miyawaki, Hiroaki Ichinohe, Takashi Tsurumaki
  • Patent number: 11114355
    Abstract: A power module includes a power wiring line provided with a power element, a glass ceramic multilayer substrate provided with a control element to control the power element, and a highly heat-conductive ceramic substrate made of a ceramic material having higher thermal conductivity than a glass ceramic contained in the glass ceramic multilayer substrate. The power wiring line is disposed on the highly heat-conductive ceramic substrate, and the glass ceramic multilayer substrate is disposed directly on the highly heat-conductive ceramic substrate.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: September 7, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takahiro Hayakawa, Yasutaka Sugimoto, Tomoki Kato, Yoichi Moriya
  • Patent number: 11101236
    Abstract: A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu Huang, Li-Chung Kuo, Sung-Hui Huang, Shang-Yun Hou, Tsung-Yu Chen, Chien-Yuan Huang
  • Patent number: 11101252
    Abstract: A package-on-package structure including a first and second package is provided. The first package includes a semiconductor die, through insulator vias, an insulating encapsulant, conductive terminals and a redistribution layer. The semiconductor die has a die height H1. The plurality of through insulator vias is surrounding the semiconductor die and has a height H2, and H2<H1. The insulating encapsulant is encapsulating the semiconductor die and the plurality of through insulator vias, wherein the insulating encapsulant has a plurality of via openings revealing each of the through insulator vias. The plurality of conductive terminals is disposed in the via openings and electrically connected to the plurality of through insulator vias. The redistribution layer is disposed on the active surface of the semiconductor die and over the insulating encapsulant. The second package is stacked on the first package and electrically connected to the plurality of conductive terminals of the first package.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ting Lin, Chin-Fu Kao, Jing-Cheng Lin, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11094649
    Abstract: Present disclosure provides a semiconductor package structure, which includes a redistribution layer (RDL) structure, an electronic device, a first reinforcement structure, a second reinforcement structure, and an encapsulant. The RDL structure has a passivation layer and a patterned conductive layer disposed in the passivation layer. The electronic device is disposed on the RDL structure. The first reinforcement structure is disposed on the RDL structure and has a first modulus. The second reinforcement structure is disposed on the first reinforcement structure and has a second modulus substantially less than the first modulus. The encapsulant is disposed on the RDL structure and encapsulates the electronic device, the first reinforcement structure and the second reinforcement structure.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: August 17, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Fan-Yu Min, Chen-Hung Lee, Hsiu-Chi Liu, Liang-Chun Chen
  • Patent number: 11088047
    Abstract: A hermetic ceramic package for high current signals includes a substrate made of a plurality of ceramic green sheets that form an upper body portion having an upper surface and a lower body portion having a lower surface and an intermediate surface between the upper surface and the lower surface. A first conductive plate is formed on the intermediate surface and a first plurality of conductive pad vias are formed in the lower body portion, extending from the first conductive plate to the lower surface of the lower body portion. A heat sink if coupled to the lower surface of the lower body portion and a first conductive pad also coupled to the lower surface such that the first conductive pad is electrically coupled to the first plurality of conductive pad vias.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: August 10, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Joao Carlos Felicio Brito, Javier Antonio Valle Mayorga, Hector Torres
  • Patent number: 11076488
    Abstract: A board having an electronic component embedded therein, includes a core layer having a groove with a bottom surface, an electronic component disposed above the bottom surface of the groove and spaced apart from the bottom surface of the groove, and an insulating layer disposed on the core layer and covering at least a portion of the electronic component. The insulating layer is disposed in at least a portion of a space between the bottom surface of the groove and the electronic component.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: July 27, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ho Hyung Ham, Jae Sung Sim
  • Patent number: 11063007
    Abstract: A semiconductor device and manufacturing process are provided wherein a first semiconductor device is electrically connected to redistribution structures. An antenna structure is located on an opposite side of the first semiconductor device from the redistribution structures, and electrical connections separate from the first semiconductor device connect the antenna structure to the redistribution structures.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yao Chuang, Po-Hao Tsai, Shin-Puu Jeng
  • Patent number: 11063016
    Abstract: A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die, encapsulating the voltage regulator die in an encapsulating material, and planarizing the encapsulating material. A back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die. The method further includes forming first redistribution lines over the encapsulating material and electrically coupled to the through-via, replacing the die-attach film with a dielectric material, forming second redistribution lines on an opposite side of encapsulating material than the first redistribution lines, and bonding an additional device die to the second redistribution lines. The voltage regulator die is electrically coupled to the additional device die.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chih-Yuan Chang, Chuei-Tang Wang, Jeng-Shien Hsieh
  • Patent number: 11049782
    Abstract: A fan-out semiconductor package includes a frame including a plurality of wiring layers electrically connected to each other and having a recess portion having a bottom surface on which a stopper layer is disposed, a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, the inactive surface being disposed in the recess portion to face the stopper layer, an encapsulant covering at least a portion of the frame and at least a portion of the semiconductor chip, the encapsulant being disposed in at least a portion of the recess portion, and a connection structure disposed on the frame and the active surface and including a redistribution layer electrically connected to the plurality of wiring layers and the connection pad. A thickness of the stopper layer is greater than a thickness of each of the plurality of wiring layers.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: June 29, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hanul Lee, Younggwan Ko
  • Patent number: 11037861
    Abstract: An interconnect structure and a method of forming an interconnect structure are provided. The interconnect structure is formed over a carrier substrate, upon which a die may also be attached. Upon removal of the carrier substrate and singulation, a first package is formed. A second package may be attached to the first package, wherein the second package may be electrically coupled to through vias formed in the first package.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Pin Hung, Jing-Cheng Lin, Po-Hao Tsai, Yi-Jou Lin, Shuo-Mao Chen, Chiung-Han Yeh, Der-Chyang Yeh
  • Patent number: 11031328
    Abstract: A semiconductor package includes: an interposer substrate including a core substrate and a connection structure, the core substrate having a cavity and having through-vias connecting upper and lower surfaces thereof, and the connection structure including an insulating member on the upper surface and a redistribution layer on the insulating member; a semiconductor chip on an upper surface of the connection structure and including connection pads connected to the redistribution layer; a passive component accommodated in the cavity; a first insulating layer disposed between the core substrate and the connection structure; a first wiring layer on the first insulating layer and connecting the through-vias and the passive component to the redistribution layer; a second insulating layer on the lower surface of the core substrate; and a second wiring layer on a lower surface of the second insulating layer and connected to the through-vias.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junghyun Cho, Youngsik Hur, Youngkwan Lee, Jongrok Kim
  • Patent number: 11031337
    Abstract: Techniques are provided to fabricate metallic interconnect structures in a single metallization level, wherein different width metallic interconnect structures are formed of different metallic materials to eliminate or minimize void formation in the metallic interconnect structures. For example, a semiconductor device includes an insulating layer disposed on a substrate, and a first metallic line and a second metallic line formed in the insulating layer. The first metallic line has a first width, and the second metallic line has a second width which is greater than the first width. The first metallic line is formed of a first metallic material, and the second metallic line is formed of a second metallic material, which is different from the first metallic material. For example, the first metallic material is cobalt or ruthenium, and the second metallic material is copper.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: June 8, 2021
    Assignee: International Business Machines Corporation
    Inventors: Hari P. Amanapu, Charan V. Surisetty, Raghuveer R. Patlolla
  • Patent number: 11031351
    Abstract: A method includes forming an insulating film over a semiconductor structure, forming a sealing ring over a sidewall of the insulating film, and forming a protective layer over an exposed sidewall of the sealing ring. The semiconductor structure includes a semiconductor chip and a molding compound disposed around the semiconductor chip. The exposed sidewall of the sealing ring faces away from the sidewall of the insulating film.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: June 8, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zi-Jheng Liu, Jo-Lin Lan, Yu-Hsiang Hu, Hung-Jui Kuo
  • Patent number: 11024556
    Abstract: A semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface; a heat dissipation member disposed on the inactive surface of the semiconductor chip and including a graphite material; an adhesive member disposed between the semiconductor chip and the heat dissipation member; an encapsulant covering at least a portion of each of the semiconductor chip and the heat dissipation member; and an interconnect structure disposed on the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pad. The encapsulant covers at least a portion of aside surface of the adhesive member.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: June 1, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Sang Hyun Kwon, Hyung Kyu Kim, Seong Chan Park, Hye Lee Kim, Choon Keun Lee
  • Patent number: 10994677
    Abstract: The invention relates to a busbar (1) arranged so as to electrically connect at least one power electronic module (13) from at least one electrical conductor (6) to which the busbar (1) can be connected. The busbar (1) comprises a plurality of coaxial sleeves (2). Each of the sleeves (2) comprises a plurality of arms (4) that are distributed peripherally and radially around an axis (A) of the sleeves (2). The arms (4) extend longitudinally in parallel to the axis (A) and each include at least one conductive track (5) forming one of the buses of the busbar (1). The invention also relates to a power electronic module incorporating a busbar in accordance with the invention, and to a vehicle fitted with said module.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: May 4, 2021
    Assignee: INSTITUT VEDECOM
    Inventor: Guy Diemunsch
  • Patent number: 10978417
    Abstract: A wiring structure includes an upper conductive structure, a lower conductive structure and an intermediate layer. The upper conductive structure includes at least one upper dielectric layer and at least one upper circuit layer in contact with the dielectric layer. The lower conductive structure includes at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer. The at least one lower dielectric layer of the lower conductive structure is substantially free of glass fiber. The intermediate layer is disposed between the upper conductive structure and the lower conductive structure and bonds the upper conductive structure and the lower conductive structure together. The upper conductive structure is electrically connected to the lower conductive structure.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: April 13, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen Hung Huang
  • Patent number: 10980125
    Abstract: A printed circuit board includes a first core layer having a first coil pattern disposed on one surface of the first core layer, a second core layer disposed on the one surface of the first core layer and having a first recess, a first magnetic member disposed in the first recess and including a first magnetic layer, a first insulating layer disposed between the first and second core layers, and a second insulating layer disposed on the second core layer, covering at least a portion of the first magnetic member, and disposed in at least a portion of the first recess.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: April 13, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Woong Choi, Ki Jung Sung, Tae Seong Kim
  • Patent number: 10978405
    Abstract: An integrated fan-out (InFO) package includes an encapsulant, a die, a plurality of conductive structures, and a redistribution structure. The die and the conductive structures are encapsulated by the encapsulant. The conductive structures surround the die. The redistribution structure is disposed on the encapsulant. The redistribution structure includes a plurality of routing patterns, a plurality of conductive vias, and a plurality of alignment marks. The conductive vias interconnects the routing patterns. At least one of the alignment mark is in physical contact with the encapsulant.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jhih-Yu Wang, Hung-Jui Kuo, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 10910336
    Abstract: A chip package structure, comprises a first chip having a plurality of first chip joints at a lower side thereof; a circuit board below the first chip; an upper side of the circuit board being arranged with a plurality of circuit board joints; in packaging, the first chip joints being combined with the circuit board joints of the circuit board so that the first chip is combined to the circuit board by a way of ACF combination or convex joint combination; and wherein in the ACF combination, ACFs are used as welding points to be combined to the pads at another end so that the chip is combined to the circuit board; and wherein in the convex pad combination, a convex pad is combined with a flat pad by chemically methods or physical methods; and these pads are arranged on the circuit board and the first chip.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: February 2, 2021
    Inventor: Shih-Chi Chen
  • Patent number: 10910465
    Abstract: In described examples, a method for fabricating a semiconductor device and a three dimensional structure, and packaging them together, includes: fabricating the integrated circuit on a substrate, immersing the substrate in a liquid encapsulation material, and illuminating the liquid encapsulation material to polymerize the liquid encapsulation material. Immersing the semiconductor device is performed to cover a layer of a platform in the liquid encapsulation material. The platform is a lead frame, a packaging substrate, or the substrate. The illuminating step targets locations of the liquid encapsulation material covering the layer. Illuminated encapsulation material forms solid encapsulation material that is fixedly coupled to contiguous portions of the semiconductor device and of the solid encapsulation material. The immersing and illuminating steps are repeated until a three dimensional structure is formed. The integrated circuit and the three dimensional structure are encapsulated in a single package.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: February 2, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Benjamin Stassen Cook, Daniel Lee Revier
  • Patent number: 10905005
    Abstract: A wiring board includes a first interconnect layer, a first insulating layer covering the first interconnect layer, a second interconnect layer, thinner than the first interconnect layer, formed on the first insulating layer and having an interconnect density higher than that of the first interconnect layer, and a second insulating layer formed on the first insulating layer and covering the second interconnect layer. The first insulating layer includes a first layer including no reinforcing material, and a second layer including a reinforcing material. The first and second layers include a non-photosensitive thermosetting resin as a main component thereof. The first layer has a coefficient of thermal expansion higher than that of the second layer, and the second insulating layer includes a photosensitive resin as a main component thereof. The second interconnect layer includes an interconnect formed directly on and electrically connected to the first interconnect layer.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: January 26, 2021
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Hiroshi Taneda, Yukari Chino
  • Patent number: 10897812
    Abstract: A component carrier and a method of manufacturing the same are disclosed. The component carrier has a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, and a component embedded in the stack. Sidewalls of the component are directly covered with an electrically conductive layer. The component carrier achieves enhanced thermal dissipation and EMI shielding characteristics and has an improved stiffness.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: January 19, 2021
    Assignee: AT&S (Chongqing) Company Limited
    Inventor: Minwoo Lee
  • Patent number: 10892233
    Abstract: Moisture-driven degradation of a crack stop in a semiconductor die is mitigated by forming a groove in an upper surface of the die between an edge of the die and the crack stop; entirely filling the groove with a moisture barrier material; preventing moisture penetration of the semiconductor die by presence of the moisture barrier material; and dissipating mechanical stress in the moisture barrier material without presenting a stress riser in the bulk portion of the die. The moisture barrier material is at least one of moisture-absorbing, moisture adsorbing, and hydrophobic.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: January 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sushumna Iruvanti, Shidong Li, Steve Ostrander, Jon Alfred Casey, Brian Richard Sundlof
  • Patent number: 10893617
    Abstract: A multilayer substrate includes a plurality of insulator layers laminated, a column conductor extending through two or more insulator layers among the plurality of insulator layers. The column conductor includes a first via conductor extending through a first insulator layer and a second via conductor extending through a second insulator layer adjacent to the first insulator layer. Each of the first via conductor and the second via conductor has a tapered shape in which a cross section decreases from one end portion to the other end portion in the lamination direction of the plurality of insulator layers. The first via conductor and the second via conductor are directly bonded to each other at large diameter portions that are end portions with a large cross section or small diameter portions that are end portions with a small cross section.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: January 12, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Saneaki Ariumi
  • Patent number: 10879198
    Abstract: A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Jung Yang, Hsien-Wei Chen, Hsien-Ming Tu, Chang-Pin Huang, Yu-Chia Lai, Tung-Liang Shao
  • Patent number: 10861827
    Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Chung-Shi Liu, Chih-Wei Lin, Hui-Min Huang, Hsuan-Ting Kuo, Ming-Da Cheng
  • Patent number: 10854550
    Abstract: The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: December 1, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Sheng-Ming Wang, Tien-Szu Chen, Wen-Chih Shen, Hsing-Wen Lee, Hsiang-Ming Feng
  • Patent number: 10840197
    Abstract: A package structure includes a first redistribution circuit structure, a second redistribution circuit structure, a semiconductor die, a waveguide structure, and an antenna. The semiconductor die is sandwiched between and electrically coupled to the first redistribution circuit structure and the second redistribution circuit structure. The waveguide structure is located aside and electrically coupled to the semiconductor die, wherein the waveguide structure includes a part of the first redistribution circuit structure, a part of the second redistribution circuit structure and a plurality of first through vias each connecting to the part of the first redistribution circuit structure and the part of the second redistribution circuit structure. The antenna is located on the semiconductor die, wherein the second redistribution circuit structure is sandwiched between the antenna and the semiconductor die, and the antenna is electrically communicated with the semiconductor die through the waveguide structure.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sen-Kuei Hsu, Hsin-Yu Pan
  • Patent number: 10790264
    Abstract: A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: September 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-seok Hong, Jin-woo Park
  • Patent number: 10784403
    Abstract: A glass wiring substrate includes a glass substrate, a first wiring portion being formed on a first surface of the glass substrate, a second wiring portion being formed on a second surface opposite to the first surface; a through-hole formed in a region of the glass substrate in which the first wiring portion and the second wiring portion are not formed, the through-hole having a diameter on a second surface side larger than a diameter on a first surface side; and a through-hole portion formed in the through-hole, one end portion of the through-hole portion extending to the first wiring portion, the other end portion of the through-hole portion extending to the second wiring portion, in which a wiring pitch P1 of the first wiring portion in the vicinity of the through-hole portion is narrower than a wiring pitch P2 of the second wiring portion in the vicinity of the through-hole portion.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: September 22, 2020
    Assignee: SONY CORPORATION
    Inventor: Toshihiko Watanabe
  • Patent number: 10779396
    Abstract: A printed circuit board includes a first insulating layer having a cavity, a metal pattern including a first shielding pattern disposed on an inner wall of the cavity and a second shielding pattern spaced apart from the first shielding pattern and covering the first shielding pattern, an electronic device positioned in the cavity and surrounded by the first shielding pattern and the second shielding pattern, and a second insulating layer stacked on the first insulating layer and embedding the electronic device therein.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: September 15, 2020
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yeo-Il Park, Yong-Duk Lee, Sang-Ho Jeong
  • Patent number: 10763293
    Abstract: An image sensing chip package and an image sensing chip packaging method are provided. In the image sensing chip package, an image sensing chip is located in a through hole of a substrate, and a front surface of the image sensing chip is flush with a first surface of the substrate. In this way, in the image sensing chip package, a height of the image sensing chip is controlled with the first surface of the substrate as a reference. Since the first surface of the substrate does not change in the packaging process, almost no uncontrollable factor affects the height of the image sensing chip.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: September 1, 2020
    Assignee: China Wafer Level CSP Co., Ltd.
    Inventor: Zhiqi Wang
  • Patent number: 10763220
    Abstract: Discussed generally herein are methods and devices including or providing an electromagnetic interference (EMI) shielding. A device can include substrate including electrical connection circuitry therein, ground circuitry on, or at least partially in the substrate, the ground circuitry at least partially exposed by a surface of the substrate, a die electrically connected to the connection circuitry and the ground circuitry, the die on the substrate, a conductive material on a die backside, and a conductive paste or one or more wires electrically connected to the ground circuitry and the conductive material.
    Type: Grant
    Filed: January 24, 2019
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Rajendra C. Dias, Mitul B. Modi
  • Patent number: 10741461
    Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole, having an active surface having a connection pad disposed thereon and an inactive surface opposing the active surface, and having a protrusion bump disposed on the connection pad; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip. In the fan-out semiconductor package, step portions of the protrusion bumps may be removed.
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: August 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyoung Joon Kim, Kyung Seob Oh, Kyoung Moo Harr
  • Patent number: 10741534
    Abstract: The present description addresses example methods for forming multi-chip microelectronic devices and the resulting devices. The multiple semiconductor die of the multichip package will be attached to a solid plate with a bonding system selected to withstand stresses applied when a mold material is applied to encapsulate the die of the multichip device. The solid plate will remain as a portion of the finished multi-chip device. The solid plate can be a metal plate to function as a heat spreader for the completed multi-chip device.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Sri Ranga Sai Boyapati, Kristof Darmawikarta, Rahul N. Manepalli, Robert Alan May, Srinivas V. Pietambaram
  • Patent number: 10714463
    Abstract: A method of forming a semiconductor device package includes the following steps. A redistribution structure is formed on a carrier. A plurality of second semiconductor devices are disposed on the redistribution structure. At least one warpage adjusting component is disposed on at least one of the second semiconductor devices. A first semiconductor device is disposed on the redistribution structure. An encapsulating material is formed on the redistribution structure to encapsulate the first semiconductor device, the second semiconductor devices and the warpage adjusting component. The carrier is removed to reveal a bottom surface of the redistribution structure. A plurality of electrical terminals are formed on the bottom surface of the redistribution structure.
    Type: Grant
    Filed: November 24, 2019
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Yao Lin, Cheng-Yi Hong, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Shu-Shen Yeh, Kuang-Chun Lee
  • Patent number: 10709008
    Abstract: A power module assembly structure includes an element layer, a flexible printed circuit board layer, and an external wire layer. The element layer includes one component. The flexible printed circuit board layer includes at least one insulating region and at least one conductive region. The external wire layer is disposed on a second side of the flexible printed circuit board layer. The first side and the second side of the flexible printed circuit board layer are two opposite sides, and the external wire layer includes at least one external wire. The at least one external wire is electrically connected to the at least one conductive region of the flexible printed circuit board layer. The heat generated by the one component is directly conducted to the outside of the power module package structure through the at least one conductive region and the at least one external wire.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: July 7, 2020
    Assignee: OTO TECHNOLOGY CORP.
    Inventor: Tung-Jung Liu
  • Patent number: 10700023
    Abstract: Package assemblies for improving heat dissipation of high-power components in microwave circuits are described. A laminate that includes microwave circuitry may have cut-outs that allow high-power components to be mounted directly on a heat slug below the laminate. Electrical connections to circuitry on the laminate may be made with wire bonds. The packaging allows more flexible design and tuning of packaged microwave circuitry.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: June 30, 2020
    Assignee: MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC.
    Inventor: Timothy Gittemeier
  • Patent number: 10692917
    Abstract: A sensor package structure includes a substrate, a sensor chip disposed on the substrate, a plurality of metal wires electrically connecting the sensor chip to the substrate, a light-permeable layer, a combining layer connecting a portion of the light-permeable layer onto the sensor chip, and a packaging compound covering lateral sides of the sensor chip, the light-permeable layer, and the combining layer. Each of the metal wires is embedded in the combining layer and the packaging compound, and has a diameter within a range of 0.8-1.1 mil. Each of the metal wires includes a first segment connected to the substrate and a second segment connected to the sensor chip. In each of the metal wires, the second segment integrally and curvedly extends from the first segment, and the second segment and a top surface of the sensor chip have a sloping angle within a range of 5-45 degrees.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: June 23, 2020
    Assignee: KINGPAK TECHNOLOGY INC.
    Inventors: Hsiu-Wen Tu, Chung-Hsien Hsin, Jian-Ru Chen
  • Patent number: 10665522
    Abstract: A semiconductor device and method is disclosed. Devices shown include a die coupled to an integrated routing layer, wherein the integrated routing layer includes a first width that is wider than the die. Devices shown further included a molded routing layer coupled to the integrated routing layer.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: May 26, 2020
    Assignee: Intel IP Corporation
    Inventors: Lizabeth Keser, Thomas Ort, Thomas Wagner, Bernd Waidhas