Multiple Contact Layers Separated From Each Other By Insulator Means And Forming Part Of A Package Or Housing (e.g., Plural Ceramic Layer Package) Patents (Class 257/700)
  • Patent number: 11569815
    Abstract: A rectangular power module with a body having two short ends defining a length and two long sides defining a width having three parallel circuit paths crossing the short width distance from side to side using side positioned gate terminals and planar top positioned top power terminal positioned between MOSFETS in the circuit for even thermal positioning and reduced current path, inductance, and resistance and increased power density.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: January 31, 2023
    Inventors: Zhong Chen, Simon S. Ang, Junji Ke
  • Patent number: 11552403
    Abstract: Embodiments herein disclose techniques for apparatuses and methods for making a slot antenna on a PCB with a cutout. A PCB may include a metal layer. The metal layer may include a cavity to be a first radiating element of an antenna, and a slot to be a second radiating element of the antenna. In addition, the cavity may extend to be the cutout of the PCB through other layers of the PCB. The first and second radiating elements may provide a determined transmission frequency for the antenna. The metal layer may further include a portion of a transmission line of the antenna, and the transmission line is in contact with the cavity and the slot. A package may be affixed to the PCB, where a portion of the package may be within the cutout of the PCB. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: October 27, 2021
    Date of Patent: January 10, 2023
    Assignee: Intel Corporation
    Inventors: Eng Huat Goh, Min Suet Lim, Boon Ping Koh, Wil Choon Song, Khang Choong Yong
  • Patent number: 11508639
    Abstract: A semiconductor package includes an interconnect structure having a first surface and a second surface opposing the first surface, and including a redistribution pattern and a vertical connection conductor, a first semiconductor chip disposed for a first inactive surface to oppose the first surface, a second semiconductor chip disposed on the first surface of the interconnect structure and disposed for the second inactive surface to oppose the first surface; a first encapsulant encapsulating the first and second semiconductor chips, a backside wiring layer disposed on the first encapsulant, a wiring structure connecting the redistribution pattern to the backside wiring layer, a heat dissipation member disposed on the second surface and connected to the vertical connection conductor.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: November 22, 2022
    Inventors: Myungsam Kang, Yongjin Park, Youngchan Ko
  • Patent number: 11502652
    Abstract: A device that includes a substrate and a power amplifier coupled to the substrate. The substrate includes at least one dielectric layer, a plurality of interconnects, and a capacitor configured to operate as an output match element, where the capacitor is defined by a plurality of capacitor interconnects. The power amplifier is coupled to the capacitor. The capacitor is configured to operate as an output match element for the power amplifier. The substrate includes an inductor coupled to the capacitor, where the inductor is defined by at least one inductor interconnect. The capacitor and the inductor are configured to operate as a resonant trap or an output match element.
    Type: Grant
    Filed: May 8, 2020
    Date of Patent: November 15, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Daniel Daeik Kim, Paragkumar Ajaybhai Thadesar, Changhan Hobie Yun, Sameer Sunil Vadhavkar, Nosun Park
  • Patent number: 11502006
    Abstract: Some embodiments include an apparatus having a well region extending into a semiconductor substrate. A first conductive element is over the well region, and a second conductive element is over the first conductive element. A hole extends through the first conductive element. A connecting element extends from the second conductive element to the well region, and passes through the hole.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: November 15, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Nanae Yokoyama, Ryota Suzuki, Makoto Sato
  • Patent number: 11488761
    Abstract: A laminated electronic component includes an element body and a conductor. The element body is formed by laminating a plurality of element-body layers. The element body has a first face, a second face, and a pair of third faces. The conductor is disposed on the element body and has an L shape. The conductor has an exposed face exposed on the first face and the second face. The exposed face includes a plurality of divided regions divided by the element body. The length of each divided region in a dividing direction is longer than a distance with which the plurality of divided regions is separated from each other and longer than a distance with which the exposed face and the pair of third faces are separated from each other.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: November 1, 2022
    Assignee: TDK CORPORATION
    Inventors: Yuto Shiga, Hajime Kato, Kazuya Tobita, Youichi Kazuta, Yuya Ishima, Satoru Okamoto, Shunji Aoki
  • Patent number: 11462509
    Abstract: A package structure is provided. The package structure includes a substrate having a first surface and a second surface opposite the first surface. The substrate includes a cavity extending from the second surface toward the first surface, and thermal vias extending from a bottom surface of the cavity to the first surface. The package structure also includes at least one electronic device formed in the cavity and thermally coupled to the thermal vias. In addition, the package structure includes an insulating layer formed over the second surface and covering the first electronic device. The insulating layer includes a redistribution layer (RDL) structure electrically connected to the electronic device. The package structure also includes an encapsulating material formed in the cavity, extending along sidewalls of the electronic device and between the electronic device and the insulating layer.
    Type: Grant
    Filed: July 1, 2020
    Date of Patent: October 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Hao Tsai, Ming-Da Cheng, Mirng-Ji Lii
  • Patent number: 11463063
    Abstract: A method for fabricating an array of front ends for an array of packaged electronic components that each comprise: an electrical element packaged within a package comprising a front part of a package comprising an inner section with a cavity therein opposite the resonator defined by the raised frame and an outer section sealing said cavity; and a back part of the package comprising a back cavity in an inner back section, and an outer back section sealing the cavity, said back package further comprising a first and a second via through the back end around said at least one back cavity for coupling to front and back electrodes of the electronic component; the vias terminating in external contact pads that are coupleable in a ‘flip chip’ configuration to a circuit board; the method comprising the stages of: i. Obtaining a carrier substrate having an active membrane layer attached thereto by its rear surface, with a front electrode on the front surface of the active membrane layer; ii.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: October 4, 2022
    Assignee: Zhuhai Crystal Resonance Technologies Co., Ltd.
    Inventors: Dror Hurwitz, BawChing Perng, Duan Feng
  • Patent number: 11450606
    Abstract: A semiconductor package structure including a semiconductor die having a first surface, a second surface opposite the first surface, and a third surface adjoined between the first surface and the second surface. A first protective insulating layer covers the first and third surfaces of the semiconductor die. A redistribution layer (RDL) structure is electrically coupled to the semiconductor die and surrounded by the first protective insulating layer on the first surface of the semiconductor die. A first passivation layer covers the first protective insulating layer and the RDL structure. At least one conductive structure passes through the first passivation layer and is electrically coupled to the RDL structure. A method of forming the semiconductor package is also provided.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: September 20, 2022
    Assignee: MediaTek Inc.
    Inventors: Yen-Yao Chi, Nai-Wei Liu, Tzu-Hung Lin, Ta-Jen Yu, Wen-Sung Hsu
  • Patent number: 11450794
    Abstract: A carrier and a component are disclosed. In an embodiment a component includes a semiconductor chip including a substrate and a semiconductor body arranged thereon and a metallic carrier having a coefficient of thermal expansion which is at least 1.5 times greater than a coefficient of thermal expansion of the substrate or of the semiconductor chip, wherein the semiconductor chip is attached to a mounting surface of the metallic carrier by a connection layer such that the connection layer is located between the semiconductor chip and a buffer layer and adjoins a rear side of the semiconductor chip, wherein the buffer layer has a yield stress which is at least 10 MPa and at most 300 MPa, and wherein the substrate of the semiconductor chip and the metallic carrier of the component have a higher yield stress than the buffer layer.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: September 20, 2022
    Assignee: OSRAM OLED GMBH
    Inventors: Paola Altieri-Weimar, Ingo Neudecker, Michael Zitzlsperger, Stefan Groetsch, Holger Klassen
  • Patent number: 11430723
    Abstract: A method of manufacturing a semiconductor device having a semiconductor die within an extended substrate and a bottom substrate may include bonding a bottom surface of a semiconductor die to a top surface of a bottom substrate, forming an adhering member to a top surface of the semiconductor die, bonding an extended substrate to the semiconductor die and to the top surface of the bottom substrate utilizing the adhering member and a conductive bump on a bottom surface of the extended substrate and a conductive bump on the bottom substrate. The semiconductor die and the conductive bumps may be encapsulated utilizing a mold member. The conductive bump on the bottom surface of the extended substrate may be electrically connected to a terminal on the top surface of the extended substrate. The adhering member may include a laminate film, a non-conductive film adhesive, or a thermal hardening liquid adhesive.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: August 30, 2022
    Assignee: AMKOR TECHNOLOGY SINGAPORE HOLDING PTE. LTD.
    Inventors: Jae Yun Kim, Gi Tae Lim, Woon Kab Jung, Ju Hoon Yoon, Dong Joo Park, Byong Woo Cho, Gyu Wan Han, Ji Young Chung, Jin Seong Kim, Do Hyun Na
  • Patent number: 11412621
    Abstract: A device-embedded board includes a board main body, conductor wiring layers formed inside or on a surface of the board main body, and device formation layers formed inside the board main body so as to be in contact with a portion of the conductor wiring layers. The device formation layer is configured in an insulating region in which functional filler for forming a devices is dispersed.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: August 9, 2022
    Assignee: TDK CORPORATION
    Inventors: Takaaki Morita, Seiichi Tajima, Takashi Kariya
  • Patent number: 11355465
    Abstract: The present technology relates to a semiconductor device and a method of manufacturing the same capable of improving reliability of a glass substrate on which a wiring layer is formed. A semiconductor device is provided with a glass substrate on a front surface or front and back surfaces of which a wiring layer including one or more layers of wiring is formed, an electronic component arranged inside a glass opening formed on the glass substrate, and a redistribution layer that connects the wiring of the glass substrate and the electronic component. The present technology is applicable to, for example, a high-frequency front-end module and the like.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: June 7, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shun Mitarai, Shusaku Yanagawa
  • Patent number: 11348865
    Abstract: A substrate for an electronic device may include one or more interconnect pockets. Each of the interconnect pockets may be defined by a first pocket wall and a second pocket wall that may extend between the first pocket wall and the second exterior surface of the substrate. The second pocket wall may extend from the first pocket wall at a wall angle that is greater than or equal to 90 degrees. Individual interconnects may be located within respective individual ones of the interconnect pockets.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Praneeth Akkinepally, Jieying Kong, Frank Truong
  • Patent number: 11335663
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface, and a die secured to the package substrate, wherein the die has a first surface and an opposing second surface, the die has first conductive contacts at the first surface and second conductive contacts at the second surface, and the first conductive contacts are coupled to conductive pathways in the package substrate by first non-solder interconnects.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Shawna M. Liff, Adel A. Elsherbini, Johanna M. Swan, Arun Chandrasekhar
  • Patent number: 11329012
    Abstract: A technique for activating a fuse function in a semiconductor device in a relatively short time is provided. The semiconductor device includes a second bonding material provided on the upper surface of the insulating substrate, a third bonding material provided on an upper surface of the semiconductor element, a through hole extending from the first circuit pattern to the second circuit pattern via the core material, a conductive film provided on an inner wall of the through hole, and a heat insulating material provided inside the through hole and surrounded by the conductive film in plan view. The conductive film allows the first circuit pattern and the second circuit pattern to be conductive.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: May 10, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takuya Kitabayashi, Hiroshi Yoshida, Hidetoshi Ishibashi, Daisuke Murata
  • Patent number: 11324131
    Abstract: A circuit board is installed with a semiconductor module on an upper face and provided with connection terminals on a lower face. A connection pin is provided on at least some of the connection terminals. The connection terminals include a drive terminal for driving the semiconductor module and a function terminal for connecting the semiconductor module and other function units. The disposition of the drive terminal in each of divided areas is point-symmetric with respect to a center of the circuit board. The divided areas divide the circuit board into fourths.
    Type: Grant
    Filed: September 21, 2018
    Date of Patent: May 3, 2022
    Assignee: AISIN CORPORATION
    Inventor: Takanobu Naruse
  • Patent number: 11316438
    Abstract: The present disclosure provides a power supply module and a manufacture method thereof, belonging to the technical field of power electronics. According to the present disclosure, a unibody conductive member is employed to connect a conductive part in a passive element to a conductive layer in a substrate. This is advantageous in simplifying the structure of the passive element, and enabling a structurally compact power supply module at a reduced cost. Additionally, stacking the passive element with the substrate may allow for a further compact structure for the power supply module, improving the space utilization rate for the power supply module, while enhancing the external appearance of the power supply module with tidiness, simplicity and aesthetics.
    Type: Grant
    Filed: December 29, 2019
    Date of Patent: April 26, 2022
    Assignee: DELTA ELETRONICS (SHANGHAI) CO., LTD.
    Inventors: Pengkai Ji, Shouyu Hong, Xiaoni Xin, Le Liang, Zhenqing Zhao
  • Patent number: 11315842
    Abstract: A transistor (2) and a matching circuit substrate (3-6) are provided on a base plate (1) and connected to each other. A frame (15) is provided on the base plate (1) and surrounds the transistor (2) and the matching circuit substrate (3-6). The frame (15) has a smaller linear expansion coefficient than that of the base plate (1). A screwing portion (17) is provided in the frame (15). A size of the base plate (1) is smaller than that of the frame (15).
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: April 26, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventors: Hiromitsu Utsumi, Hiroaki Minamide, Suguru Maki, Katsumi Miyawaki
  • Patent number: 11310914
    Abstract: A circuit board includes a board body, a first electrode, and a second electrode. The board body contains a resin material. The first electrode is disposed on a first main surface of the board body and includes a first electrode base and a first coating film that covers at least a part of an outer surface of the first electrode base. The second electrode is disposed on the first main surface of the board body and includes a pillar-shaped structure that includes a second electrode base, a first plating film that is disposed on the second electrode base, and a first plating structure having a first end directly connected to the first plating film, and a second coating film that covers at least a part of an outer surface of the pillar-shaped structure.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: April 19, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takafumi Kusuyama
  • Patent number: 11294957
    Abstract: A method for searching video includes receiving a video query, the video query including a first video query term identifying a first foreground object, a second video query term identifying a second foreground object, and a third video query term identifying a spatiotemporal relationship; searching the video in response to the video query for the first foreground object and the second foreground object within the spatiotemporal relationship; and generating a search result in response to the searching.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: April 5, 2022
    Assignee: CARRIER CORPORATION
    Inventors: Sofiane Yous, Keith J. Power, Kishore K. Reddy, Alan Matthew Finn, Jaume Amores, Zhen Jia, Yanzhi Chen
  • Patent number: 11289456
    Abstract: A semiconductor package includes a frame having a through-opening, a first semiconductor chip disposed in the through-opening and having a first active surface on which a first connection pad is disposed and a first inactive surface opposing the first active surface, a second semiconductor chip disposed on the first semiconductor chip and having a second active surface on which a second connection pad is disposed and a second inactive surface opposing the second active surface, first and second bumps electrically connected to the first and second connection pads, respectively, first and second dummy bumps disposed on a same level as levels of the first and second bumps, respectively, first and second posts electrically connected to the first and second bumps, respectively, a connection member including a redistribution layer electrically connected to each of the first and second posts, and a dummy post disposed between the frame and the connection member.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: March 29, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Doohwan Lee, Jungsoo Byun
  • Patent number: 11282811
    Abstract: An apparatus includes an integrated circuit and a substrate coupled to the integrated circuit. The substrate includes a primary layer having a first surface that is a first external surface of the substrate. The primary layer includes an open area that extends through the primary layer to an inner layer of the substrate. The substrate includes a secondary layer. The inner layer is located between the primary layer and the secondary layer. The inner layer includes a third surface that is orientated approximately parallel to the first surface of the primary layer. A portion of the third surface of the inner layer is exposed via the open area of the primary layer. A first plurality of wire bond pads are disposed on the portion of the third surface of the inner layer that is exposed via the open area of primary layer.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: March 22, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kelvin Tan Aik Boo, Chin Hui Chong, Seng Kim Ye, Hong Wan Ng, Hem P. Takiar
  • Patent number: 11276667
    Abstract: Heat dissipation technology in a die stack is disclosed. In one example, an electronic device comprises a pair of electrically coupled dies; and a heat spreader disposed between the pair of dies and electrically isolated from an electrical connection between the pair of dies.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: March 15, 2022
    Assignee: Intel Corporation
    Inventor: Yen Hsiang Chew
  • Patent number: 11270298
    Abstract: Mining circuitry may be used to mine digital currency such as bitcoins by computing solutions to a cryptographic puzzle. Successful computation of a solution to the cryptographic puzzle may provide a reward of the digital currency. The mining circuitry may partition the mined reward between a first digital wallet and a second digital wallet. The first digital wallet may be user-provided, whereas the second digital wallet may be hardcoded into the dedicated mining circuitry. The mining circuitry may include control circuitry and multiple processing core circuits. The control circuitry may control the processing cores to solve the cryptographic puzzle via exhaustive search over possible inputs to the cryptographic puzzle.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: March 8, 2022
    Assignee: 21, Inc.
    Inventors: Matthew Pauker, Nigel Drego, Veerbhan Kheterpal, Daniel Firu
  • Patent number: 11251146
    Abstract: A semiconductor device comprises a semiconductor chip having a radio-frequency circuit and a radio-frequency terminal, an external radio-frequency terminal, and a non-galvanic connection arranged between the radio-frequency terminal of the semiconductor chip and the external radio-frequency terminal, wherein the non-galvanic connection is designed to transmit a radio-frequency signal.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: February 15, 2022
    Assignee: Infineon Technologies AG
    Inventors: Walter Hartner, Francesca Arcioni, Birgit Hebler, Martin Richard Niessner, Claus Waechter, Maciej Wojnowski
  • Patent number: 11251257
    Abstract: A display panel including a first array substrate, a first pad, and a second pad is provided. The first array substrate includes a first substrate, a first active element, a first display element, and a second display element. The first active element is disposed on the top surface of the first substrate. The first display element and the second display element are disposed on the top surface of the first substrate. The first display element is electrically connected to the first active element. The first pad and the second pad are disposed on the bottom surface of the first substrate. The first active element is electrically connected to the first pad. Each of the first pad and the second pad includes an embedded part and a protruded part. The embedded part is located in the first substrate. The protruded part is protruded from the bottom surface of the first substrate.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: February 15, 2022
    Assignee: Au Optronics Corporation
    Inventors: Tsung-Ying Ke, Yung-Chih Chen, Keh-Long Hwu, Wan-Tsang Wang, Chun-Hsin Liu
  • Patent number: 11251141
    Abstract: A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.
    Type: Grant
    Filed: May 31, 2020
    Date of Patent: February 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Hsuan Tai, Ting-Ting Kuo, Yu-Chih Huang, Chih-Wei Lin, Hsiu-Jen Lin, Chih-Hua Chen, Ming-Da Cheng, Ching-Hua Hsieh, Hao-Yi Tsai, Chung-Shi Liu
  • Patent number: 11244924
    Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: February 8, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shang-Yun Hou, Yun-Han Lee
  • Patent number: 11240912
    Abstract: A cavity elongated in one direction is formed in a protective film covering the conductive pattern of the topmost conductive layer of a multilayer wiring substrate. The cavity exposes part of the conductive pattern. A first via-conductor extends downward from the conductive pattern of the topmost conductive layer at least until that of a second conductive layer. Second via-conductors extend downward from the conductive pattern of the second or third conductive layer at least until that of a conductive layer one below. As viewed from above, the first via-conductor and the cavity partially overlap each other. At least two second via-conductors are disposed to sandwich the cavity therebetween. The difference between the smallest gap between the cavity and the second via-conductor at one side and that between the cavity and the second via-conductor at the other side is smaller than the smallest gap between the cavity and the second via-conductors.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: February 1, 2022
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Masao Kondo, Shigeki Koya, Kenji Sasaki
  • Patent number: 11232998
    Abstract: A semiconductor device package includes a substrate, a first circuit layer and a second circuit layer. The first circuit layer is disposed on the substrate. The first circuit layer has a plurality of dielectric layers and a first through via penetrating the dielectric layers and electrically connected to the substrate. The second circuit layer is disposed on the first circuit layer. The second circuit layer has a plurality of dielectric layers and a second through via penetrating the dielectric layers and electrically connected to the first circuit layer.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: January 25, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Ming-Fong Jhong, Chen-Chao Wang, Hung-Chun Kuo
  • Patent number: 11217530
    Abstract: A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer including an inorganic film located on the lower layer Cu line and an organic resin film located on the inorganic film, and a via connection part located in a via connection hole running in an up-down direction through the insulating layer in an area where the lower layer Cu line and the upper layer Cu line overlap each other is provided. The via connection part includes a barrier conductive layer located on a part of the lower layer Cu line exposed to a bottom part of the via connection hole and on an inner wall of the via connection hole.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: January 4, 2022
    Assignee: DAI NIPPON PRINTING CO., LTD.
    Inventors: Hiroshi Kudo, Takamasa Takano
  • Patent number: 11217551
    Abstract: A manufacturing method of a chip package structure is provided. A carrier board with an accommodating cavity, a substrate, and a stainless steel layer sputtered on the substrate is disposed. A chip is disposed in the accommodating cavity of the carrier board. The chip has an active surface, a back surface opposite to the active surface, and multiple electrodes disposed on the active surface. A circuit structure layer is formed on the carrier board. The circuit structure layer includes a patterned circuit and multiple conductive vias. The patterned circuit is electrically connected to the electrodes of the chip through the conductive vias. An encapsulant is formed to cover the active surface of the chip and the circuit structure layer. The active surface of the chip and a bottom surface of the encapsulant are coplanar. The carrier board is removed to expose the chip disposed in the accommodating cavity.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: January 4, 2022
    Inventor: Chung W. Ho
  • Patent number: 11183621
    Abstract: A component may include a semiconductor chip, a buffer layer, a connecting layer, and a metal carrier. The semiconductor chip may include a substrate and a semiconductor body arranged thereon. The metal carrier may have a thermal expansion coefficient at least 1.5 times as great as a thermal expansion coefficient of the substrate or of the semiconductor chip. The chip may be fastened on the metal carrier by the connecting layer, and the buffer layer may have a yield stress ranging from 10 MPa. The buffer layer may have a thickness ranging from 2 um to 10 um and adjoin the chip. The substrate and the metal carrier may have a higher yield strength than the buffer layer.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: November 23, 2021
    Assignee: OSRAM OLED GMBH
    Inventors: Paola Altieri-Weimar, Ingo Neudecker, Andreas Ploessl, Marcus Zenger
  • Patent number: 11177207
    Abstract: A transistor includes a semiconductor substrate having a first terminal and a second terminal. An interconnect structure is formed on an upper surface of the semiconductor substrate, the interconnect structure being formed of multiple layers of dielectric material and electrically conductive material. The electrically conductive material of the interconnect structure includes a pillar in electrical contact with the first terminal, a first runner electrically connected to the pillar, a tap interconnect in electrical contact with the second terminal, a second runner electrically connected to the tap interconnect, a shield structure positioned between the pillar and the tap interconnect, and a shield runner electrically connected to the shield structure, the shield runner overlying the second runner in a direction perpendicular to the upper surface of the semiconductor substrate.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: November 16, 2021
    Assignee: NXP USA, Inc.
    Inventors: Vikas Shilimkar, Kevin Kim, Charles John Lessard, Humayun Kabir
  • Patent number: 11166386
    Abstract: An interposer substrate includes a dielectric portion, a magnetic portion, and a first principal surface and a second principal surface opposite to each other. Connection terminal electrodes are each provided on a corresponding one of first principal surfaces of the dielectric portion and the magnetic portion, and are connected to a cable. Circuit-board terminal electrodes are provided on a second principal surface of the dielectric portion and connected to a circuit board. Wiring electrodes are provided inside a base body, and connecting the connection terminal electrodes to the circuit-board terminal electrodes in a predetermined connection pattern. The wiring electrodes include a first wiring electrode passing through only the dielectric portion, and a second wiring electrode passing through the magnetic portion.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: November 2, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Keito Yonemori, Hirokazu Yazaki, Takanori Tsuchiya, Koji Kamada
  • Patent number: 11164804
    Abstract: An IC device package includes a carrier, one or more IC devices and a lid. The lid includes a lid-ridge. The lid is connected to the carrier by connecting the lid-ridge to the carrier with first nano particle metallic paste, prior to connecting the IC device to the carrier. Subsequent to connecting the IC device to the carrier, the lid is connected to the lid-ridge with second nano particle metallic paste. The nano particle metallic paste may be sintered to form a metallic connection. In multi-IC device packages, the lid-ridge may be positioned between the lid and the carrier and between the IC devices.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: November 2, 2021
    Assignee: International Business Machines Corporation
    Inventors: Charles L. Arvin, Kevin Drummond, Luca Del Carro, Thomas Brunschwiler, Stephanie Allard, Kenneth C. Marston, Marcus E. Interrante
  • Patent number: 11147851
    Abstract: A method of fabricating an electronic power module by additive manufacturing, the electronic module including a substrate having an electrically insulating plate presenting opposite first and second faces, with a first metal layer arranged directly on the first face of the insulating plate, and a second metal layer arranged directly on the second face of the insulating plate. At least one of the metal layers is made by a step of depositing a thin layer of copper and a step of annealing the metal layer, and the method further includes a step of forming at least one thermomechanical transition layer on at least one of the first and second metal layers, the at least one thermomechanical transition layer including a material presenting a coefficient of thermal expansion that is less than that of the metal of the metal layer.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: October 19, 2021
    Assignee: SAFRAN
    Inventors: Rabih Khazaka, Stéphane Azzopardi, Donatien Henri Edouard Martineau
  • Patent number: 11134030
    Abstract: Techniques and mechanisms for interconnecting network circuitry of an integrated circuit (IC) die and physical layer (PHY) circuits of the same IC die. In an embodiment, nodes of the network circuitry include first routers and processor cores, where the first routers are coupled to one another in an array configuration which includes rows and columns. First interconnects each extend to couple both to a corresponding one of the PHY circuits and to a corresponding one of the first routers. For each of one or more of the first interconnects, a respective one or more rows (or one or more columns) of the array configuration extend between the corresponding PHY and the corresponding router. In another embodiment, the network circuitry comprises network clusters which each include a different respective row of the array configuration.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: September 28, 2021
    Assignee: Intel Corporation
    Inventors: Akhilesh Kumar, Surhud Khare
  • Patent number: 11127706
    Abstract: An electronic package and method includes a substrate including a plurality of pads on a major surface. An electronic component including a plurality of pads on a major surface facing the major surface of the substrate. A stud bump electrically couples one of the plurality of pads of the substrate to one of the plurality of pads of the electronic component.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation
    Inventors: Zhaozhi Li, Sanka Ganesan, Debendra Mallik, Gregory Perry, Kuan H. Lu, Omkar Karhade, Shawna M. Liff
  • Patent number: 11121099
    Abstract: A semiconductor device includes a heat sink, an integrated component in which a ceramic terminal having a microstrip line and a matching circuit are integrated into one unit, a lead fixed to the ceramic terminal, a matching substrate fixed to the heat sink, a semiconductor chip fixed to the heat sink, a plurality of wires configured to connect the matching circuit and the matching substrate and to connect electrically the matching substrate and the semiconductor chip, a frame configured to surround the matching substrate and the semiconductor chip in a plan view, and a cap provided on the frame.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: September 14, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Masayasu Ito, Katsumi Miyawaki, Hiroaki Ichinohe, Takashi Tsurumaki
  • Patent number: 11114355
    Abstract: A power module includes a power wiring line provided with a power element, a glass ceramic multilayer substrate provided with a control element to control the power element, and a highly heat-conductive ceramic substrate made of a ceramic material having higher thermal conductivity than a glass ceramic contained in the glass ceramic multilayer substrate. The power wiring line is disposed on the highly heat-conductive ceramic substrate, and the glass ceramic multilayer substrate is disposed directly on the highly heat-conductive ceramic substrate.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: September 7, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takahiro Hayakawa, Yasutaka Sugimoto, Tomoki Kato, Yoichi Moriya
  • Patent number: 11101252
    Abstract: A package-on-package structure including a first and second package is provided. The first package includes a semiconductor die, through insulator vias, an insulating encapsulant, conductive terminals and a redistribution layer. The semiconductor die has a die height H1. The plurality of through insulator vias is surrounding the semiconductor die and has a height H2, and H2<H1. The insulating encapsulant is encapsulating the semiconductor die and the plurality of through insulator vias, wherein the insulating encapsulant has a plurality of via openings revealing each of the through insulator vias. The plurality of conductive terminals is disposed in the via openings and electrically connected to the plurality of through insulator vias. The redistribution layer is disposed on the active surface of the semiconductor die and over the insulating encapsulant. The second package is stacked on the first package and electrically connected to the plurality of conductive terminals of the first package.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Ting Lin, Chin-Fu Kao, Jing-Cheng Lin, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11101236
    Abstract: A method of forming a semiconductor device includes applying an adhesive material in a first region of an upper surface of a substrate, where applying the adhesive material includes: applying a first adhesive material at first locations of the first region; and applying a second adhesive material at second locations of the first region, the second adhesive material having a different material composition from the first adhesive material. The method further includes attaching a ring to the upper surface of the substrate using the adhesive material applied on the upper surface of the substrate, where the adhesive material is between the ring and the substrate after the ring is attached.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: August 24, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuan-Yu Huang, Li-Chung Kuo, Sung-Hui Huang, Shang-Yun Hou, Tsung-Yu Chen, Chien-Yuan Huang
  • Patent number: 11094649
    Abstract: Present disclosure provides a semiconductor package structure, which includes a redistribution layer (RDL) structure, an electronic device, a first reinforcement structure, a second reinforcement structure, and an encapsulant. The RDL structure has a passivation layer and a patterned conductive layer disposed in the passivation layer. The electronic device is disposed on the RDL structure. The first reinforcement structure is disposed on the RDL structure and has a first modulus. The second reinforcement structure is disposed on the first reinforcement structure and has a second modulus substantially less than the first modulus. The encapsulant is disposed on the RDL structure and encapsulates the electronic device, the first reinforcement structure and the second reinforcement structure.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: August 17, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Fan-Yu Min, Chen-Hung Lee, Hsiu-Chi Liu, Liang-Chun Chen
  • Patent number: 11088047
    Abstract: A hermetic ceramic package for high current signals includes a substrate made of a plurality of ceramic green sheets that form an upper body portion having an upper surface and a lower body portion having a lower surface and an intermediate surface between the upper surface and the lower surface. A first conductive plate is formed on the intermediate surface and a first plurality of conductive pad vias are formed in the lower body portion, extending from the first conductive plate to the lower surface of the lower body portion. A heat sink if coupled to the lower surface of the lower body portion and a first conductive pad also coupled to the lower surface such that the first conductive pad is electrically coupled to the first plurality of conductive pad vias.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: August 10, 2021
    Assignee: Texas Instruments Incorporated
    Inventors: Joao Carlos Felicio Brito, Javier Antonio Valle Mayorga, Hector Torres
  • Patent number: 11076488
    Abstract: A board having an electronic component embedded therein, includes a core layer having a groove with a bottom surface, an electronic component disposed above the bottom surface of the groove and spaced apart from the bottom surface of the groove, and an insulating layer disposed on the core layer and covering at least a portion of the electronic component. The insulating layer is disposed in at least a portion of a space between the bottom surface of the groove and the electronic component.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: July 27, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ho Hyung Ham, Jae Sung Sim
  • Patent number: 11063007
    Abstract: A semiconductor device and manufacturing process are provided wherein a first semiconductor device is electrically connected to redistribution structures. An antenna structure is located on an opposite side of the first semiconductor device from the redistribution structures, and electrical connections separate from the first semiconductor device connect the antenna structure to the redistribution structures.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yao Chuang, Po-Hao Tsai, Shin-Puu Jeng
  • Patent number: 11063016
    Abstract: A method includes adhering a voltage regulator die over a carrier through a die-attach film, with the die-attach film being in the voltage regulator die and encircles metal pillars of the voltage regulator die, encapsulating the voltage regulator die in an encapsulating material, and planarizing the encapsulating material. A back portion of the voltage regulator die is removed to expose a through-via in a semiconductor substrate of the voltage regulator die. The method further includes forming first redistribution lines over the encapsulating material and electrically coupled to the through-via, replacing the die-attach film with a dielectric material, forming second redistribution lines on an opposite side of encapsulating material than the first redistribution lines, and bonding an additional device die to the second redistribution lines. The voltage regulator die is electrically coupled to the additional device die.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chih-Yuan Chang, Chuei-Tang Wang, Jeng-Shien Hsieh
  • Patent number: 11049782
    Abstract: A fan-out semiconductor package includes a frame including a plurality of wiring layers electrically connected to each other and having a recess portion having a bottom surface on which a stopper layer is disposed, a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, the inactive surface being disposed in the recess portion to face the stopper layer, an encapsulant covering at least a portion of the frame and at least a portion of the semiconductor chip, the encapsulant being disposed in at least a portion of the recess portion, and a connection structure disposed on the frame and the active surface and including a redistribution layer electrically connected to the plurality of wiring layers and the connection pad. A thickness of the stopper layer is greater than a thickness of each of the plurality of wiring layers.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: June 29, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hanul Lee, Younggwan Ko