Abstract: A method and system for fabricating a interconnect substrate for a multi-component package is disclosed. The multi-component package includes at least one die and a package substrate. The method and system include providing an insulating base and providing at least one conductive layer. The at least one conductive layer provides interconnects for at least one discrete component. The interconnect substrate is configured to be mounted on the at least one die and to have the at least one discrete component mounted on the interconnect substrate.

Abstract: In a semiconductor device, via holes are formed around a chip buried in a package, one end of a conductor filled in the via hole is covered with a pad portion exposed to the outside, and a wiring layer connected to the other end of the conductor is formed. The portion (pad portion) of the wiring layer which correspond to the conductor is exposed from a protective film, or an external connection terminal is bonded to the top of the pad portion. Electrode terminals of the chip are connected to the wiring layer, and the opposite surface of the chip is exposed to the outside.

Abstract: A high dielectric loss tangent layer is provided in a dielectric layer between a power-supply plane and a ground plane. The high dielectric loss tangent layer is arranged such that its edge is located between the edge of the power-supply plane and the edge of the ground plane. The edge of the high dielectric loss tangent layer is preferably separated by a predetermined distance or more from the edge of the power-supply plane or the edge of the ground plane which is located on the inner side.

Abstract: A device is disclosed which includes a flexible material including at least one conductive wiring trace, a first die including at least an integrated circuit, the first die being positioned above a portion of the flexible material, and an encapsulant material that covers the first die and at least a portion of the flexible material. A method is disclosed which includes positioning a first die above a portion of a flexible material, the first die including an integrated circuit and the flexible material including at least one conductive wiring trace, and forming an encapsulant material that covers the first die and at least a portion of the flexible material, wherein at least a portion of the flexible material extends beyond the encapsulant material.

Abstract: A power semiconductor module comprises at least one power semiconductor component and a connection device which makes contact with the power semiconductor component. The connection device is composed of a layer assembly having at least one first electrically conductive layer facing the power semiconductor component and forming at least one first conductor track, and an insulating layer following in the layer assembly, and a second layer following further in the layer assembly and forming at least one second conductor track, the second layer being remote from the power semiconductor component. The power semiconductor module has at least one internal connection element, wherein the internal connection element is embodied as a contact spring having a first and a second contact section and a resilient section. The first contact section has a common contact area with a first or a second conductor track of the connection device.

Abstract: The present invention discloses a structure of package comprising: a substrate with a die receiving through hole; a base attached on a lower surface of the substrate; a die disposed within the die receiving through hole and attached on the base; a dielectric layer formed on the die and the substrate; a re-distribution layer (RDL) formed on the dielectric layer and coupled to the die; a protection layer formed over the RDL; and pluralities of pads formed on the protection layer and coupled to the RDL. The RDL is made from an alloy comprising Ti/Cu/Au alloy or Ti/Cu/Ni/Au alloy.

Abstract: A pad (20) is electrically connected to a first I/O cell (14) while also physically overlying active circuitry of a second I/O cell (16). Note that although the pad (20) overlies the second I/O cell (16), the pad (20) is not electrically connected to the I/O cell (16). Such a pattern may be replicated in any desired manner so that the I/O cells (e.g. 300-310) may have a finer pitch than the corresponding pads (320-324 and 330-335). In addition, the size of the pads may be increased (e.g. pad 131 may be bigger than pad 130) while the width “c” of the I/O cells (132-135) does not have to be increased. Such a pattern (e.g. 500) may be arranged so that the area required in one or more dimensions may be minimized.

Abstract: A method for forming a semiconductor device includes forming drain contact holes in a first interlayer insulating layer provided over a semiconductor substrate. First metal material is formed over the first interlayer insulating layer and fills the drain contact holes. A first metal layer formed by patterning the first metal material includes first lines and landing pads. Trenches formed in a second interlayer insulating layer formed over the patterned first metal material expose the landing pads. A second metal layer is formed by providing second metal material over the second interlayer insulating layer and filling the trenches. The second metal layer includes second lines within the trenches that contact the landing pads. The first and second metal layers define a first metal level of the semiconductor device. The first lines define odd-number lines of the first metal level, and the second lines define even-number lines of the first metal level.

Abstract: A semiconductor device is made by providing a sacrificial substrate and depositing an adhesive layer over the sacrificial substrate. A first conductive layer is formed over the adhesive layer. A polymer pillar is formed over the first conductive layer. A second conductive layer is formed over the polymer pillar to create a conductive pillar with inner polymer core. A semiconductor die or component is mounted over the substrate. An encapsulant is deposited over the semiconductor die or component and around the conductive pillar. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure is electrically connected to the conductive pillar. The sacrificial substrate and adhesive layers are removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first interconnect structure. The second interconnect structure is electrically connected to the conductive pillar.

Abstract: An IC chip for a high frequency region, particularly, a packaged substrate in which no malfunction or error occurs even if 3 GHz is exceeded. A conductive layer is formed at a thickness of 30 ?m on a core substrate and a conductive circuit on an interlayer resin insulation layer is formed at a thickness of 15 ?m. By thickening the conductive layer, the volume of the conductor itself can be increased thereby decreasing its resistance. Further, by using the conductive layer as a power source layer, the capacity of supply of power to an IC chip can be improved.

Abstract: A power semiconductor device and a method for its production. The power semiconductor device has at least one power semiconductor chip, which has on its top side and on its back side large-area electrodes. The electrodes are electrically in connection with external contacts by means of connecting elements, the power semiconductor chip and the connecting elements being embedded in a plastic package. This plastic package has a number of layers of plastic, which are pressed one on top of the other and have plane-parallel upper sides. The connecting elements are arranged on at least one of the plane-parallel upper sides, between the layers of plastic pressed one on top of the other, as a patterned metal layer and are electrically in connection with the external contacts by means of contact vias through at least one of the layers of plastic.

Abstract: A power semiconductor circuit has a power semiconductor module (2) embodied as a flat assembly. A particularly compact and space-saving production of a power semiconductor circuit may be achieved with the possibilities provided by an embodiment of the power semiconductor module, whereby the power semiconductor module (2) is arranged directly on a top track (3) of a power supply and/or output tracking (11) and a cooling device (5) is integrated in the tracking (11).

Abstract: A ball grid array (BGA) package includes a substrate and a chip. A bottom surface of the substrate includes a central area and a marginal area. Several source balls are disposed in the central area. Several ball groups are disposed in the marginal area. Each ball group includes one ground ball and at most three signal balls. The chip is disposed on a top surface of the substrate and electrically connected to the substrate.

Abstract: An electronic device and method is disclosed. In one embodiment, a method includes providing an electrically insulating substrate. A first electrically conductive layer is applied over the electrically insulating substrate. A first semiconductor chip is placed over the first electrically conductive layer. An electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the electrically insulating layer. A through connection is formed in the electrically insulating layer to couple the second electrically conductive layer to the first electrically conductive layer.

Abstract: Mutual inductance from an external output signal system to an external input signal system, in which parallel input/output operation is enabled, is reduced. A semiconductor integrated circuit has a plurality of external connection terminals facing a package substrate, and has an external input terminal and an external output terminal, in which parallel input/output operation is enabled, as part of the external connection terminals. The package substrate has a plurality of wiring layers for electrically connecting between the external connection terminals and module terminals corresponding to each other. A first wiring layer facing the semiconductor integrated circuit has a major wiring for connecting between the external input terminal and a module terminal corresponding to each other, and a second wiring layer in which the module terminals are formed has a major wiring for connecting between an external output terminal and a module terminal corresponding to each other.

Abstract: A semiconductor device capable of improving the efficiency of dispersing heat via a dummy pad. The semiconductor device may be included in a semiconductor package, stack module, card, or system. Also disclosed is a method of manufacturing the semiconductor device. In the semiconductor device, a semiconductor substrate has a first surface and a second surface opposite to the first surface, and at least one conductive pad is arranged on a predetermined region of the first surface. At least one dummy pad is arranged on the first or second surface, and is not electrically coupled to the at least one conductive pad. The dummy pad or pads may be used to disperse heat. Accordingly, it is possible to increase the efficiency of dispersing heat of a semiconductor device, thereby improving the yield of semiconductor devices.

Abstract: A substrate structure is disclosed. The substrate structure includes a core substrate, an interconnection portion and a solder mask. The core substrate includes a top surface and a bottom surface opposite the top surface. A circuit pattern is disposed on the top surface. The interconnection portion is disposed on the top surface; herein the interconnection portion includes a surface dielectric layer and a surface circuit layer disposed on the surface dielectric layer. The surface circuit layer is electrically connected to the circuit pattern. The solder mask is disposed on the interconnection portion; herein the solder mask includes a hole to identify the substrate structure. Besides, a method for manufacturing the substrate structure is disclosed.

Abstract: A semiconductor device which stores a plurality of semiconductor chips, having planar sizes which differ, in the same sealing body in a state in which they are accumulated via an insulating film which has an adhesive property. In the semiconductor device, the thickness of DAF of the back surface of the uppermost semiconductor chip with which the control circuit is formed is thicker than each of DAF of the back surface of the lower layer semiconductor chip with which the memory circuit is formed.

Abstract: A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer.

Abstract: Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device includes at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device including at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein includes the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

Abstract: A first sealing resin seals a side surface of an electronic component and a side surface of a conductive member. A second sealing resin is provided on the first sealing resin, and seals an electrode pad and an electrode pad forming surface of the electronic component and a part of the conductive member. A multilayer wiring structure includes a plurality of stacked insulating layers and a wiring pattern and is provided on a surface of the second sealing resin from which a connecting surface of the electrode pad and a first connecting surface of the conductive member are exposed. The wiring pattern is connected to the connecting surface of the electrode pad and the first connecting surface of the conductive member.

Abstract: A monolithic substrate contains an integrated circuit comprising an amplifier having input and output, a mixer and a hybrid coupler for coupling the amplifier to the mixer. Metallic pads on the substrate are connected to each of two ports of the coupler and separate metallic pads are also connected to each of the input and output of the amplifier. The metallic pads allow the amplifier and mixer to be separately tested by a probe and the input or the output of the amplifier to be selectively connected to the mixer to enable the circuit to operate either as a receiver or transmitter. Alternatively, connections between the mixer and both input and output of the amplifier may be preformed and one of the connections subsequently severed depending on whether the circuit is to operate in receive or transmit mode.

Abstract: The semiconductor device concerning the present invention has a wiring substrate, a semiconductor chip, under-filling resin, a reinforcement ring, a heat spreader, a power supply pattern and a wiring layer under surface via land which are formed on the wiring substrate and spaced out by a clearance region, an insulating film, a wiring layer via land, a via, and a wiring which is formed on the insulating film, passes over the clearance region, and connects the wiring layer via land to the semiconductor chip. The wiring layer via land is formed between the semiconductor chip and the reinforcement ring, and within a region of a 1 mm width from the extension line of the diagonal line of the semiconductor chip. The angle of the lead-out direction of the wiring from a wiring layer via land to the extension line of the diagonal line of the semiconductor chip is 20° or more.

Abstract: A semiconductor device includes an electronic component having a pad surface on which an electrode pad is formed, and having a back surface opposite the pad surface, a sealing resin disposed to cover side faces of the electronic component while exposing the pad surface at a first surface thereof and the back surface at a second surface thereof, a multilayer interconnection structure including insulating layers stacked one over another and interconnection patterns, having an upper surface thereof being in contact with the first surface, the electrode pad, and the pad surface, and having a periphery thereof situated outside a periphery of the sealing resin, and another pad disposed on the upper surface of the multilayer interconnection structure outside the periphery of the sealing resin, wherein the interconnection patterns include a first interconnection pattern directly connected to the electrode pad and a second interconnection pattern directly connected to said another pad.

Abstract: Various apparatus and methods for improving the dissipation of heat from integrated circuit micro-modules are described. One aspect of the invention pertains to an integrated circuit package with one or more thermal pipes. In this aspect, the integrated circuit package includes multiple layers of a cured, planarizing dielectric. An electrical device is embedded within at least one of the dielectric layers. At least one electrically conductive interconnect layer is embedded within one or more of the dielectric layers. A thermal pipe made of a thermally conductive material is embedded in at least one associated dielectric layer. The thermal pipe thermally couples the electrical device with one or more external surfaces of the integrated circuit package. Various methods for forming the integrated circuit package are described.

Abstract: Electronics packages are provided with structure that provides a significantly-reduced package footprint and also facilitates substantial reduction of package fabrication time and cost. The footprint reduction is realized with a frame that defines an aperture wall which surrounds first sets of components on the first side of a printed circuit board and also extends away from the printed circuit board to provide package input/output access along the perimeter of the package footprint. The second side of the printed circuit board receives a second set of components and this set is protected by a board fill. The frame and printed circuit board are configured for realization from frame and board panels whose planar forms substantially reduce package fabrication time and cost because they facilitate the use of modern high-speed printed circuit board (PCB) fabrication processes.

Abstract: A seal ring structure is disclosed for protecting a core circuit region of an integrated circuit chip. The seal ring structure includes a metallization layer, having a bridge sublevel and a plug sublevel. An upper-level bridge is formed on the bridge sublevel at a predetermined location between a peripheral edge of the integrated circuit chip and the core circuit region. A lower-level bridge is formed on the plug sublevel in substantial alignment with the upper-level bridge, wherein the lower-level bridge has a width substantially the same as that of the upper-level bridge.

Abstract: A substrate includes a inorganic material base board has a recess and at least one penetration hole provided around the recess, and a semiconductor device accommodated in the recess and including at least one electrode pad provided on a surface of the semiconductor device. A resin filling is provided in the at least one penetration hole and has at least one through-hole for electrically connecting a top surface and a back surface of the resin filling. An insulating layer covers the surfaces of the semiconductor device, the resin filling and the inorganic material base board and has a first opening corresponding to the at least one through-hole and a second opening corresponding to the at least one electrode pad. A conductive wiring is formed on a surface of the insulating layer for electrically connecting the at least one through-hole and the at least one electrode pad.

Abstract: The present invention provides a substantially hermetically sealed enclosure about an active device area of a semiconductor substrate. The enclosure is created by forming a guard ring around the active device area on the substrate, and forming a metal panel over and in contact with the guard ring to enclose the active device area. The guard ring is a laminate of metal rings formed from alternating metal filled via rings and metal trace rings. The guard ring is formed on an ohmic contact ring on the surface of the substrate. An annealing process may be used to hermetically seal the guard ring to the ohmic contact ring.

Abstract: A semiconductor device includes a package board, first connectors, and a first multi-layered structure. The package board has first and second regions. The first connectors are in the first region. The first multi-layered structure includes a first semiconductor chip, a wiring board, and second to fifth connectors. The first semiconductor chip has first and second surfaces. The first surface covers the second region. The wiring board has third and fourth surfaces. The third surface is fixed to the second surface. The second to fourth connectors are in the center regions of the second to fourth surfaces, respectively. The fifth connectors are aligned along opposing two sides of the fourth surface. The second connectors electrically connect to the third connectors. The third connectors electrically connect to the fourth and fifth connectors. The first connectors electrically connect to the fourth and fifth connectors.

Abstract: A carrier structure embedded with semiconductor chips is disclosed, which comprises a core board and a plurality of semiconductor chips mounted therein. The core board comprises two metal plates between which an adhesive material is disposed. An etching stop layer is deposited on the both surfaces of the core board. Pluralities of cavities are formed to penetrate through the core board. The semiconductor chips each have an active surface on which a plurality of electrode pads are disposed, and those are embedded in the cavities and mounted in the core board. An etching groove formed on the core board between the neighboring semiconductor chips is filled with the adhesive material. The present invention avoids the production of metal burrs when the carrier structure is cut.

Abstract: In a semiconductor device including a semiconductor substrate and an electrode pad formed over the semiconductor substrate, at least one of test element is formed in a region of the semiconductor substrate beneath the electrode pad. The test element is electrically isolated from upper conductive layers outside of the region and the electrode pad.

Abstract: A semiconductor chip includes flip chip contacts that are arranged on contact surfaces of an active top side of the semiconductor chip. The contact surfaces are surrounded by a passivation layer that covers the active top side while leaving exposed the contact surfaces. The passivation layer includes thickened portions that surround the contact surfaces. The semiconductor chip formed with thickened portions around the contact surfaces is protected from delamination during packaging of the semiconductor chip to form a semiconductor device.

Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.

Abstract: A package substrate strip having a reserved plating bar and a metal surface treatment method thereof are provided. The metal surface treatment method forms a conductive layer connecting the reserved plating bar and bonding pads of the package substrate stripe and further forms an isolating layer covering the conductive layer. By original plating bars and the reserved plating bar, an anti-oxidation layer can be simultaneously formed on finger contacts, first ball pads electrically connected to the finger contacts, and second ball pads electrically connected to the bonding pads. The package substrate strip and the method for metal surface treatment thereof can simplify manufacturing process, reduce production cost, and improve production efficiency and yield. Furthermore, a chip package applying the package substrate strip is also provided.

Abstract: In a semiconductor device, a plurality of interconnections are formed in an interconnection formation insulating interlayer, and a plurality of reinforcing elements are substantially evenly formed in blank areas of the interconnection insulating interlayer in which no interconnection is formed. A wire-bonding electrode pad is provided above the interconnection formation insulating interlayer so that a pad area, on which the wire-bonding electrode pad is projected, is defined on the interconnection formation insulating interlayer. A part of the reinforcing elements included in the pad area features a larger size than that of the remaining reinforcing elements.

Abstract: An embedded semiconductor chip structure and a method for fabricating the same are proposed. The structure comprises: a carrier board, therewith a plurality of through openings formed in the carrier board, and through trenches surrounding the through openings in the same; a plurality of semiconductor chips received in the through openings of the carrier board. Subsequently, cutting is processed via the through trenches. Thus, the space usage of the circuit board and the layout design are more efficient. Moreover, shaping time is also shortened.

Abstract: This invention provides a semiconductor device and a manufacturing method thereof which can minimize deterioration of electric characteristics of the semiconductor device without increasing an etching process. In the semiconductor device of the invention, a pad electrode layer formed of a first barrier layer and an aluminum layer laminated thereon is formed on a top surface of a semiconductor substrate. A supporting substrate is further attached on the top surface of the semiconductor substrate. A second barrier layer is formed on a back surface of the semiconductor substrate and in a via hole formed from the back surface of the semiconductor substrate to the first barrier layer. Furthermore, a re-distribution layer is formed in the via hole so as to completely fill the via hole or so as not to completely fill the via hole. A ball-shaped terminal is formed on the re-distribution layer.

Abstract: A pattern matched pair of a front metal interconnect layer and a back metal interconnect layer having matched thermal expansion coefficients are provided for a reduced warp packaging substrate. Metal interconnect layers containing a high density of wiring and complex patterns are first developed so that interconnect structures for signal transmission are optimized for electrical performance. Metal interconnect layers containing a low density wiring and relatively simple patterns are then modified to match the pattern of a mirror image metal interconnect layer located on the opposite side of the core and the same number of metal interconnect layer away from the core. During this pattern-matching process, the contiguity of electrical connection in the metal layers with a low density wiring may become disrupted. The disruption is healed by an additional design step in which the contiguity of the electrical connection in the low density is reestablished.

Abstract: An insulating layer 12 is formed as a surface layer of electronic circuit chip 10. A conductor interconnect 14 is formed in the insulating layer 12. The conductor interconnect 14 is exposed in the surface of the insulating layer 12. A solder wetting metallic film 16 (a metallic film) is formed on a portion of the conductor interconnect 14 to be exposed in the surface of the insulating layer 12. Typical metallic material (second metallic material) available for composing the solder wetting metallic film 16 includes a material that requires higher free energy for forming an oxide thereof, as compared with a free energy required for forming an oxide of the metallic material composing the conductor interconnect 14.

Abstract: A method including depositing a suspension of a colloid comprising an amount of nano-particles of a ceramic material on a substrate; and thermally treating the suspension to form a thin film. A method including depositing a plurality of nano-particles of a ceramic material to pre-determined locations across a surface of a substrate; and thermally treating the plurality of nano-particles to form a thin film. A system including a computing device comprising a microprocessor, the microprocessor coupled to a printed circuit board through a substrate, the substrate comprising at least one capacitor structure formed on a surface, the capacitor structure comprising a first electrode, a second electrode, and a ceramic material disposed between the first electrode and the second electrode, wherein the ceramic material comprises columnar grains.

Abstract: The invention relates to a metal-ceramic substrate for electric circuits or modules, said substrate including a ceramic layer which is provided with at least one metallic layer of a first type applied to a surface of said ceramic layer in a plane manner. An insulating layer made up of a glass-containing material is applied to at least one partial region of a surface of the metallic layer of the first type, said surface opposing the ceramic layer, and a metallic layer of a second type is applied to the insulating layer, the insulating layer and the metallic layer of a second type respectively being thinner then the ceramic layer and the metallic layer of the first type.

Abstract: A die package generally including (A) ground paths routing a power ground from a ground power set of contact pads in a first conductive layer to a ground ring in a second conductive layer, (B) core paths routing a core voltage from a core power set of contact pads in the first conductive layer to a core ring in the second conductive layer, and (C) input/output voltage paths routing input/output voltages from an input/output power set of contact pads in the first conductive layer to an input/output ring in the second conductive layer, (i) the input/output ring surrounding the core ring, (ii) the ring being configured to power input and output circuits of the die, (iii) the input/output ring being split into ring segments isolated from each other and (iv) at least one particular ring segment having a length of less than a single connector pitch.

Abstract: A semiconductor device is made by providing a sacrificial substrate, forming a first insulating layer over the sacrificial substrate, forming a first passivation layer over the first insulating layer, forming a second insulating layer over the first passivation layer, forming an integrated passive device over the second insulating layer, forming a wafer support structure over the integrated passive device, removing the sacrificial substrate to expose the first insulating layer after forming the wafer support structure, and forming an interconnect structure over the first insulating layer in electrical contact with the integrated passive device. The integrated passive device includes an inductor, capacitor, or resistor. The sacrificial substrate is removed by mechanical grinding and wet etching. The wafer support structure can be glass, ceramic, silicon, or molding compound.

Abstract: An embodiment of a package for Micro-Electro-Mechanical Systems of the MEMS type comprising a base for the assembly of said MEMS and a protective envelope, for containing the MEMS. The base is a multi-layer structure with at least one layer of composite material to make a substrate and at least one flexible wing projecting from the substrate, such base being a monolithic element suitable for being connected to external connection tracks.

Abstract: A heat dissipation plate having a lamination of a copper layer, a molybdenum layer and a graphite layer, and outer copper layers each provided on a surface of the lamination, is disclosed. And also a semiconductor device using the heat dissipation plate is disclosed.

Abstract: As for electrode pads for a semiconductor integrated circuit element, some of electrode pads for signal transmission are coupled to Ti films. Others of the electrode pads for signal transmission are coupled to electrode pads through wiring routed in multilayer wiring. Electrode pads for power supply are coupled to electrode pads to which power lines at potentials different from each other are coupled through wiring. The electrode pads are also coupled to Al foils (anodes). Electrode pads for grounding are coupled to electrode pads to which ground lines are coupled through wiring. The electrode pads are also coupled to conductive polymer films (cathodes).

Abstract: In a semiconductor device, re-wiring is provided on a circuit element formation region of a semiconductor substrate. A columnar electrode for connection with a circuit board is provided on the rewiring. A first insulating film is provided over the semiconductor substrate excluding a connection pad, and a ground potential layer connected to a ground potential is provided on an upper surface of the first insulating film. A re-wiring is provided over the ground potential layer with a second insulating film interposed. The ground potential layer serves as a barrier layer for preventing crosstalk between the re-wiring and circuit element formation region. A thin-film circuit element is provided on the second insulating film, and a second ground potential layer is provided as a second barrier layer over the thin-film circuit element with an insulating film interposed. Re-wiring is provided over the second ground potential layer.

Abstract: An electronic device and coupled flexible circuit board and method of manufacturing. The electronic device is coupled to the flexible circuit board by a plurality of Z-interconnections. The electronic device includes a substrate with electronic components coupled to it. The substrate also has a plurality of device electrical contacts coupled to its back surface that are electrically coupled to the electronic components. The flexible circuit board includes a flexible substrate having a front surface and a back surface and a plurality of circuit board electrical contacts coupled to the front surface of the flexible substrate. The plurality of circuit board electrical contacts correspond to plurality of device electrical contacts. Each Z-interconnection is electrically and mechanically coupled to one device electrical contact and a corresponding circuit board electrical contact.

Abstract: In the semiconductor device, a control power MOSFET chip 2 is disposed on the input-side plate-like lead 5, and the drain terminal DT1 is formed on the rear surface of the chip 2, and the source terminal ST1 and gate terminal GT1 are formed on the principal surface of the chip 2, and the source terminal ST1 is connected to the plate-like lead for source 12. Furthermore, a synchronous power MOSFET chip 3 is disposed on the output-side plate-like lead 6, and the drain terminal DT2 is formed on the rear surface of the chip 3 and the output-side plate-like lead 6 is connected to the drain terminal DT2. Furthermore, source terminal ST2 and gate terminal GT2 are formed on the principal surface of the synchronous power MOSFET chip 3, and the source terminal ST2 is connected to the plate-like lead for source 13. The plate-like leads for source 12 and 13 are exposed, and therefore, it is possible to increase the heat dissipation capability of the MCM 1.