Abstract: A detector including an electrode formed from a first layer of conductive material, a readout line formed from a second layer of conductive material, and a via electrically connecting the readout line and the electrode. In one embodiment, the detector includes a source electrode and a drain electrode formed from the first layer of conductive material, and a data line formed from the second layer of conductive material, such that the source and drain electrodes are vertically offset from the data line. Alternatively, in another embodiment, the detector includes a gate electrode formed from the first layer of conductive material, and a scan line formed from the second layer of conductive material, such that the gate electrode is vertically offset from the scan line.

Abstract: In one embodiment, an edge seal region of a semiconductor die is formed by forming a first dielectric layer on a surface of a semiconductor substrate near an edge of the semiconductor die and extending across into a scribe grid region of the semiconductor substrate. Another dielectric layer is formed overlying the first dielectric layer. An opening is formed through the first and second dielectric layers. The second dielectric layer is used as a mask for forming a doped region on the semiconductor substrate through the opening. A metal is formed that electrically contacts the doped region and an exterior edge of the first dielectric layer within the opening.

Abstract: An electronic component includes a number of leads and at least one cooling element. The bottom surface of the cooling element is exposed and the material of the cooling element is different from the material of the leads. At least one semiconductor chip is provided on the cooling element. An encapsulation compound covers at least part of the leads, at least part of the semiconductor chip(s), and at least part of the cooling element(s).

Abstract: This research discloses an ultra wideband system-on-package (SoP). The SoP includes a package body; a first integrated circuit mounted on the package body; a first signal transmission unit connected to the first integrated circuit; a signal via connected to the first signal transmission unit and including a slab line and a trough line; and a second signal transmission unit connected to the signal via. The technology of the present research can transmit ultra broadband signals by minimizing discontinuity of signals appearing during vertical transition that occurs in the course of a signal transmission to/from an external circuit, and a fabrication method thereof.

Abstract: A semiconductor device has a first interconnect structure formed over a first side of a substrate. A semiconductor die is mounted to the first interconnect structure. An encapsulant is deposited over the semiconductor die and first interconnect structure for structural support. A portion of a second side of the substrate, opposite the first side of the substrate, is removed to reduce its thickness. The encapsulant maintains substrate robustness during thinning process. A TSV is formed through the second side of the substrate to the first interconnect structure. A second interconnect structure is formed in the TSV. The TSV has a first insulating layer formed over the second side of the substrate and first conductive layer formed over the first insulating layer and into the TSV. The second interconnect structure has a second conductive layer formed over the first conductive layer in an area away from the TSV.

Abstract: A semiconductor device, includes: an organic multilayer wiring substrate having an inner conductive layer; a semiconductor element mounted and connected on one surface of the wiring substrate; and a plurality of solder balls disposed on the other surface in a grid array. A defect portion is formed at an area corresponding to a corner solder ball disposed at an outer peripheral corner, or at an area corresponding to the corner solder ball and peripheral solder balls at the inner conductive layer. Temperature rises of the solder balls disposed in a vicinity of the corner are suppressed, and therefore, the semiconductor device of which fatigue life is prolonged and superior in reliability can be obtained.

Abstract: A contact that takes a structure to laminate a protective conductive film over a metal film has a high hardness of the protective conductive film; therefore, a damage of contact surface made by contacting with an electrode of an inspection apparatus can be prevented in an inspection before boding FPC. However, the protective conductive film has higher resistivity compared to the metal film; therefore, contact resistivity with FPC gets higher, and power consumption gets bigger in the condition of using the display device.

Abstract: A device mounting board for a device to be mounted on, comprising: a substrate; and a laminated film composed of a plurality of insulating layers formed on one side of the substrate. Here, any of the second and subsequent insulating layers from the substrate is a photosolder resist layer containing a cardo type polymer. The photosolder resist layer has a thickness smaller than that of the insulating resin film arranged between the photosolder resist layer and the substrate.

Abstract: Provided are an embedded wiring board and a method of manufacturing the same. The embedded wiring board includes: a printed circuit board (PCB) including a first surface and a second surface, the first surface having a concave portion; through electrodes penetrating the PCB; a semiconductor device group embedded in the concave portion of the PCB, the semiconductor device group including bonding pads exposed in a direction of the first surface of the PCB; bumps disposed on the bonding pads, exposed in the direction of the first surface of the PCB; and a film substrate including a first surface and a second surface, the first surface including connection electrode patterns that are electrically connected to the bumps and the through electrodes, the film substrate having penetrated openings.

Abstract: A transparent board is positioned on a support board provided with a positioning mark, and a release material is provided. A semiconductor element is then positioned so that the electrode element faces upward, and the support board is then removed. An insulating resin is then formed on the release material so as to cover the semiconductor element; and a via, a wiring layer, an insulation layer, an external terminal, and a solder resist are then formed. The transparent board is then peeled from the semiconductor device through the use of the release material. A chip can thereby be mounted with high precision, there is no need to provide a positioning mark during mounting of the chip on the substrate in the manufacturing process, and the substrate can easily be removed. As a result, a semiconductor device having high density and a thin profile can be manufactured at low cost.

Abstract: A microelectronic package includes a first substrate (120) having a first surface area (125) and a second substrate (130) having a second surface area (135). The first substrate includes a first set of interconnects (126) having a first pitch (127) at a first surface (121) and a second set of interconnects (128) having a second pitch (129) at a second surface (222). The second substrate is coupled to the first substrate using the second set of interconnects and includes a third set of interconnects (236) having a third pitch (237) and internal electrically conductive layers (233, 234) connected to each other with a microvia (240). The first pitch is smaller than the second pitch, the second pitch is smaller than the third pitch, and the first surface area is smaller than the second surface area.

Abstract: There is provided a wiring substrate for connecting a mounting board on one surface thereof and mounting an integrated circuit chip on the opposite surface to the surface. The wiring substrate has a conductive connecting portion penetrating the substrate for connecting to at least a portion of a wiring layer of the integrated circuit chip, with the portion of a wiring layer formed on the substrate, and an insulating portion formed at a lateral side of the connecting portion for surrounding the connecting portion via a portion of the wiring substrate.

Abstract: A semiconductor device includes a semiconductor element, an electrode formed on the semiconductor element, and a protective member covering the semiconductor element. The protective member is formed with a through-hole facing the electrode. In the through-hole, a wiring pattern is formed to be electrically connected to the electrode.

Abstract: A method of manufacturing a semiconductor package may include: forming a first board; forming second boards, in each of which at least one cavity is formed; attaching the second boards to both sides of the first board, such that the second boards are electrically connected with the first board; and connecting at least one component with the first board by a flip chip method by embedding the component in the cavity. The method can prevent damage to the semiconductor chips and lower manufacturing costs, while the connection material may also mitigate stresses, to prevent cracking in the boards and semiconductor chips, while preventing defects such as bending and warpage. Defects caused by temperature changes may also be avoided. Furthermore, it is not necessary to use an underfill in the portions where the semiconductor chips are connected with the printed circuit board, which allows for easier reworking and lower costs.

Abstract: A structure includes a semiconductor substrate having semiconductor devices formed on or in the substrate. An interconnecting metallization structure is formed over and connected to the devices. The interconnecting metallization structure including at least one dielectric layer. A passivation layer is deposited over the interconnecting metallization structure and the dielectric layer. At least one metal contact pad and at least one dummy metal structure are provided in the passivation layer. The contact pad is conductively coupled to at least one of the devices. The dummy metal structure is spaced apart from the contact pad and unconnected to the contact pad and the devices.

Abstract: An integrated circuit package system is provided including providing an integrated circuit die having a contact pad, forming a protection cover over the contact pad, forming a passivation layer having a first opening over the protection cover with the first opening exposing the protection cover, developing a conductive layer over the passivation layer, and forming a pad opening in the protection cover for exposing the contact pad.

Abstract: A package substrate having an electrically connecting structure are provided. The package substrate include: a package substrate substance with at least a surface having a plurality of electrically connecting pads formed thereon, allowing an insulating protective layer to be formed on the surface of the package substrate substance and the electrically connecting pads and formed with a plurality of openings corresponding in position to the electrically connecting pads so as to expose a portion of the electrically connecting pads, respectively; and a metal layer provided on an exposed portion of the electrically connecting pads, walls of the openings of the insulating protective layer, and a circular portion of the insulating protective layer encircling each of the openings thereof, and provided with a slope corresponding in position to a bottom rim of each of the openings. Accordingly, solder bleeding and short circuits are prevented.

Abstract: A semiconductor process is provided. First, a silicon base is provided. Next, a surface of the silicon base is partially exposed and at least a stair structure is formed on the silicon base by etching the surface of the silicon base. The stair structure has a first notch with a first depth and a second notch with a second depth. The first depth is smaller than the second depth, and a diameter of the first notch is larger than a diameter of the second notch. A final insulating layer and a metal seed layer are sequentially formed on the stair structure. A patterned photoresist layer is formed on the metal seed layer. A circuit layer coving exposed portions of the metal seed layer located above the first notch is formed. The patterned photoresist layer and portions of the metal seed layer disposed below the patterned photoresist layer are then removed.

Abstract: The present invention has for its object to provide a multilayer printed circuit board which is very satisfactory in facture toughness, dielectric constant, adhesion and processability, among other characteristics. The present invention is directed to a multilayer printed circuit board comprising a substrate board, a resin insulating layer formed on said board and a conductor circuit constructed on said resin insulating layer, wherein said resin insulating layer comprises a polyolefin resin.

Abstract: An integrated circuit package system comprising: providing a package substrate; attaching an integrated circuit over the package substrate; and attaching a side substrate adjacent the integrated circuit over the package substrate.

Abstract: A semiconductor module includes a multilayer substrate. The multilayer substrate includes a first metal layer and a first ceramic layer over the first metal layer. An edge of the first ceramic layer extends beyond an edge of the first metal layer. The multilayer substrate includes a second metal layer over the first ceramic layer and a second ceramic layer over the second metal layer. An edge of the second ceramic layer extends beyond an edge of the second metal layer. The multilayer substrate includes a third metal layer over the second ceramic layer.

Abstract: An integrated circuit package system comprising: providing an integrated circuit die having an active side; forming a first internal stacked module and a second internal stacked module over the active side of the integrated circuit die; and coupling an electrical interconnect between the first internal stacked module or the second internal stacked module and the active side.

Abstract: A printed wiring board including a core substrate, a build-up layer formed over the core substrate and including a first insulating layer, a conductor layer formed over the first insulating layer, and a second insulating layer formed over the conductor layer, and one or more wiring patterns formed over the first insulating layer. The conductor layer includes conductor portions, and the conductor portions have notched portions, respectively, facing each other across the wiring pattern.

Abstract: A wired circuit board assembly sheet has a plurality of wired circuit boards, distinguishing marks for distinguishing defectiveness of the wired circuit boards, and a supporting sheet for supporting the plurality of wired circuit boards and the distinguishing marks. Each of the distinguishing marks has an indication portion for indicating a specified one of the wired circuit boards.

Abstract: A virtual wire assembly that includes a substantially electrically-nonconductive substrate and a plurality of hermetic feedthroughs including a conductive region extending transversely through the substrate to form a conductive pathway with accessible surfaces at opposing ends thereof, wherein each conductive pathway is electrically isolated from other conductive pathways. In certain embodiments of this aspect of the invention, the substantially electrically-nonconductive substrate is a semiconductor device, and the conductive regions each include an n-type or a p-type doped semiconductor material.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric and a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide post-passivation interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick passivation interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: A wireless IC device includes a radiation plate, a wireless IC chip, and a substrate provided with a feed circuit that includes a resonant circuit and/or the matching circuit including an inductance element and that is electromagnetically coupled to the radiation plate. The substrate is made of a resin material. A recess is provided in a first main surface of the substrate. The substrate is provided with a wiring electrode arranged along a bottom surface and an inner circumferential surface of the recess and the first main surface of the substrate and electrically connected to the feed circuit, and a wedge member made of a different material from the resin material and extending between the bottom surface of the recess and a second main surface of the substrate spaced apart from the wiring electrode. The wireless IC chip is mounted in the recess and coupled to the wiring electrode.

Abstract: A plurality of IC regions are formed on a semiconductor wafer, which is cut into individual chips incorporating ICs, wherein wiring layers and insulating layers are sequentially formed on a silicon substrate. In order to reduce height differences between ICs and scribing lines, a planar insulating layer is formed to cover the overall surface with respect to ICs, seal rings, and scribing lines. In order to avoid occurrence of breaks and failures in ICs, openings are formed to partially etch insulating layers in a step-like manner so that walls thereof are each slanted by prescribed angles ranging from 20° to 80°. For example, a first opening is formed with respect to a thin-film element section, and a second opening is formed with respect to an external-terminal connection pad.

Abstract: Provided is an adhesive composition for a semiconductor device. For example, the adhesive composition comprises a binder resin and a silicon carbide filler. The silicon carbide filler has relatively high thermal conductivity and a relatively low coefficient of thermal expansion (CTE). Accordingly, the adhesive composition containing the silicon carbide filler exhibits improved heat dissipation performance and electrical performance due to high thermal conductivity and shows inhibition of delamination or cracking of semiconductor devices due to low CTE. The silicon carbide has high thermal conductivity, but is electrically non-conductive. Therefore, an electrically conductive adhesive can be obtained by additional incorporation of a silver (Ag) filler into the binder resin.

Abstract: A multilayer wiring layer 400, a first inductor 310 and a second inductor 320 are formed on a substrate 10. The multilayer wiring layer is formed by alternately stacking an insulating layer and a wiring layer in this order t or more times (t?3). The first inductor 310 is provided in the nth wiring layer in the multilayer wiring layer 400. The second inductor 320 is provided in the mth wiring layer in the multilayer wiring layer 400 (t?m?n+2) and positioned above the first inductor 310. No inductor is provided in any of the wiring layers positioned between the nth wiring layer and the mth wiring layer to be positioned above the first inductor 310. The first inductor 310 and the second inductor 320 constitute a signal transmitting device 300 which transmits an electrical signal in either of two directions.

Abstract: A circuit module includes an electronic component, a ceramic multilayer substrate and a resin wiring substrate. The ceramic multilayer substrate is provided with a wiring layer disposed on top thereof and a cavity in which the electronic component is mounted, wherein a space between the electronic component and the cavity is filled with a thermosetting resin and a surface of the filled cavity is planarized. The resin wiring substrate has an insulating adhesive layer disposed at one side thereof and provided with at least one opening filled with a conductive resin. The ceramic multilayer substrate and the resin wiring substrate are bonded by the insulating adhesive layer, and the wiring layer on the ceramic multilayer substrate is electrically connected with the conductive resin.

Abstract: A new method is provided for the creation of interconnect lines. Fine line interconnects are provided in a first layer of dielectric overlying semiconductor circuits that have been created in or on the surface of a substrate. A layer of passivation is deposited over the layer of dielectric, a thick second layer of dielectric is created over the surface of the layer of passivation. Thick and wide interconnect lines are created in the thick second layer of dielectric. The first layer of dielectric may also be eliminated, creating the wide thick interconnect network on the surface of the layer of passivation that has been deposited over the surface of a substrate.

Abstract: Provided are a high reliability stack module fabricated at low cost by using simplified processes, a card using the stack module, and a system using the stack module. In the stack module, unit substrates are stacked with respect to each other and each unit substrate includes a selection terminal. First selection lines are electrically connected to selection terminals of first unit substrates disposed in odd-number layers, pass through some of the unit substrates, and extend to a lowermost substrate of the unit substrates. Second selection lines are electrically connected to selection terminals of second unit substrates disposed in even-number layers, pass through some of the unit substrates, and extend to the lowermost substrate of the unit substrates. The selection terminal is disposed between the first selection lines and the second selection lines.

Abstract: Semiconductor device has a semiconductor chip embedded in an insulating layer. A semiconductor device comprises a semiconductor chip formed to have external connection pads and a positioning mark that is for via formation; an insulating layer containing a non-photosensitive resin as an ingredient and having a plurality of vias; and wiring electrically connected to the external connection pads through the vias and at least a portion of which is formed on the insulating layer. The insulating layer is formed to have a recess in a portion above the positioning mark. The bottom of the recess is the insulating layer alone. Vias have high positional accuracy relative to the mark.

Abstract: A semiconductor device having a voltage regulator is disclosed that does not have an external output condenser for phase compensation. The semiconductor device includes a semiconductor chip that includes a voltage regulator, a power supply input terminal, a ground terminal, and an output terminal for outputting a produced constant voltage; and a phase compensation condenser that is connected between the output terminal and the ground terminal for phase compensation of the voltage regulator. The semiconductor chip and the phase compensation condenser are accommodated in a single package.

Abstract: A semiconductor chip includes an integrated circuit region, at least one alignment indicator region and a seal-ring. The alignment indicator region is disposed near the integrated circuit region. The seal-ring surrounding the integrated circuit region is disposed outside of the integrated circuit region, and is formed as a mark for alignment on the alignment indicator region at a corner of the semiconductor chip. A manufacturing process of the seal-ring structure is also disclosed.

Abstract: A die having a base formed of a first material is connected to a board having a base formed of a second material. An interposer having a coefficient of thermal expansion intermediate coefficients of thermal expansion of the first and second materials is positioned between the die and the board.

Abstract: By dividing a single chip area into individual sub-areas, a thermally induced stress in each of the sub-areas may be reduced during operation of complex integrated circuits, thereby enhancing the overall reliability of complex metallization systems comprising low-k dielectric materials or ULK material. Consequently, a high number of stacked metallization layers in combination with increased lateral dimensions of the semiconductor chip may be used compared to conventional strategies.

Abstract: Layers suitable for stacking in three dimensional, multi-layer modules are formed by interconnecting a ball grid array electronic package to an interposer layer which routes electronic signals to an access plane. The layers are under-filled and may be bonded together to form a stack of layers. The leads on the access plane are interconnected among layers to form a high-density electronic package.

Abstract: A semiconductor package and a method for making the same, whereby the semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, and second and third metal layers. The substrate has a surface having at least first and second pads. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer.

Abstract: A semiconductor wafer may include, but is not limited to, the following elements. A semiconductor substrate has a device region and a dicing region. A stack of inter-layer insulators may extend over the device region and the dicing region. Multi-level interconnections may be disposed in the stack of inter-layer insulators. The multi-level interconnections may extend in the device region. An electrode layer may be disposed over the stack of inter-layer insulators. The electrode layer may extend in the device region. The electrode layer may cover the multi-level interconnections. A cracking stopper groove may be disposed in the dicing region. The cracking stopper groove may be positioned outside the device region.

Abstract: A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.

Abstract: An embedded chip package structure is proposed. The embedded chip package structure includes a supporting board with a protruding section, a semiconductor chip formed on the protruding section of the supporting board, a dielectric layer formed on the supporting board and the semiconductor chip, and a circuit layer formed on the dielectric layer. The circuit layer is electrically connected to electrode pads of the semiconductor chip via a plurality of conducting structures formed inside the dielectric layer such that the semiconductor chip can be electrically connected to an external element through the circuit layer. By varying the thicknesses of the protruding section, the dielectric layer and the supporting board, warpage of the package structure resulted from temperature change during the fabrication process can be prevented.

Abstract: An embedded chip package includes a substrate, a semiconductor structure, an encapsulating material layer and a plurality of conductive vias. Herein the substrate includes at least a dielectric layer and at least a patterned circuit layer disposed on the dielectric layer. The semiconductor structure is disposed on the substrate and has a plurality of electrical bonding pads, and the electrical bonding pads contact the dielectric layer. The encapsulating material layer is disposed on the substrate and around the semiconductor structure. In addition, a plurality of conductive vias is disposed in the substrate to electrically connect the patterned circuit layer to the electrical bonding pads.

Abstract: Provided is a semiconductor device in which a plurality of chips are packaged without increasing the thickness of the package. A plurality of semiconductor elements (a first and a second semiconductor elements) that are packaged in the semiconductor device are overlaid with each other. Specifically, the first semiconductor element is fixed on the top surface of the first island while the second semiconductor element is fixed on the bottom surface of the second island. Furthermore, each of the islands (a first and a second islands) on which the semiconductor elements are respectively mounted in the present invention provides a structure has an irregular shape, and the islands are overlaid with each other along the sides of the semiconductor element to be mounted.

Abstract: A passive component incorporating interposer includes a double-sided circuit board (1) having a wiring layer (8) on both sides, a passive component (2) mounted on the wiring layer (8) on one surface of the double-sided circuit board (1), a second insulating layer (3) made of woven fabric or non-woven fabric or inorganic filler and thermosetting resin laminated on the surface of the double-sided circuit board (1) mounted with the passive component (2), a first insulating layer (4) made of woven fabric or non-woven fabric or inorganic filler and thermosetting resin laminated on the other surface of the double-sided circuit board (1) not mounted with the passive component (2), first and second wiring layers (5, 6) formed on the first and second insulating layers (3, 4), and a through hole (7) for electrically connecting the wiring layers (8) disposed on both surfaces of the double-sided circuit board (1) and the first and second wiring layers (5, 6), where the first wiring layer (5) is formed to enable mounting

Abstract: A semiconductor chip package having multiple leadframes is disclosed. Packages can include a first leadframe having a first plurality of electrical leads and a die attach pad having a plurality of tie bars, a second leadframe generally parallel to the first leadframe and having a second plurality of electrical leads, and a mold or encapsulant. Tie bars can be located on three main sides of the die attach pad, but not the fourth main side. Gaps in the first and second plurality of electrical leads can be enlarged or aligned with each other to enable the elimination of mold flash outside the encapsulated region, which can be accomplished with mold cavity bar protrusions. Additional components can include a primary die, a secondary die, an inductor and/or a capacitor. The first and second leadframes can be substantially stacked atop one another, and one or both leadframes can be leadless leadframes.

Abstract: A wiring board includes a substrate core and a ceramic chip to be embedded therein. The substrate core has a housing opening portion opening at a core main surface. The ceramic chip is accommodated in the housing opening portion so that the core main surface and a chip first main surface face the same way. The ceramic chip includes a plurality of second terminal electrodes comprised of a metallized layer and formed on the chip second main surface so as to protrude therefrom. A projecting portion, disposed on the second main surface side so as to surround a plurality of the second terminal electrodes, is formed on the chip second main surface so as to protrude therefrom.

Abstract: An alternating current (AC) light emitting device is revealed. The AC light emitting device includes a substrate and a plurality of light emitting units arranged on the substrate. The light emitting unit consists of a first semiconductor layer, a light emitting layer, a second semiconductor layer, at least one electrode and at least one second electrode respectively arranged on the first semiconductor layer and the second semiconductor layer from bottom to top. The plurality of light emitting units is coupled to at least one adjacent light emitting unit by a plurality of conductors. By the plurality of conductors that connect light emitting units with at least one adjacent light emitting unit, an open circuit will not occur in the AC light emitting device once one of the conductors is broken.

Abstract: A submount for red, green, and blue LEDs is described where the submount has thermally isolated trenches and/or holes in the submount so that the high heat generated by the green/blue AlInGaN LEDs is not conducted to the red AlInGaP LEDs. The submount contains conductors to interconnect the LEDs in a variety of configurations. In one embodiment, the AlInGaP LEDs are recessed in the submount so all LEDs have the same light exit plane. The submount may be used for LEDs generating other colors, such as yellow, amber, orange, and cyan.