Abstract: A structure of a semiconductor device package having a substrate with a die receiving through hole, a connecting through hole structure and a contact pad. A die is disposed within the die receiving through hole. A surrounding material is formed under the die and filled in the gap between the die and the sidewall of the die receiving though hole. Dielectric layers are formed on the both side surface of the die and the substrate. Re-distribution layers (RDL) are formed on the dielectric layers and coupled to the contact pads. Protection layers are formed over the RDLs.

Abstract: A module includes a semiconductor chip and a conductive layer arranged over the semiconductor chip. The module also includes a spacer structure arranged to deflect the conductive layer away from the semiconductor chip.

Abstract: In an embodiment, an integrated circuit is provided. The integrated circuit may include an active area extending along a first direction corresponding to a current flow direction through the active area, a contact structure having an elongate structure. The contact structure may be electrically coupled with the active area. Furthermore, the contact structure may be arranged such that the length direction of the contact structure forms a non-zero angle with the first direction of the active area.

Abstract: Provided is a semiconductor device having a substrate, a semiconductor chip flip-chip mounted on the substrate, and a stacked film provided in a gap between the substrate and the semiconductor chip. The stacked film is composed of a protective film covering the surface of the substrate, and an underfill film formed between the solder resist film and the semiconductor chip. The protective film is roughened on the contact surface brought into contacting said underfill film.

Abstract: A manufacturing method of electronic components includes forming a first insulation layer on a substrate, forming a plurality of passive elements on the first insulation layer, forming a second insulation layer on the passive elements, forming a plurality of conductor layers electrically connected to the respective passive elements, on the outer side of the second insulation layer to be exposed to an upper surface of each electronic component, and forming grooves between the electronic components including the respective passive elements to expose side surfaces of each electronic component and parts of the conductor layers from the side surfaces of each electronic component. The manufacturing method further including plating a plurality of external electrodes on the respective conductor layers exposed to the upper surface and the side surfaces of each electronic component, and cutting the substrate to completely separate into individual electronic components.

Abstract: A disclosed semiconductor device includes a reinforcing board having first and second faces, an electronic part accommodating portion penetrating the reinforcing board, a through hole, an electronic part having a front face on which an electrode pad is formed and a back face, a through electrode installed inside the through hole, a first sealing resin filling a gap between the through electrode and an inner wall of the through hole, a second sealing resin filled into the electronic part accommodating portion while causing the bonding face of the electrode pad of the electronic part accommodating portion to be exposed to an outside, and a multi-layered wiring structure configured to include insulating layers laminated on the first face of the reinforcing board and an interconnection pattern, wherein the interconnection pattern is directly connected to the electrode pad of the electronic part and the through electrode.

Abstract: A structurally robust power switching assembly, that has a first rigid structural unit, defining a first unit major surface that is patterned to define a plurality of mutually electrically isolated, electrically conductive paths. Also, a similar, second rigid structural unit is spaced apart from the first unit major surface. Finally, a transistor is interposed between and electrically connected to the first unit major surface and the second unit major surface.

Abstract: A semiconductor arrangement has a silicon body with a first surface and a second surface and a thick metal layer arranged on at least one surface of the silicon body. The thickness of the thick metal-layer is at least 10 micrometers (?m).

Abstract: Disclosed are a semiconductor package and a manufacturing method thereof. The semiconductor package can include a semiconductor substrate, having one surface on which a conductive pad is formed; an insulating layer, being formed on one surface of the semiconductor substrate; a metal post, penetrating through the conductive pad, the semiconductor substrate, and the insulating layer; and an outer-layer circuit, being electrically connected to the metal post. With the present invention, it can become unnecessary to form an additional via for electrically connecting both surfaces of the semiconductor substrate, thereby simplifying the manufacturing process, reducing the manufacturing cost, and improving the coupling reliability.

Abstract: A power semiconductor module is disclosed. One embodiment includes a multilayer substrate having a plurality of metal layers and a plurality of ceramic layers, where the ceramic layers are located between the metal layers.

Abstract: A cellular telephone is provided with a wearable housing, desirably in a form which can be concealed in the user's clothing, wallet, or other place. The housing may be devoid of switches or buttons for controlling the cellular telephone, and control inputs can be provided through free space communications such as a short-range radio link. A module for use in portable communications devices includes chips superposed on one another on a stack, and incorporates an interposer for facilitating connections between the chips.

Abstract: A semiconductor chip has a main surface, a back surface and a plurality of side surfaces. A plurality of electrodes is provided on the main surface of the semiconductor chip so as to be arranged in a plurality of lines. An insulating film is formed on the main surface of the semiconductor chip so as to expose at least one of the plurality of electrodes. A plurality of leads are formed on the insulating film, each of the plurality of leads having a first end and a second end, and the first end of the lead being connected to the one of the plurality of electrodes. A base resin film is formed on the insulting film and the plurality of leads, the base resin film having a plurality of electrodes holes exposing a part of the second end of each of the leads and a device hole in which the first end of the lead and the one of the plurality of electrodes are located.

Abstract: In a substrate for a stacking-type semiconductor device including a connection terminal provided for a connection with a semiconductor chip to be stacked and an external terminal connected to the connection terminal through a conductor provided in a substrate, connection terminals of a power supply, a ground and the like, which terminals have an identical node, are electrically continuous with each other. Thus, it is possible to facilitate an inspection of electrical continuity between each connection terminal and an external terminal corresponding to each connection terminal by minimum addition of inspecting terminals. Further, it is possible to improve reliability of a stacking-type semiconductor module.

Abstract: Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.

Abstract: A wiring device for a semiconductor device, a composite wiring device for a semiconductor device and a resin-sealed semiconductor device are provided, each of which is capable of mounting thereon a semiconductor chip smaller than conventional chips and being manufactured at lower cost. The wiring device electrically connects an electrode provided on a semiconductor chip with an external wiring device, and has an insulating layer, a metal substrate and a copper wiring layer. The metal substrate is provided on one side of the insulating layer. The copper wiring layer is provided on another side of the insulating layer. The wiring device has a semiconductor chip support portion provided on the side of the copper wiring layer with respect to the insulating layer. The copper wiring layer includes a first terminal, a second terminal and a wiring portion. The first terminal is connected with the electrode provided on the semiconductor chip. The second terminal is connected with the external wiring device.

Abstract: A package for one or more semiconductor die is described. A generally rectangular package includes two large terminals that occupy substantially the entire length of the package and provide low resistance connections. Additional connections may be provided preferably in a central portion of a short end of the package. BGA connections between the semiconductor die and the package substrate provide low impedance connections between the die and the package contacts. The package and connections facilitate current flow orthogonal to the longest package dimension maximizing conductor width and minimizing interconnection resistance.

Abstract: A die that includes a substrate having a first and second major surface is disclosed. The die has at least one unfilled through via passing through the major surfaces of the substrate. The unfilled through via serves as a vent to release pressure generated during assembly.

Abstract: A circuit carrier having a metal support layer, at least some portions of which are covered by a dielectric layer, the dielectric layer having a plurality of pores, with the pores being sealed by glass at least on the opposite side of the dielectric layer to the support layer.

Abstract: Disclosed is a heat dissipating circuit board, which includes a metal core including an insulating layer formed on the surface thereof, a circuit layer formed on the insulating layer and including a seed layer and a first circuit pattern, and a heat dissipating frame layer bonded onto the circuit layer using solder and having a second circuit pattern, and in which the heat dissipating frame layer is bonded onto the circuit layer not by a plating process but by using solder, thus reducing the cost and time of the plating process and relieving stress applied to the heat dissipating circuit board due to the plating process. A method of manufacturing the heat dissipating circuit board is also provided.

Abstract: Microelectronic packages are fabricated by stacking integrated circuits upon one another. Each integrated circuit includes a semiconductor layer having microelectronic devices and a wiring layer on the semiconductor layer having wiring that selectively interconnects the microelectronic devices. After stacking, a via is formed that extends through at least two of the integrated circuits that are stacked upon one another. Then, the via is filled with conductive material that selectively electrically contacts the wiring. Related microelectronic packages are also described.

Abstract: A laminated substrate for an integrated circuit package, including a core layer and at least one build-up layer located above only one side of said core layer. An integrated circuit package, including a laminated substrate and including an integrated circuit die placed above the side build-up layer.

Abstract: In accordance with the present invention, there is provided a semiconductor package and a fabrication method thereof. The semiconductor package is provided with a substrate made of metal, thereby improving efficiency of thermal emission from a semiconductor die mounted to the substrate, and simplifying the fabrication process for the substrate which reduces fabricating costs. Further, unlike a conventional land, a rivet electrically insulated with the substrate is inserted into a corresponding hole of the substrate, the upper and lower surfaces of the rivet being removed to form land, thereby simplifying the fabrication process for the substrate which further reduces fabricating costs.

Abstract: The present invention provides a technique capable of suppressing variations in the height of each solder ball where an NSMD is used as a structure for each land. Vias that extend through a wiring board are provided. Lands are formed at the back surface of the wiring board so as to be coupled directly to the vias respectively. The lands are respectively formed so as to be internally included in openings defined in a solder resist. Half balls are mounted over the lands respectively. Namely, the present invention has a feature in that the configuration of coupling between each of the lands and its corresponding via both formed at the back surface of the wiring board is taken as a land on via structure and a configuration form of each land is taken as an NSMD.

Abstract: A component includes a first semiconductor chip attached to a first carrier and second semiconductor chip attached to a second carrier. The first carrier has a first extension, which forms a first external contact element. The second carrier has a second extension, which forms a second external contact element. The first and the second carriers are arranged in such a way that the first and the second extension point in different directions.

Abstract: A system and method for forming an embedded chip package is disclosed. The embedded chip package includes a first chip portion having a plurality of pre-patterned re-distribution layers joined together to form a pre-patterned lamination stack, with the pre-patterned lamination stack having a die opening extending therethrough. The embedded chip package also includes a die positioned in the die opening and a second chip portion having at least one uncut re-distribution layer, with the second chip portion affixed to each of the first chip portion and the die and being patterned to be electrically connected to both of the first chip portion and the die.

Abstract: An onboard electric power control device which comprises a power unit, a control unit and a power source unit, in which: an opening portion of a case containing components of the power unit and an opening portion of a case containing components of the control unit are abutted so as to be coupled; a case of the power supply unit is fitted to an opening portion being provided on a side surface of the case of the power unit so that the both cases are coupled; the power unit and the control unit is connected by a flexible connecting conductor; and the connecting conductor is folded and is contained between a resin molded portion formed inside of the case of the power unit and a resin molded portion formed inside of the case of the control unit.

Abstract: In a semiconductor apparatus, a semiconductor element is mounted on a wiring substrate. Wiring patterns and protrusions are formed on a surface of a substrate with the wiring patterns extending on tops of the protrusions. The surface of the substrate on which the wiring patterns are formed are covered with an insulating layer. Surfaces of connection parts of the wiring patterns formed on the tops of the protrusions are formed with the surfaces of the connection parts exposed to a surface of the insulating layer on a level with the surface of the insulating layer or in a position lower than the surface of the insulating layer. The connection parts are formed as pads for connection formed in alignment with connection electrodes of the semiconductor element. The semiconductor element is mounted by making electrical connection to the connection parts by flip chip bonding.

Abstract: The present invention comprises a first substrate with a die formed on a die metal pad, a first and a second wiring circuits formed on the surfaces of the first substrate. A second substrate has a die opening window for receiving the die, a third wiring circuit is formed on top surface of the second substrate and a fourth wiring circuit on bottom surface of the second substrate. An adhesive material is filled into the gap between back side of the die and top surface of the first substrate and between the side wall of the die and the side wall of the die receiving through hole and the bottom side of the second substrate. During the formation, laser is introduced to cut the backside of the first substrate and an opening hole is formed in the first substrate to expose a part of the backside of the Au or Au/Ag metal layer of chip/die.

Abstract: A wafer level package includes a chip, a removable resin layer, a molding material, a dielectric layer, redistribution lines and a solder resist. The removable resin layer is formed to surround side surfaces and a lower surface of the chip. The molding material is formed on the lower surface of the removable resin layer. The dielectric layer is formed over the removable resin layer including the chip and having via holes to expose portions of the chip. The redistribution lines are formed on the dielectric layer including insides of the via holes to be connected to the chip. The solder resist layer is formed on the dielectric layer to expose portions of the redistribution lines.

Abstract: A flexible substrate used in a semiconductor package, a method of manufacturing the same, and a semiconductor package including the flexible substrate. A circuit pattern forming region is formed in an insulating substrate with a dented shape and a circuit pattern formed of a metallic material is formed in the circuit pattern forming region.

Abstract: An integrated circuit package including a first metal layer coupled to a bonding pad, a first redistribution layer coupled to the bonding pad, and a RDL to Metal (RTM) via coupled to a first surface of the metal layer and further coupled to a first surface of the first RDL is described. The IC package may further include additional metal layers and redistribution layers.

Abstract: The semiconductor device package structure includes a first die with a through silicon via (TSV) open from back side of the first die to expose bonding pads; a build up layer coupled between the bonding pads to terminal metal pads by the through silicon via (TSV); a substrate with a second die embedded inside and top circuit wiring and bottom circuit wiring on top and bottom side of the substrate respectively; and a conductive through hole structure coupled between the terminal metal pads to the top circuit wiring and the bottom circuit wiring.

Abstract: The outer peripheral portion of a substrate is provided with a first peripheral edge and a second peripheral edge. The first peripheral edge is provided on the edge portion of a first upper surface of the substrate on which a light-emitting diode element is mounted. The second peripheral edge is formed either on an extension of an imaginary line connecting an edge of the light-emitting facet of the light-emitting diode element and the first peripheral edge or inwardly of the extension. The second peripheral edge is located at a position where the first peripheral edge blocks direct light from the light-emitting diode element. This configuration prevents the second upper surface of the substrate provided between the first peripheral edge and the second peripheral edge from becoming deteriorated due to the direct light.

Abstract: A device mounting board includes an insulating layer formed of an insulating resin, a glass cloth covering the surface of the insulating layer, and an electrode provided in a through hole extending through the glass cloth. The angle of contact with solder of the glass cloth is larger than that of the resin. Thus, solder bumps are formed on the electrode 14 of the device mounting board 10 with high precision.

Abstract: A chip structure and a stacked structure composed of the chip structures are provided. The chip structure has a substrate and at least one compliant contact. Furthermore, the chip structure may further have a redistribution layer for redistributing pads originally disposed around the substrate in a specific arrangement. The substrate has a first surface and a second surface. The compliant contact is embedded into the substrate and protrudes outside the first surface and the second surface of the substrate. The compliant contact has a compliant bump and a conductive layer encapsulating the compliant bump. The conductive layer can be connected with the redistribution layer. Two chip structures can be connected with each other through their compliant contacts or through their compliant contacts or redistribution layers.

Abstract: A resistance memory element is provided which has a relatively high switching voltage and whose resistance can be changed at a relatively high rate. The resistance memory element includes an elementary body and a pair of electrodes opposing each other with at least part of the elementary body therebetween. The elementary body is made of a semiconductor ceramic expressed by a formula: {(Sr1-xMx)1-yAy}(Ti1-zBz)O3 (wherein M represents at least one of Ba and Ca, A represents at least one element selected from the group consisting of Y and rare earth elements, and B represents at least one of Nb and Ta), and satisfies 0<x?0.5 and 0.001?y+z?0.02 (where 0?y?0.02 and 0?z?0.02); 0.5<x?0.8 and 0.003?y+z?0.02 (where 0?y?0.02 and 0?z?0.02); or 0.8<x?1.0 and 0.005?y+z?0.01 (where 0?y?0.02 and 0?z?0.02).

Abstract: Device comprising an ohmic via contact, and method of fabricating thereof. A preferred embodiment comprises forming a metal layer over a substrate, forming a conductive barrier layer over the metal layer, depositing an insulating layer over the conductive barrier layer, creating an opening in the insulating layer to expose the conductive barrier layer, and forming a via contact in the opening. The conductive barrier layer protects the metal layer by preventing the formation of an oxide layer, which could reduce conductivity.

Abstract: A layered chip package includes a main body, and wiring disposed on a side surface of the main body. The main body includes: a main part including a plurality of layer portions stacked; a plurality of first terminals disposed on the top surface of the main part and connected to the wiring; and a plurality of second terminals disposed on the bottom surface of the main part and connected to the wiring. The plurality of layer portions include a first-type layer portion and a second-type layer portion. The first-type layer portion includes a conforming semiconductor chip, and a plurality of first-type electrodes that are connected to the semiconductor chip and the wiring. The second-type layer portion includes a defective semiconductor chip, and a plurality of second-type electrodes that are connected to the wiring and not to the semiconductor chip.

Abstract: Connection structure (5) for attaching a semiconductor chip (2) to a metal substrate (4) is provided which has a plurality of electrically conducting layers (11, 12, 13, 14) arranged in a stack. The stack has a contact layer (11) for providing an ohmic contact to a semiconductor chip (2), at least one mechanical decoupling layer (12) for mechanically decoupling the semiconductor chip (2) and the metal substrate (4), at least one diffusion barrier layer (13) and a diffusion solder layer (14) for providing a diffusion soldered mechanical bond and an electrical connection to a metal substrate (4). The mechanical decoupling layer (12) is positioned in the stack between the diffusion barrier layer (13) and the contact layer (11).

Abstract: A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include a plurality of electrode terminals which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.

Abstract: The invention provides a contact pad supporting structure. The contact pad supporting structure includes an underlying first conductive plate and an overlying second conductive plate, wherein the first and second conductive plates are separated by a first dielectric layer. A plurality of circular ring-shaped via plug groups comprising a plurality of circular ring-shaped via plugs is through the first dielectric layer, electrically connecting to the first and second conductive plates. All of the circular ring-shaped via plugs of each of the circular ring-shaped via plug groups are disorderly arranged.

Abstract: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.

Abstract: In a fingerprint apparatus, fingerprint sensing members disposed on a silicon substrate detect skin textures of a finger placed thereon to generate electric signals. A set of integrated circuits formed on the substrate processes the electric signals. First bonding pads are disposed on the substrate and electrically connected to the set of integrated circuits. A first insulating layer is disposed below the first bonding pads. Metal plugs penetrating through the substrate are respectively electrically connected to the first bonding pads. A second insulating layer is formed on the substrate and between the metal plugs and the substrate. Second bonding pads are formed on a rear side of the second insulating layer, and are respectively electrically connected to the first bonding pads through the metal plugs. The protection layer is disposed on the substrate and covers the sensing members to form a flat touch surface to be touched by the finger.

Abstract: An object of the invention is to provide an oscillator with a pedestal that facilitates soldering operations and offers a high level of productivity. A surface mount crystal oscillator with a pedestal comprises a crystal oscillator with lead wires led out from a bottom surface of a metallic base thereof; and a pedestal having a substantially rectangular outer shape in plan view, has insertion holes through which the lead wires pass, and is attached to a bottom surface of the crystal oscillator, and has mount terminals to be electrically connected to the lead wires formed on a bottom surface thereof. The configuration is such that the insertion holes are provided in four corner sections of the pedestal, in the four corner sections of the bottom surface of the pedestal where the insertion holes are formed there is provided a recess with an open outer periphery, and the lead wire is connected to a terminal electrode formed inside the recess, using solder.

Abstract: A semiconductor package has a first substrate having a plurality of electrically conductive patterns formed thereon. A first semiconductor die is coupled to the plurality of conductive patterns. A second semiconductor die is coupled to the first semiconductor die by a die attach material. A third semiconductor die is coupled to the second semiconductor die by a die attach material. A second substrate having a plurality of electrically conductive patterns formed thereon is coupled to the third semiconductor die. A plurality of contacts is coupled to a bottom surface of the first substrate. A connector jack is coupled to the second substrate. A plurality of leads is coupled to the second semiconductor die by conductive wires.

Abstract: In the present invention, a first circuit pattern 3 composing a semiconductor element is formed on the front side of a substrate 1, a first insulating layer 2 is formed on the first circuit pattern 3, solder electrodes 5 for external connection are formed on the first insulating layer 2, a second insulating layer 6 is formed on the backside of the substrate 1, a second circuit pattern 7 is formed on the second insulating layer 6, through vias 8 are formed to connect the first circuit pattern 3 and the second circuit pattern 7, chip passive components 9 are placed on the second circuit pattern 7, and the backside of the substrate is integrally molded with epoxy resin 10 such that the epoxy resin 10 covers the chip passive components 9.

Abstract: The semiconductor package includes a dielectric layer, a trace layer, a conductive layer, a die and an underfill layer. The dielectric layer has first side and an opposing dielectric layer second side. Multiple vias extend through the dielectric layer from the dielectric layer first side to the dielectric layer second side. Multiple solder balls are disposed at the dielectric layer second side. Each of the solder balls is electrically coupled to a different one of the vias. The die is electrically coupled to the solder balls. The conductive layer is disposed between the dielectric layer second side and the die. The conductive layer defines a window there through for allowing the solder balls to electrically couple to the vias without contacting the conductive layer, i.e., no physical or electrical contact. The underfill layer is formed between the die and the conductive layer, while the trace layer is formed at the dielectric layer first side.

Abstract: A package structure in which a coreless substrate has direct electrical connections to a semiconductor chip and a manufacturing method thereof are disclosed. The method includes the following steps: providing a metal carrier board having a cavity; placing a chip having a plurality of electrode pads on an active surface in the cavity of a board; filling the cavity with an adhesive for fixing the chip; forming a solder mask on the active surface of the chip and the surface of the metal carrier board at the same side, wherein the solder mask has a plurality of openings to expose the electrode pads of the chip; forming a built-up structure on the solder mask and the exposed active surface of the chip in the openings; and removing the metal carrier board. In this method the metal carrier board can support the built-up structure to thereby avoid warpage.

Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device comprises a semiconductor die including a bond pad, a redistribution layer, and a solder ball. The redistribution layer is formed by sequentially plating copper and nickel, sequentially plating nickel and copper, or sequentially plating copper, nickel, and copper. The redistribution layer includes a nickel layer in order to prevent a crack from occurring in a copper layer. Further, a projection is formed in an area of the redistribution layer or a dielectric layer to which the solder ball is welded and corresponds, so that an area of the redistribution layer to which the solder ball is welded increases, thereby increasing bonding power between the solder ball and the redistribution layer.

Abstract: A solid state light emitting device includes a laminated substrate structure (120), an LED chip (30), a transparent capsulation material (50) and an electric component (40). The laminated substrate structure includes a first substrate (10) and a second substrate (20) attached to each other by a sintering process. The first substrate has a mounting surface (100) and a receiving through hole (11) defined in the mounting surface thereof. The LED chip is mounted on the mounting surface of the first substrate. The transparent capsulation material envelops the LED chip therein. The electric component is received in the receiving hole and mounted on the second substrate. The electric component is located below the mounting surface of the first substrate.