Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a single-layer support structure having a structure non-horizontal surface; forming a single-layer contact coplanar with the single-layer support structure, the single-layer contact having a contact non-horizontal surface; forming a single-layer insulation coplanar with the single-layer contact and horizontally between the structure non-horizontal surface and the contact non-horizontal surface; forming an upper support pad over the single-layer insulation and directly on the single-layer support structure; and mounting an integrated circuit over the upper support pad.

Abstract: Embodiments discussed herein are directed to a power semiconductor packaging that removes heat from a semiconductor package through one or more cooling zones that are located in a laterally oriented position with respect to the semiconductor package. Additional embodiments are directed to circuit elements that are constructed from one or more modular power semiconductor packages.

Abstract: A method of fabricating a microelectronic package having a direct contact heat spreader, a package formed according to the method, a die-heat spreader combination formed according to the method, and a system incorporating the package. The method comprises metallizing a backside of a microelectronic die to form a heat spreader body directly contacting and fixed to the backside of the die thus yielding a die-heat spreader combination. The package includes the die-heat spreader combination and a substrate bonded to the die.

Abstract: Microelectronic die packages, stacked systems of die packages, and methods of manufacturing them are disclosed herein. In one embodiment, a system of stacked packages includes a first die package having a bottom side, a first dielectric casing, and first metal leads; a second die package having a top side attached to the bottom side of the first package, a dielectric casing with a lateral side, and second metal leads aligned with and projecting towards the first metal leads and including an exterior surface and an interior surface region that generally faces the lateral side; and metal solder connectors coupling individual first leads to individual second leads. In a further embodiment, the individual second leads have an “L” shape and physically contact corresponding individual first leads. In another embodiment, the individual second leads have a “C” shape and include a tiered portion that projects towards the lateral side of the second casing.

Abstract: A tiered integrated circuit (IC) assembly includes stacks of a limited number of ICs coupled to each other and arranged in a first direction across a base tier and a second tier. The base tier includes ICs and a data bridge. Each of the ICs includes a respective array of through silicon vias (TSVs) arranged in parallel with the first direction. The data bridge includes submicron metal interconnects (densely spaced electrical conductors) arranged in a plane that is substantially orthogonal to the first direction. The second tier is adjacent to the base tier and includes respective high-performance ICs different from the ICs of the base tier. The TSVs provide power and ground paths to the ICs in the second tier. In an example embodiment, the ICs in the second tier support one or more data bridges for connecting adjacent stacks.

Abstract: The semiconductor device includes a plurality of semiconductor packages stacked on one another. Each semiconductor package includes a main current electrode terminal disposed in a case section of the semiconductor package, the main current electrode terminal being exposed outside the case section to be electrically connected to an external power supply. The main current electrode terminal extends in the stack direction of the semiconductor packages, and embedded in the case section at a surface portion thereof facing an external surface of the case section. Both end surface portions of the main current electrode terminal in the stack direction respectively reach end surface portions of the case section in the stack direction so that the main current electrode terminals of each adjacent two of the semiconductor packages are in contact with each other when the semiconductor packages are stacked on one another in the stack direction.

Abstract: An article of manufacture includes a semiconductor die (110) having an integrated circuit (105) on a first side of the die (110), a diffusion barrier (125) on a second side of the die (110) opposite the first side, a mat of carbon nanotubes (112) rooted to the diffusion barrier (125), a die attach adhesive (115) forming an integral mass with the mat (112) of the carbon nanotubes, and a die pad (120) adhering to the die attach adhesive and (115) and the mat (112) of carbon nanotubes for at least some thermal transfer between the die (110) and the die pad (120) via the carbon nanotubes (112). Other articles, integrated circuit devices, structures, and processes of manufacture, and assembly processes are also disclosed.

Abstract: A semiconductor module structure and a method of forming the semiconductor module structure are disclosed. The structure incorporates a die mounted on a substrate and covered by a lid. A thermal compound is disposed within a thermal gap between the die and the lid. A barrier around the periphery of the die extends between the lid and the substrate, contains the thermal compound, and flexes in response to expansion and contraction of both the substrate and the lid during cycling of the semiconductor module. More particularly, either the barrier is formed of a flexible material or has a flexible connection to the substrate and/or to the lid. The barrier effectively contains the thermal compound between the die and the lid and, thereby, provides acceptable and controlled coverage of the thermal compound over the die for heat removal.

Abstract: A semiconductor chip assembly includes a semiconductor device, a heat spreader, a conductive trace, a substrate and an adhesive. The heat spreader includes a post and a base. The conductive trace includes a pad, a terminal, a conductive pattern and first and second vias. The substrate includes the conductive pattern and a dielectric layer. The semiconductor device is electrically connected to the conductive trace and thermally connected to the heat spreader. The post extends upwardly from the base into an opening in the adhesive and an aperture in the substrate, and the base extends laterally from the post. The conductive trace provides signal routing between the pad and the terminal using the conductive pattern and the vias.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead; forming an interior conductive layer having an interior top side and an interior bottom side, the interior bottom side directly on the lead; mounting an integrated circuit over the lead, the integrated circuit having an inactive side and an active side; forming an encapsulation directly on the inactive side and the interior top side; and forming an insulation layer directly on the active side and a portion of the interior bottom side.

Abstract: An electronic assembly includes a workpiece, a through substrate via (TSV) die including a substrate and a plurality of TSVs, a topside and a bottomside having TSV connectors thereon. The TSV die is attached to the workpiece with its topside on the workpiece. A heat spreader having an inner open window is on the bottomside of the TSV die. Bonding features are coupled to the TSV connectors or include the TSV connectors themselves. The bonding features protrude from the inner open window to a height above a height of the top of the heat spreader that allows a top die to be bonded thereto.

Abstract: A semiconductor module system includes a first semiconductor module and a second semiconductor module. The first semiconductor module has a first housing and a first base plate. The second semiconductor module has a second housing and a second base plate. The first base plate includes a first fitting segment fitted with a semiconductor component, and a first adjustment segment separated from the first fitting segment. The first adjustment segment also has a first adjustment device. The second base plate has a second adjustment device. The first semiconductor module and the second semiconductor module are configured to be positioned relative to one another using the first adjustment device and the second adjustment device so as to form at least one undercut connection. The first fitting segment and the first adjustment segment are connected to the first housing in a captive manner even when the undercut connection is not formed.

Abstract: An inner-layer heat-dissipating board and a multi-chip stack package structure having the inner-layer heat-dissipating board are disclosed. The inner-layer heat-dissipating board includes a metal board body formed with a plurality of penetrating conductive through holes each comprising a plurality of nano wires and an oxidative block having nano apertures filled with the nano wires. The multi-chip stack package structure includes a first chip and an electronic component respectively disposed on the inner-layer heat-dissipating board to thereby facilitate heat dissipation in the multi-chip stack structure as well as increase the overall package rigidity.

Abstract: Disclosed is a composition, in particular a dispersion, which contains nanofiber material in at least one organic matrix component, said nanofiber material being pre-treated in at least one method step for adjusting the physical properties of the composition.

Abstract: After a semiconductor chip is cut out, an In-10 atom % Ag pellet is placed on a metal film. Next, an epoxy sheet on a stiffener is stuck to a ceramic substrate. At this time, the In alloy pellet is sandwiched between a central protrusion portion and the metal film. Then, an In alloy film is formed from the In alloy pellet by heating, melting, and then cooling the In alloy pellet. As a result, the semiconductor chip and a heat spreader are bonded via the metal film and the In alloy film.

Abstract: An exemplary LED module includes a ceramic substrate, a heat spreader, a heat sink, an LED die, and a packaging layer. The substrate defines a hole extending therethrough from a top side to a bottom side thereof. The heat spreader is disposed in the hole with a top side thereof substantially coplanar with the top side of the substrate. An outer circumferential surface of the heat spreader contacts an inner circumferential surface of the substrate around the hole. The heat sink is attached to the top sides of the substrate and the heat spreader. The LED die is attached to a bottom side of the heat spreader, and the packaging layer encapsulates the LED die.

Abstract: The package substrates with through silicon plugs (or vias) described above provide lateral and vertical heat dissipation pathways for semiconductor chips that require thermal management. Designs of through silicon plugs (TSPs) with high duty ratios can most effectively provide heat dissipation. TSP designs with patterns of double-sided combs can provide high duty ratios, such as equal to or greater than 50%. Package substrates with high duty ratios are useful for semiconductor chips that generate large amount of heat. An example of such semiconductor chip is a light-emitting diode (LED) chip.

Abstract: By filling an air gap between tiers of a stacked IC device with a thermally conductive material, heat generated at one or more locations within one of the tiers can be laterally displaced. The lateral displacement of the heat can be along the full length of the tier and the thermal material can be electrically insulating. Through silicon-vias (TSVs) can be constructed at certain locations to assist in heat dissipation away from thermally troubled locations.

Abstract: A thermally enhanced expanded wafer level ball grid array package. The expanded wafer level ball grid array package includes an integrated thermally conductive heat dissipater. In one embodiment the heat dissipater is positioned in close proximity to a non-active face of a die and is separated from the non-active face by a thermal interface material. In another embodiment the heat dissipater includes legs that displace the heat dissipater a short distance from the non-active die face, with the intervening space occupied by encapsulation material. In yet another embodiment, the thermal interface material exists between the non-active die face and the heat dissipater, but extends beyond the edge of the semiconductor die to also cover a portion of the encapsulation material. Methods for making the various embodiments of the expanded wafer level ball grid array package are also shown.

Abstract: An electronic device includes an integrated circuit and a heat spreader. The integrated circuit includes a substrate with an active via located therein. The heat spreader includes a thermally conductive core. The active via is connected to a corresponding heat spreader via that passes through the thermally conductive core.

Abstract: An electrical control unit has a printed circuit board substrate, on which an electronic circuit is situated, which circuit includes multiple electrical components which are interconnected via printed conductors of the printed circuit board substrate, as well as housing parts for covering the electrical components on the printed circuit board substrate, and at least one device plug connector part situated on the printed circuit board substrate outside the section of the printed circuit board substrate covered by the housing parts. Outside the section covered by the at least one housing part and outside the section of the printed circuit board substrate provided with the device plug connector part, at least one contact point for an additional electrical component is situated on the printed circuit board substrate.

Abstract: A power module includes a first power chip and a second power chip, each of which has at least two electrodes. The power module is applied to a power converter having a power density higher than 15 W/inch3 and a maximum efficiency higher than 92%, or to a power converter having a power density higher than 20 W/inch3 or having a maximum efficiency higher than 93%. At least one of the power chips operates at a frequency higher than 25 kHz.

Abstract: A microelectronic package includes a substrate, first and second microelectronic elements, and a heat spreader. The substrate has terminals thereon configured for electrical connection with a component external to the package. The first microelectronic element is adjacent the substrate and the second microelectronic element is at least partially overlying the first microelectronic element. The heat spreader is sheet-like, separates the first and second microelectronic elements, and includes an aperture. Connections extend through the aperture and electrically couple the second microelectronic element with the substrate.

Abstract: Thermal management solutions for higher power LEDs. In accordance with embodiments, a heat sink, preferably copper, is connected directly to the thermal pad of an LED. Directly connecting the LED thermal pad to the copper heat sink reduces the thermal resistance between the LED package and the heat sink, and more efficiently conducts heat away from the LED through the copper heat sink. In embodiments, the copper heat sink is directly soldered to the LED thermal pad.

Abstract: A semiconductor device includes a semiconductor element having a rectangular two-dimensional geometry and serving as a heat source, a first heat sink section including the semiconductor element mounted thereon, and a second heat sink section joined to an opposite side of the first heat sink section that includes the semiconductor element. A relation among directional components of thermal conductivity is K1yy?K1xx>K1zz, where directional components of a three-dimensional thermal conductivity of the heat sink section in X, Y, and Z directions are determined as Kxx, Kyy, and Kzz. A relation among directional components of a thermal conductivity of the second heat sink section is K2zz?K2yy>K2xx or K2yy?K2zz>K2xx, where the directional components of the thermal conductivity of the second heat sink section in X, Y, and X directions are determined as K2xx, K2yy, and K2zz.

Abstract: Provided is a small and low-cost resin-sealed electronic control device including a first electronic board and a second electronic board respectively bonded onto an upper surface and a lower surface of a support plate, each of the first electronic board and the second electronic board having an increased mounting area on which circuit components are mounted. A first electronic board (30A) and a second electronic board (40A) respectively bonded onto an upper surface and a lower surface of a support plate (20A) include outer circuit components (31, 41) and inner circuit components (33, 43) respectively mounted on outer surfaces and inner surfaces thereof. The inner circuit components (33, 43) are fitted into a window hole portion (21) of the support plate (20A) and are sealed with a filler (25).

Abstract: An electronic device includes an electronic component mounted on a substrate; a cooling system for cooling the electronic component; and a fastening structure for fastening the cooling system to the substrate. The fastening structure includes a first magnet provided to one of the substrate and the cooling system, a second magnetic material fixed to the other of the substrate and the cooling system and magnetically coupled with the first magnet, and a magnetic shield that covers a part or all of the first magnet except for a coupling face to be coupled with the second magnetic material.

Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a substrate; forming a mold gate on an upper surface of the substrate; mounting an integrated circuit to the substrate; and forming an encapsulant encapsulating the integrated circuit, the encapsulant having disruption patterns emanating from the mold gate and underneath a bottom plane of the integrated circuit.

Abstract: A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit over a package carrier; mounting a conductive connector over the package carrier; forming an encapsulation over the integrated circuit, the encapsulation having a recess exposing the conductive connector; and mounting a heat slug over the encapsulation, the heat slug having an opening with an opening width greater than a recess width of the recess, the opening exposing a portion of a top surface of the encapsulation.

Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a lead; forming an interior conductive layer having an interior top side and an interior bottom side, the interior bottom side directly on the lead; mounting an integrated circuit over the lead, the integrated circuit having an inactive side and an active side; forming an encapsulation directly on the inactive side and the interior top side; and forming an insulation layer directly on the active side and a portion of the interior bottom side.

Abstract: A semiconductor module includes a power semiconductor chip and a passive discrete component. The semiconductor chip includes on its top side and/or on the back side a large-area contact, which in its two-dimensional extent takes up the top side and/or the back side of the semiconductor chip virtually completely. The passive component, arranged in a package, is stacked on one of the large-area contacts. The electrode of the passive component is electrically connected with one of the large-area contacts. The counter electrode of the passive component is operatively connected with a control or signal electrode of the power semiconductor chip or an electrode of a further semiconductor chip.

Abstract: The present disclosure provides systems and methods for forming a semiconductor device. The semiconductor device includes a substrate having a first side and a second side opposite the first side. A first heat producing element is formed on the first side of the substrate. A second heat producing element is formed on the first side of substrate co-planar with, but not touching the first heat producing element. A heat spreader is coupled to the second side of the substrate using a thermal interface material. The heat spreader includes a first and second vapor chambers. The first vapor chamber is embedded in the heat spreader substantially opposite the first heat producing element. The second vapor chamber is embedded in the heat spreader substantially opposite the second heat producing element. As an example, the first heat producing element may be a light-emitting diode (LED) and the second heat producing element may be a driver circuit for the LED.

Abstract: Disclosed herein is a semiconductor package. According to a preferred embodiment of the present invention, there is provided a semiconductor package, including: a first substrate having a first wiring pattern formed therein; a first semiconductor device mounted above the first substrate by being contacted with the first substrate; a second substrate having a second wiring pattern formed therein; a third semiconductor device mounted above the first semiconductor device and contacted with a lower portion of the second substrate; and a third substrate positioned between the first semiconductor device and the third semiconductor device and having a third wiring pattern including at least one upper electrode and lower electrode protruding outwardly, the lower electrode being contacted with the first semiconductor device and the upper electrode being contacted with the third semiconductor device.

Abstract: A semiconductor device includes a semiconductor element placed over a substrate, a heat conducting material placed over the semiconductor element, and a radiator placed over the heat conducting material. The radiator has a plurality of projections which are arranged outside a region opposite to the semiconductor element and which protrude toward the substrate. Even if the heat conducting material flows out from over the semiconductor element at fabrication time, the heat conducting material which flows out is made by the plurality of projections to adhere to and spread along the radiator. As a result, the outflow or scattering of the heat conducting material toward the substrate or an electric trouble caused by it is prevented.

Abstract: The object of the present invention is to efficiently dissipate heat from the upper and lower main surfaces of a semiconductor device carrying a semiconductor element. A semiconductor device (1) is provided with an insulating substrate (10A), an insulating substrate (10B) provided so as to face the insulating substrate (10A), and a semiconductor element (20) disposed between the insulating substrate (10A) and the insulating substrate (10B) and having a collector electrode and an emitter electrode provided on the side opposite to that of the collector electrode. The collector electrode is electrically connected to a metal foil (10ac) provided on the insulating substrate (10A), and the emitter electrode is electrically connected to the metal foil (10bc) provided on the insulating substrate (10B). As a result, heat generated by the semiconductor element (20) is efficiently dissipated from the upper and lower main surfaces of the semiconductor device (1).

Abstract: A semiconductor device includes a multilayer wiring substrate and a double-sided multi-electrode chip. The double-sided multi-electrode chip includes a semiconductor chip and has multiple electrodes on both sides of the semiconductor chip. The double-sided multi-electrode chip is embedded in the multilayer wiring substrate in such a manner that the double-sided multi-electrode chip is not exposed outside the multilayer wiring substrate. The electrodes of the double-sided multi-electrode chip are connected to wiring layers of the multilayer wiring substrate.

Abstract: A light emitting die package and a method of manufacturing the die package are disclosed. The die package includes a leadframe, at least one light emitting device (LED), a molded body, and a lens. The leadframe includes a plurality of leads and has a top side and a bottom side. A portion of the leadframe defines a mounting pad. The LED device is mounted on the mounting pad. The molded body is integrated with portions of the leadframe and defines an opening on the top side of the leadframe, the opening surrounding the mounting pad. The molded body further includes latches on the bottom side of the leadframe. The lens is coupled to the molded body. A composite lens is used as both reflector and imaging tool to collect and direct light emitted by LED(s) for desired spectral and luminous performance.

Abstract: A semiconductor device includes a substrate, a first die attached to the substrate, and a lid coupled to the substrate. The lid defines a cavity for engaging the first die, and the lid has a die enclosure barrier having ends extending downwardly into the cavity. The ends of the die enclosure barrier are attached to the substrate and a thermal interface material is disposed between the first die and the lid, thermally connecting the first die to the lid.

Abstract: A thermally enhanced packaging structure includes a chip carrier; a high power chip disposed on the chip carrier; a molding compound covering the high power chip; a heat dissipating layer disposed on the molding compound, wherein the heat dissipating layer comprises a plurality of carbon nanocapsules (CNCs); and a non-fin type heat dissipating device, disposed either on the heat dissipating layer or between the molding compound and the heat dissipating layer. The molding compound can also comprise a plurality of CNCs.

Abstract: A heat spreader package includes a substrate having a first surface, first traces on the first surface of the substrate, and an electronic component having an inactive surface mounted to the first surface of the substrate. The electronic component further includes an active surface having bond pads. Bond wires electrically connect the bond pads to the first traces. An inverted pyramid heat spreader includes a first heatsink, a first heatsink adhesive directly connecting the first heatsink to the active surface of the electronic component inward of the bond pads, a second heatsink having an absence of active circuitry, and a second heatsink adhesive directly connecting a first surface of the second heatsink to the first heatsink. The second heatsink adhesive is a dielectric directly between the bond wires and the second heatsink that prevents inadvertent shorting between the bond wires and the second heatsink.

Abstract: To improve manufacture of an electronic circuit, the electronic circuit is composed of modules of sub-circuits arranged on a common substrate, such as a cooling body, and that are electrically interconnected by a planar electrical contact element.

Abstract: A semiconductor device has a semiconductor die mounted to a substrate. A recess is formed in a back surface of the semiconductor die to an edge of the semiconductor die with sidewalls on at least two sides of the semiconductor die. The sidewalls are formed by removing a portion of the back surface of the die, or by forming a barrier layer on at least two sides of the die. A channel can be formed in the back surface of the semiconductor die to contain the TIM. A TIM is formed in the recess. A heat spreader is mounted in the recess over the TIM with a down leg portion of the heat spreader thermally connected to the substrate. The sidewalls contain the TIM to maintain uniform coverage of the TIM between the heat spreader and back surface of the semiconductor die.

Abstract: A semiconductor device is made by mounting an insulating layer over a temporary substrate. A via is formed through the insulating layer. The via is filled with conductive material. A semiconductor die has a stress sensitive region. A dam is formed around the stress sensitive region. The semiconductor die is mounted to the conductive via. The dam creates a gap adjacent to the stress sensitive region. An encapsulant is deposited over the semiconductor die. The dam blocks the encapsulant from entering the gap. The temporary substrate is removed. A first interconnect structure is formed over the semiconductor die. The gap isolates the stress sensitive region from the first interconnect structure. A shielding layer or heat sink can be formed over the semiconductor die. A second interconnect structure can be formed over the semiconductor die opposite the first interconnect structure.

Abstract: A structure for attaching a heat sink to an integrated circuit chip includes a servo control system and at least one voice coil motor for actuating the heat sink.

Abstract: A process for forming a heat sink on a semiconductor package at the wafer level stage of manufacture is disclosed. A semiconductor component wafer, prior to separation into separate component packages, is covered on one side with a resin metal foil layer. The resin foil layer is patterned by laser ablation to define the heat sink locations, and then a thermal paste is applied over the patterned layer. The thermal conductive past is hardened to form the heat sinks. The wafer can then be separated into packages.

Abstract: A semiconductor package system is provided including: a semiconductor chip; a substrate having a substrate opening and a vertical build-up wing, the substrate having the semiconductor chip mounted thereon with the vertical build-up wing circumscribed by vertical planes of a perimeter of, and spaced apart from, the semiconductor chip; a first heat slug attached above the substrate at a first horizontal plane and to a first surface of the semiconductor chip, the semiconductor chip at least partially encapsulated by the first heat slug; and a second heat slug attached to the substrate at a second horizontal plane above the first horizontal plane and to a second surface of the semiconductor chip through the substrate opening.

Abstract: A module includes a substrate including a first copper surface and a semiconductor chip. The module includes a first sintered joint bonding the semiconductor chip directly to the first copper surface.

Abstract: An integrated circuit (IC) package having a packaging substrate, an IC disposed onto the packaging substrate, and a rigid support member attached to the substrate layer through an adhesive spacer is provided. The packaging substrate includes multiple decoupling capacitors positioned thereon around the IC. A heat sink is placed over the IC. The rigid support member provides enhanced structural support for the IC packaging and there is ample space between a bottom surface of the rigid support member and the packaging substrate to allow the placement of the decoupling capacitors underneath the rigid support member.

Abstract: In one embodiment, the present invention includes a socket for a semiconductor package, where the socket has a frame with a segmented design, where socket streets are located between the segments. One or more of the streets may include a conduit to enable thermal transfer during operation of the semiconductor package. Other embodiments are described and claimed.

Abstract: To reduce the thermal stresses that may be caused by a difference in thermal expansion coefficients between a molded casing and an active side of a semiconductor device embedded in the molded casing, and thus reduce the number of corresponding failures caused by the thermal stresses, the active side of the semiconductor device is arranged face-down, towards a substrate supporting the semiconductor device. The semiconductor device includes a through via that electrically connects the active side of the semiconductor device to a passive side of the semiconductor device. A wire bond electrically connects the passive side of the semiconductor device to the substrate. To increase the dissipation of heat generated in the semiconductor device, a thermally conductive slug may be disposed in the substrate, and the active side of the semiconductor device may be attached to the thermally conductive slug.