Abstract: Implementations of a semiconductor package may include a first substrate including a first group of leads physically coupled thereto and a second group of leads physically coupled thereto; a second substrate coupled over the first substrate and physically coupled to the first group of leads and the second group of leads; and one or more semiconductor die coupled between the first substrate and the second substrate. The second group of leads may be electrically isolated from the first substrate.

Abstract: A package structure includes a lower substrate, substrate connection terminals on the lower substrate, a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate, first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, as viewed in a plan view, and covering at least one of the substrate connection terminals, and a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in a plan view.

Abstract: A ceramic heater includes a ceramic plate, a planar electrode, and a resistive heating element. A first via, a second via, a coupler, and a reinforcement portion are embedded in the ceramic plate. The first via is conductive and extends from the resistive heating element toward a via through-hole. The second via is conductive and extends from the via through-hole in a direction opposite a direction toward the resistive heating element. The coupler is conductive and electrically couples the first via and the second via with each other. The reinforcement portion is disposed inside the via through-hole 16 between the coupler and an inner circumferential surface around the via through-hole and is composed of a material that is the same as the material of the ceramic plate.

Abstract: Provided is a semiconductor package structure including a redistribution layer (RDL) structure, a chip, an electronic device and a stress compensation layer. The RDL structure has a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the RDL structure. The electronic device is disposed in the RDL structure, electrically connected to the chip, and includes a dielectric layer disposed therein. The stress compensation layer is disposed in or outside the RDL structure. The dielectric layer provides a first stress between 50 Mpa and 200 Mpa in a first direction perpendicular to the second surface, the stress compensation layer provides a second stress between 50 Mpa and 200 Mpa in a second direction opposite to the first direction, and the difference between the first stress and the second stress does not exceed 60 Mpa.

Abstract: A via for semiconductor devices is disclosed. Implementations of vias for semiconductor devices may include: a semiconductor substrate that includes a first side; a via extending from the first side of the semiconductor substrate to a pad; a polymer layer coupled along an entire sidewall of the via, the polymer layer in direct contact with the pad; and a metal layer directly coupled over the polymer layer and directly coupled with the pad.

Abstract: An electronic circuit device according to the present invention includes a base substrate including a wiring layer having a connection part, at least one electronic circuit element, and a re-distribution layer including a photosensitive resin layer, the photosensitive resin layer enclosing a surface on which a connection part of the electronic circuit element is formed and a side surface of the electronic circuit element and embedding a first wiring photo via, a second wiring photo via and a wiring, the first wiring photo via directly connected to the connection part of the electronic circuit element, the second wiring photo via arranged at the outer periphery of the electronic circuit element and directly connected to a connection part of the wiring layer, the wiring electrically connected to the first wiring photo via and the second wiring photo via on a same surface.

Abstract: Provided is a semiconductor chip, including: a semiconductor substrate; a thin film formed on the semiconductor substrate, the thin film having internal stress; and a semiconductor device formed on the semiconductor substrate that has the thin film formed thereon, wherein the semiconductor chip warps due to the internal stress of the thin film.

Abstract: In an embodiment, a semiconductor package includes a semiconductor device embedded in an insulating layer, a contact pad having an area, and a vertical redistribution structure including substantially parallel vertical paths arranged in the insulating layer and extending perpendicular to the area of the contact pad. The substantially vertical paths are non-uniformly distributed over the area of the contact pad.

Abstract: A packaging glass substrate for semiconductor includes a glass substrate with a first surface and a second surface facing each other, and a plurality of core vias penetrating through the glass substrate in a thickness direction, wherein a plain line is a line linking places where the core vias are not formed, a via line is a line linking places where the core vias are formed, a stress difference value (P) is a value according to Equation (1), and the stress difference value (P) is 1.5 MPa or less, Equation (1): P=Vp?Np where P is a stress difference value measured at the same glass substrate, Vp is a difference between the maximum value and the minimum value of stress measured at the via line, and Np is a difference between the maximum value and the minimum value of stress measured at the plain line.

Abstract: In the oscillator, a quartz crystal resonator and an oscillation circuit formed in an IC incorporating an inductor are electrically coupled to each other with a resonator interconnection disposed on a surface of a substrate to form an oscillation loop. A conductor layer disposed as an intermediate layer of the substrate is disposed so as to overlap the resonator interconnection and not to overlap the inductor incorporated in the IC in a plan view.

Abstract: A method for mounting an electrical component on a substrate is disclosed. According to the method, joining is simplified using a cover, or hood, that includes a contact structure on an inner side of the hood, wherein when the hood is mounted, the contact structure is joined to the underlying structure at different joining levels simultaneously using an additional material. Moreover, a joining pressure, e.g., for diffusion or sintered bonds for electrical contacts, can be applied using such a hood.

Abstract: A sliding element for an engine may include a polymer-based overlay layer and a metallic substrate. The polymer-based overlay layer may include a polymer-based matrix, a metal particulate, and a pigment. The pigment may have a hardness of at least 4 on the Mohs hardness scale.

Abstract: Embodiments include a microelectronic device package structure having an inductor at least partially embedded within a substrate. At least one thermal solution structure may be on a surface of the inductor, and may be thermally coupled with the inductor. The one or more thermal solution structures provide a thermal pathway for cooling for the inductor, and extend a thermal time constant of the inductor.

Abstract: A sensor unit includes a circuit board including, on a first surface, a plurality of electrode pads to which a plurality of mounting terminals of an inertial sensor are respectively attached via connecting members. The first surface of the circuit board includes an insulating layer provided on the outer side of the plurality of electrode pads in a plan view, includes, in a portion overlapping a center region further on the inner side than the mounting terminals of the inertial sensor in the plan view, a first region where the insulating layer is not provided, and includes, from the first region to the outer side of the inertial sensor in the plan view, a second region where the insulating layer is not provided.

Abstract: A high-frequency module (1) includes a component (3a) mounted on an upper surface (2a) of a substrate (2), a second sealing resin layer (4) stacked on the upper surface (2a) of the substrate (2), a component (3b) mounted on a lower surface (2b) of the substrate (2), a first sealing resin layer (5) stacked on the lower surface (2b) of the substrate (2), and a first terminal assembly (6) and a second terminal assembly (7) that are mounted on the lower surface (2b) of the substrate (2). The first terminal assembly (6) is mounted on a four-corner portion of the substrate (2) and includes a connection conductor (6a) thicker than a connection conductor (7a) of the second terminal assembly (7).

Abstract: A light-emitting module 1 includes a light-emitting element, a mounting board, a module board, an anode connection member, a cathode connection member, and a metal ribbon. The light-emitting element includes an anode electrode and a cathode electrode. The mounting board includes an anode pad, a cathode pad and a heat radiating pads, each of which is electrically independent. The anode electrode and the anode pad are connected. The cathode electrode and the cathode pad are connected. The module board includes an anode terminal, a cathode terminal and a heat sink. The anode connection member connects the anode pad and the anode terminal. The cathode connection member connects the cathode pad and the cathode terminal. The metal ribbon connects the heat radiating pads and the heat sink.

Abstract: A semiconductor package includes a package main body. The package main body includes: a lead frame that includes first terminals and a die pad; two or more integrated circuit chips that are disposed on the die pad; one or more electrically conductive members that are disposed on the die pad; wires that connect the first terminals and the integrated circuit chips electrically; and a molded member that seals the lead frame, the integrated circuit chips, the electrically conductive member, and the wires. An upper surface, a bottom surface, and side surfaces of the package main body are formed by the molded member. The electrically conductive member is exposed through the upper surface of the package main body, and the die pad is exposed through the bottom surface of the package main body.

Abstract: Disclosed are a device and a method for pressure-molding an anti-overheating CSP fluorescent membrane. The device comprises a frame, a mould pressing device, a force measuring device, a control device and a feeding device; and the mould pressing device comprises an upper pressing mould, an upper clamp, a lower pressing mould, a guide post, an elastic supporting structure, and a lower clamp. As the stage of pressing the elastic supporting structure is added to the course of pressure molding, a mould clamping force of the pressure molding increases in a relatively steady way, and a force impact of a mould clamping device is reduced, thereby easily determining an initial point for maintain temperature of the pressure molding.

Abstract: A light-emitting device includes a heat-dissipating structure having a first part and a second part separated from the first part; a light-emitting unit including a light-emitting element with a first pad formed on the first part; and a first transparent enclosing the light-emitting element and having a sidewall; and an adhesive material covering a portion of the sidewall.

Abstract: A semiconductor device includes a substrate, a semiconductor element, a ground pad, an insulating coating member, a conductive bonding member, and a conductive cap. The inner peripheral end of a bottom of the conductive cap is disposed at a side close to the inner periphery of the insulating coating member relative to the outer peripheral end of the insulating coating member. The bottom has a shape in which the distance between the main surface and itself decreases continuously from its outer peripheral end toward its inner peripheral end.

Abstract: Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be incorporated as part of an electronic packaging for the structure, is disclosed. Semiconductor structures and stacked semiconductor structures including an external gettering element are also disclosed. An encapsulation mold compound providing external gettering is also disclosed. Methods of fabricating such devices are also disclosed.

Abstract: A semiconductor device includes PMOS and NMOS FinFET devices disposed on a hybrid substrate including a first substrate and a second substrate, in which a fin of the PMOS FinFET device is formed on the first substrate having a top surface with a (100) crystal orientation, and another fin of the NMOS FinFET device is formed on the second substrate having a top surface with a (110) crystal orientation. The semiconductor device further includes a capping layer enclosing a buried bottom portion of the fin of the PMOS FinFET device, and another capping layer enclosing an effective channel portion of the fin of the PMOS FinFET device.

Abstract: An apparatus configured to function as a pluggable active optical connector that is modular with one or more channels and that converts electrical signals to optical signals and vice versa. On one side, the apparatus has a pluggable electrical interface to a line replaceable unit (LRU); on the other side the apparatus has a pluggable optical interface side to an aircraft fiber optic wiring bundle. The apparatus is pluggable to different types of LRUs including rack-mounted and bolted-down LRUs. The apparatus includes electronic and photonic components sufficient to enable electrical/optical conversion totally within a standard-sized aircraft connector. The apparatus is adaptable to various data communication protocols and has the flexibility to be used in either a single-fiber or a dual-fiber bidirectional data link.

Abstract: An electronic component housing package includes an insulating substrate having a first principal face and a second principal face opposing the first principal face; external connection conductors provided on the second principal face; and connection conductors provided so as to extend from outer peripheral ends of the external connection conductors to outer peripheral ends of the insulating substrate, respectively. The connection conductors are provided so as to be curved convexly toward a first principal face side over a range from the outer peripheral ends of the external connection conductors to the outer peripheral ends of the insulating substrate in a vertical cross-sectional view of the electronic component housing package and so that a distance from each of the connection conductors to the second principal face is gradually increased in a thickness direction of the insulating substrate. Insulating bodies are provided so as to cover the connection conductors, respectively.

Abstract: A light bar, a backlight module and a liquid crystal display are provided. The backlight module includes the light bar and a backplane, the light bar includes a PCB, a plurality of LED chips arranged on a surface of the PCB and a protrusion arranged on the other surface of the PCB, and the backplane includes a baseboard defining a through groove. The protrusion on the PCB is inserted into the through groove of the backplane to facilitate heat conduction. In this way, heat generated by the LED chips could be conducted out quickly.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads of the semiconductor chip; a passivation layer disposed on the second interconnection member; and an under-bump metal layer including an external connection pad formed on the passivation layer and a plurality of vias connecting the external connection pad and the redistribution layer of the second interconnection member to each other, wherein the first interconnection member includes a redistribution layer electrically connected to the connection pads of the semiconductor chi

Abstract: A semiconductor package includes a frame having an insulative body with a first main surface and a second main surface opposite the first main surface, a first plurality of metal traces at the first main surface, and a first cavity in the insulative body. A thermally and/or electrically conductive material filling the first cavity in the insulative body and having a different composition than the first plurality of metal traces. The thermally and/or electrically conductive material provides a thermally and/or electrically conductive path between the first and the second main surfaces of the insulative body. A semiconductor die attached to the frame at the first main surface of the insulative body is electrically connected to the first plurality of metal traces and to the thermally and/or electrically conductive material filling the first cavity in the insulative body. A corresponding method of manufacture is also described.

Abstract: Devices for protecting a plurality of conductors against a power surge. One device includes a first electrode positioned on a first surface of the device, a second electrode positioned on the first surface of the device, and a floating electrode positioned on a second surface of the device. The first electrode is configured to receive a surge current from a first conductor. The surge current travels through the device from the first electrode to the floating electrode and from the floating electrode to the second electrode.

Abstract: A fan-out semiconductor package includes a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposing the active surface, an encapsulant sealing at least a portion of the inactive surface, a first connection member disposed on the active surface and including a redistribution layer and a first via electrically connecting the connection pad to the redistribution layer, a passivation layer disposed on the first connection member, and an under-bump metal layer including an external connection pad disposed on the passivation layer and a second via connecting the external connection pad to the redistribution layer. In a vertical direction, the first and second vias are disposed within the external connection pad and do not overlap each other.

Abstract: There are provided a light emitting device package and a method for manufacturing the same. The light emitting device includes: a plurality of barriers provided above a metal circuit board; a plurality of light emitting devices placed in a space between the barriers; and a lens unit provided at an upper side of the barrier. Accordingly, the plurality of light emitting devices can be conveniently seated as a module format, and a luminance can be increased. Also, an efficiency of heat sink can be increase.

Abstract: Presented herein is a WLCSP intermediate structure and method forming the same, the method comprising forming a first redistribution layer (RDL) on a carrier, the first RDL having mounting pads disposed on the first RDL, and mounting interposer dies on a second side of the first RDL. A second RDL is formed over a second side of the interposer dies, the second RDL having a first side adjacent to the interposer dies, one or more lands disposed on the second RDL, at least one of the one or more lands in electrical contact with at least one of the interposer dies or at least one of the mounting pads. A molding compound is formed around the interposer dies and over a portion of the first RDL prior to the forming the second RDL and the second RDL is formed over at least a portion of the molding compound.

Abstract: A polyimide composition for a package structure is provided. The polyimide composition includes a polyimide precursor, a cross-linker, a photosensitizer, a first additive, a second additive and a solvent. The first additive comprises a polyether based compound, and the second additive comprises a siloxane based compound. The polyimide composition has more than 98% cyclization of the polyimide precursor when the polyimide composition is cured at a temperature range of 160° C. to 200° C.

Abstract: A wafer perforating device includes a chuck stage configured to receive a wafer, a housing spaced apart in a vertical direction on the chuck stage, wherein at least one of the housing and the chuck stage moves in a first horizontal direction, and the housing and the chuck stage intersect each other on the first direction, a displacement sensor fixed within the housing and configured to measure a displacement with a surface of the wafer at a perforating point spaced apart periodically in the first direction of the wafer and a laser module fixed within the housing and configured to irradiate a laser into a perforating depth determined according to the displacement at the perforating point. The displacement sensor determines whether an upper particle and a lower particle are present at the perforating point by considering a step height of the displacement, and ignores the displacement of the perforating point with the presence of an upper particle.

Abstract: A wiring board includes an insulator layer, a wiring layer including a wiring pattern and formed on one surface of the insulator layer, an inorganic layer covering a region of the one surface of the insulator layer not formed with the wiring layer, and covering an upper surface and side surfaces of the wiring pattern along a concavo-convex of the wiring pattern, and a shield part covering the wiring pattern via the inorganic layer.

Abstract: A method for manufacturing an assembly (10) is disclosed. The assembly (10) comprises a substrate (1) having a first surface (3) and a second surface (4). The substrate (1) is at least partially plastically deformable. The assembly (10) comprises a supporting surface (5) arranged to support at least a portion of the second surface (4). The substrate (1) is plastically deformed, thereby producing an elastic preload in at least a portion of the substrate (1). The substrate (1) is fixedly arranged in the assembly (10) such that the second surface (4) is placed against the supporting surface (5), wherein the elastic preload in the at least a portion of the substrate (1) produces a force between the at least a portion of the second surface (4) and the supporting surface (5), whereby the at least a portion of the second surface (4) becomes in abutment with the supporting surface (5) over the at least a portion of the second surface (4). A light source comprising the assembly (10) is also disclosed.

Abstract: Disclosed embodiments include external gettering provided by electronic packaging. An external gettering element for a semiconductor substrate, which may be incorporated as part of an electronic packaging for the structure, is disclosed. Semiconductor structures and stacked semiconductor structures including an external gettering element are also disclosed. An encapsulation mold compound providing external gettering is also disclosed. Methods of fabricating such devices are also disclosed.

Abstract: A manufacturing method for a multi-layer circuit board is provided. The multi-layer circuit structure is disposed on the delivery loading plate through the bottom dielectric layer, the delivery loading plate and the patterned metal interface layer expose the conductive corrosion-barrier layer, and the top-layer circuit of the multi-layer circuit structure is electrically connected to the conductive corrosion-barrier layer through the bottom-layer circuit and the electrical connection layer. Therefore, before the multi-layer circuit board is delivered to the assembly company or before the multi-layer circuit board is packaged with chips, an electrical testing can be applied to the multi-layer circuit board to check if the multi-layer circuit board can be operated normally or not.

Abstract: A printed circuit board (PCB) having a reliable electrical connection with connection terminals and a semiconductor package including the PCB, the printed circuit board including: a substrate base; a plurality of pads disposed on upper and lower surfaces of the substrate base; and a solder resist layer configured to cover at least a portion of the upper and lower surfaces of the substrate base, wherein at least some of the plurality of pads are groove pads comprising at least one annular groove in a side opposite to the substrate base.

Abstract: A flexible integrated circuit that includes a first dielectric layer having a first section at one polarity and a second section at an opposing polarity, wherein the first section and the second section are separated by dielectric material within first dielectric layer; a second dielectric layer having a first side wall that is electrically connected to the first section and a second side wall that is electrically connected to the second section; and a third dielectric layer having a base that is electrically connected to the first side wall and the second side wall, wherein the second dielectric layer is between the first dielectric layer and the third dielectric layer, wherein the base, the first and second side walls and the first and second sections form an antenna that is configured to send or receive wireless signals.

Abstract: A component with a semiconductor body, a first metal layer and a second metal layer is disclosed. The first metal layer is arranged between the semiconductor body and the second metal layer. The semiconductor body has a first semiconductor layer, a second semiconductor layer, and an active layer. The component has a plated-through hole, which extends through the second semiconductor layer and the active layer for the electrical contacting of the first semiconductor layer. The second metal layer has a first subregion, and a second subregion, spaced apart laterally from the first subregion by an intermediate space. The first subregion is electrically connected to the plated-through hole and is assigned to a first electrical polarity of the component. In plan view, the first metal layer laterally completely bridges the intermediate space and is assigned to a second electrical polarity of the component which differs from the first electrical polarity.

Abstract: A module comprising a base (20) supporting a planar capacitor, an antenna, and a microcircuit electrically connected to each other to form a resonant electrical circuit, the capacitor including on a first face of the base a first electrode (30, 301, 302, 303) and a second electrode (300) disposed on a second face opposite to said first face facing said first electrode, the second electrode and the first electrode having substantially the same shape. Each electrode has at least a first portion and a second portion disposed on either side of the turns (40) of said antenna.

Abstract: Discontinuous bonds for semiconductor devices are disclosed herein. A device in accordance with a particular embodiment includes a first substrate and a second substrate, with at least one of the first substrate and the second substrate having a plurality of solid-state transducers. The second substrate can include a plurality of projections and a plurality of intermediate regions and can be bonded to the first substrate with a discontinuous bond. Individual solid-state transducers can be disposed at least partially within corresponding intermediate regions and the discontinuous bond can include bonding material bonding the individual solid-state transducers to blind ends of corresponding intermediate regions. Associated methods and systems of discontinuous bonds for semiconductor devices are disclosed herein.

Abstract: A package substrate with embedded circuit is disclosed. The package substrate comprises a redistribution layer, the redistribution layer comprises a plurality of circuits, each circuit of the plurality of circuits runs with a top surface coplanar with a top surface of the dielectric material.

Abstract: LEDs for an illumination system may be mounted on a PCB. The PCB may be provided with alignment features such as oversized holes for connection to a support surface. Using optical sensing of the position of the mounted LEDs, the space made available by the alignment features may be reduced and aligned to create modified alignment features. The modified alignment features may be created by adding a modifying component and aligned based on the sensed positions of the mounted LEDs. The positioning of the modifying component may offset misalignment of the LEDs with the PCB. An opening in the modified alignment feature may receive a bolt or alignment pin for connection to the support surface. The support surface may be aligned with the secondary optics, resulting in the LEDs being aligned with the secondary optics irrespective of misalignment of the LEDs with respect to the PCB.

Abstract: A multilayer ceramic capacitor may include a ceramic body including a plurality of dielectric layers; a first internal electrode disposed in the ceramic body and exposed to a first side surface in a width direction of the ceramic body and a second internal electrode disposed in the ceramic body and exposed to the first side surface in the width direction of the ceramic body; and first to third external electrodes disposed on the first side surface in the width direction of the ceramic body.

Abstract: Lithium silicate glass ceramics and glasses containing specific oxides of tetravalent elements are described which crystallize at low temperatures and are suitable in particular as dental materials.

Abstract: Provided are a process method for bond-packaging an LED using a refined photoconverter, and a refining equipment system. The process method includes the following continuous process flow: roll-shaping of a special-shaped microporous carrier sheet, refining of a semi-cured photoconversion sheet, preparation of a flip chip LED array sheet, forming of LED package elements by roll-bonding, curing of the LED package elements, and cutting of the LED package elements. The present invention has a significant advantage of a refined photoconverter, and especially can meet a requirement of a continuous process flow of bond-packaging an LED using an organic silicone resin photoconverter, so as to enhance the production efficiency and yield of LED packages in industrialized batch production.

Abstract: A manufacturing method of a semiconductor package includes the following steps. Firstly, a conductive carrier is provided. Then, a first conductive layer is formed on a lower surface of the conductive carrier. Then, a second conductive layer is formed on a lower surface of the first conductive layer, wherein the second conductive layer and the first conductive layer together constitute a conductive structure. Then, an electrical component is disposed on the lower surface of the first conductive layer. Then, a first package body encapsulating the first conductive layer, the second conductive layer and the electrical component but not covering an edge of the lower surface of the conductive carrier is formed. Then, a portion of the first package body is removed. Then, partial material of the conductive carrier is removed, such that a reserved part of the conductive carrier forms a ring-shaped conductive structure.

Abstract: A semiconductor module is provided, including: a cooling-target device; a first cooling unit on which the cooling-target device is placed and that has a flow channel through which a refrigerant for cooling the cooling-target device flows; and a second cooling unit to which the first cooling unit is fixed and that has a flow channel coupled with the flow channel of the first cooling unit. Also, a semiconductor module manufacturing method is provided, including: placing a cooling-target device on a first cooling unit that has a flow channel through which a refrigerant for cooling the cooling-target device flows; and fixing the first cooling unit to a second cooling unit that has a flow channel coupled with the flow channel of the first cooling unit.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.