With Specified Means (e.g., Lip) To Seal Base To Cap Patents (Class 257/710)
  • Patent number: 5541451
    Abstract: A semiconductor device has a semiconductor chip and a ceramic envelope consisting of a base portion and a sealing portion sealing the chip, and has good high-speed operability, radiation properties and electric characteristics. Leads made of Cu and electrically connected to the semiconductor chip are held between the base portion and the sealing portion, and have anchor holes formed in the portions thereof held therebetween. A glass-based adhesive is coated in the anchor holes, between the held portions of the leads and the base portion, and between the held portions and the sealing portion.
    Type: Grant
    Filed: November 6, 1995
    Date of Patent: July 30, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Megumi Kusumi
  • Patent number: 5539151
    Abstract: One or more reinforcement pins are inserted between the lid and base of a sealed integrated-circuit package. The reinforcement pins reinforce a sealing layer between the lid and the base, particularly against shear forces exerted on the sealing layer between the lid and the base of a package. Shorter pins are provided which do not extend through the lid or base. Longer pins are provided which extend through the lid or base, with the ends of the pins being mechanically secured to the lid or base and sealed with solder, glass, or epoxy material.
    Type: Grant
    Filed: July 23, 1993
    Date of Patent: July 23, 1996
    Assignee: VLSI Technology, Inc.
    Inventors: Ahmad Hamzehdoost, Leonard L. Mora
  • Patent number: 5521436
    Abstract: A semiconductor device includes a semiconductor substrate forming the bottom portion of a package of the device and a ceramic plate forming the upper or lid portion of the device. The substrate includes a layer of metal on its upper surface along the substrate outer edge and spaced apart from electrodes on the substrate upper surface. The ceramic plate includes a copper foil on its lower surface along the outer edge thereof which overlaps and is bonded to the substrate metal layer. The ceramic plate has apertures therethrough which are sealed by copper foils on the inside of the package, the foils being bonded to respective ones of the substrate electrodes.
    Type: Grant
    Filed: August 17, 1993
    Date of Patent: May 28, 1996
    Assignee: Harris Corporation
    Inventor: Victor A. K. Temple
  • Patent number: 5498900
    Abstract: An integrated circuit package for use in radiation environments includes a base and a lid of insulative materials. The base has a recess for receiving a die and a seal ring located on the periphery. The lid has a central insulation portion and an outwardly extending flange which can be welded to the seal ring.
    Type: Grant
    Filed: December 22, 1993
    Date of Patent: March 12, 1996
    Assignee: Honeywell Inc.
    Inventors: Thomas J. Dunaway, Richard K. Spielberger
  • Patent number: 5497032
    Abstract: A semiconductor device having a package in which a semiconductor device is sealed includes a base, and a metallic film is formed on a surface of the base. The semiconductor chip is formed on the metallic film. A pad formed on the semiconductor chip is connected to the metallic film by a wire. A sealing layer is formed on the metallic film. Leads are formed on the glass layer. A connecting layer is formed on the metallic film and contains electrically conductive particles. The connecting layer is in contact with a lead for a power supply system and connecting the metallic film to the lead.
    Type: Grant
    Filed: March 16, 1994
    Date of Patent: March 5, 1996
    Assignees: Fujitsu Limited, Kyushu Fujitsu Electronics Limited
    Inventors: Kazuto Tsuji, Yoshiyuki Yoneda, Hideharu Sakoda, Michio Sono, Ichiro Yamaguchi, Toshio Hamano, Yoshihiro Kubota, Michio Hayakawa, Yoshihiko Ikemoto, Yukio Saigo, Naomi Miyaji
  • Patent number: 5465008
    Abstract: A ceramic microelectronic package suitable for high-frequency microelectronic devices includes a base which is at least partially conductive attached either by seal glass or by solder to a ceramic RF substrate with a cavity formed at its center and a pattern of conductive paths for providing interconnection from the inside to the outside of the package. The base may be metal or ceramic with a metal layer deposited thereon. A ceramic seal ring with a second cavity corresponding to that of the RF substrate, but slightly larger, is attached to the RF substrate by seal glass which is patterned to generally match the dimensions of the seal ring. A ceramic lid is attached to the top of the seal ring by a non-conductive adhesive, such as a polymer adhesive or low temperature seal glass, to seal the package once the microelectronic device has been mounted inside.
    Type: Grant
    Filed: October 8, 1993
    Date of Patent: November 7, 1995
    Assignee: Stratedge Corporation
    Inventors: Martin Goetz, Joseph Babiarz, Deborah S. Wein, Paul M. Anderson, Alan W. Lindner
  • Patent number: 5455457
    Abstract: A package for one or a plurality of semiconductor elements comprises a package substrate, at least one semiconductor element mounted on the package substrate having an active layer in a surface which faces away from the package substrate, a thin pliable electrically insulating resin layer applied to the surface of each semiconductor element, a metal cap which cooperates with the package substrate to hermetically enclose the space containing one or more semiconductor elements, and a heat diffusing plate of high thermal conductivity provided between the electrically insulating resin layer of each semiconductor element and the metal cap. A part of heat generated in the active layer is conducted through the heat diffusing plate to the metal cap and is released there, thereby shortening the heat path and reducing the heat-releasing surface of the package substrate.
    Type: Grant
    Filed: January 5, 1993
    Date of Patent: October 3, 1995
    Assignee: Nec Corporation
    Inventor: Yasuhiro Kurokawa
  • Patent number: 5455456
    Abstract: A novel lid for sealing an encapsulant within a cavity of an integrated circuit package is disclosed herein. A ring is formed around a cavity opening, where a semiconductor die is located in an integrated circuit package. A lid, having a radially extending potion biased toward the die, is adapted to engage the cavity opening. According to one embodiment of the invention, a dam ring is disposed on the top surface of an integrated circuit package so as to form the cavity opening. A radially extending potion of the lid is adapted to engage the inner or outer surface of the ring so as to retain the lid in close communication with the cavity opening and seal the encapsulant within the cavity. Alternatively, the lid can be adapted to engage the cavity opening as existing in the top surface of an integrated circuit package. The present invention is especially advantageous in conjunction with ball grid array ("BGA") packages and pin grid array ("PGA") type IC packages.
    Type: Grant
    Filed: September 15, 1993
    Date of Patent: October 3, 1995
    Assignee: LSI Logic Corporation
    Inventor: Keith G. Newman
  • Patent number: 5455386
    Abstract: There is disclosed an adhesively sealed electronic package in which a compensation apparatus is provided for excess adhesive. As a result, excess adhesive does not extend beyond the package perimeter, squeeze-out, or travel along the inner lead fingers interfering with wire bonding. The compensation is a chamfer on the peripheral edges and/or interior edges of the package base component and cover component.
    Type: Grant
    Filed: January 14, 1994
    Date of Patent: October 3, 1995
    Assignee: Olin Corporation
    Inventors: George A. Brathwaite, German J. Ramirez, Michael A. Holmes, Paul R. Hoffman, Dexin Liang
  • Patent number: 5444286
    Abstract: A semiconductor pressure sensor has a package base provided with an adhesive supporting portion for supporting nearly the entire lengths of inner portions of outer leads. Since nearly the entire lengths of the inner portions in a package are supported, the inner portions do not resonate even if the semiconductor pressure sensor vibrates, thereby preventing detachment of the wires bonded to the ends of the inner portions.
    Type: Grant
    Filed: February 3, 1994
    Date of Patent: August 22, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Motomi Ichihashi
  • Patent number: 5436407
    Abstract: An improved metal semiconductor package is described. The semiconductor package includes a lead frame with a top side and a bottom side. A semiconductor is positioned on the top side of the lead frame. Bond wires electrically couple the lead frame to the semiconductor die. A metallic base is positioned at the bottom side of the lead frame. A metallic cap is positioned over the top side of the lead frame. The metallic cap includes a central aperture that is aligned with the semiconductor die. An external plastic seal is used to join the metallic base, lead frame, and metallic cap. The external plastic seal may be in the form of a perimeter seal or a body seal.
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: July 25, 1995
    Assignee: Integrated Packaging Assembly Corporation
    Inventors: Gerald K. Fehr, Victor Batinovich
  • Patent number: 5416358
    Abstract: An IC card includes: a circuit board on which functional components are mounted; and a frame covered with a thin plate, the circuit board being disposed in the frame, the inside of the frame being filled with a foamed resin. As a result of the above arrangement, an IC card having a strong resistance to various external forces is produced. Furthermore, because it is possible to incorporate a surface material with a design in an integrally molded device, thus it is also possible to produce an IC card device having an excellent appearance.
    Type: Grant
    Filed: September 16, 1993
    Date of Patent: May 16, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Katsunori Ochi, Syojiro Kodai, Tuguo Kurisu, Osamu Murakami, Makoto Kobayashi
  • Patent number: 5412247
    Abstract: A protection and packaging system for a semiconductor circuit having a first planar surface and an active region on at least a portion of the planar surface. An adhesive securely bonds a protective member directly to the first planar surface for generally protecting and hermetically sealing at least the active region of the semiconductor circuit. The protective member has a coefficient of thermal expansion which matches or closely matches that of the semiconductor device. The protective member may include an electrically conductive member and may have one or more openings. Individual electrically conductive members distribute power and ground to the active region of the circuit through bonding wires and contact pads located within the openings.
    Type: Grant
    Filed: January 25, 1991
    Date of Patent: May 2, 1995
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventor: Jacob Martin
  • Patent number: 5394011
    Abstract: A package structure in which conductive layers are provided on the lower surface of a circuit substrate provided with a semiconductor element mounted on the upper surface thereof, which conductive layers are connected to a conductive seal portion via conductive through holes, whereby both satisfactory air-tightness and satisfactory electromagnetic shielding characteristics of the package structure can be obtained. Projections consisting of high-temperature solder are formed as externally connecting electrodes, whereby a surface packaging operation can be carried out smoothly.
    Type: Grant
    Filed: July 6, 1993
    Date of Patent: February 28, 1995
    Assignees: Iwaki Electronics Co. Ltd., Fuji Electrochemical Co., Ltd.
    Inventors: Hiroyasu Yamamoto, Takayuki Konuma, Akira Shika, Hiroyoshi Suzuki, Masanori Katouno, Kaori Sato
  • Patent number: 5343076
    Abstract: This invention relates to a package construction of a semiconductor device, and provides a semiconductor device in which a vapor-impermeable moistureproof plate is embedded in a bottom surface of a hollow package or an inner surface wallthicknesswise therefrom to provide an excellent moisture-proofness in terms of the package construction.
    Type: Grant
    Filed: November 22, 1993
    Date of Patent: August 30, 1994
    Assignee: Mitsui Petrochemical Industries, Ltd.
    Inventors: Shigeru Katayama, Kaoru Tominaga, Junichi Yoshitake
  • Patent number: 5329160
    Abstract: In a semiconductor package in which a cover and a substrate are combined with each other in a sealed state, metallized portions consisting of a material of a high solder wettability are provided on the joint surface, which is opposed to the substrate, of the cover, outer side surfaces of the cover, and the portions of the inner side surfaces of the cover which are in the vicinity of the joint surface. These metallized portions are formed so that the height thereof on the outer side surfaces of the cover is larger than that on the inner side surfaces thereof. The metallized portions on the outer side surfaces are formed so that the height thereof at the corner portions of the cover is larger than that at the intermediate portions of the four sides thereof, and the metallized portions on the inner side surfaces are formed so that the height thereof at the intermediate portions of the four sides of the cover is larger than that at the corner portions thereof.
    Type: Grant
    Filed: February 11, 1992
    Date of Patent: July 12, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Shinya Miura, Kouzou Kanda, Mitsugu Shirai
  • Patent number: 5323058
    Abstract: A semiconductor device includes: a base and a cap having sealing surfaces furnished with a structure to prevent outflow of resin on the inner side of each corner thereof; and a lead frame arranged between the sealing surfaces of the base and the cap, with a part of the lead frame extending into each corner of the sealing surfaces, whereby the generation of recesses and holes in the resin sealing portion is prevented and a high-quality semiconductor device can be obtained which provides a satisfactory production yield.
    Type: Grant
    Filed: February 9, 1993
    Date of Patent: June 21, 1994
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Namiki Moriga
  • Patent number: 5317478
    Abstract: A hermetically sealed electronics package in which an electronic element located on a support is hermetically sealed using a cover comprising the top layer of a multilayer flexprint or a separate flexprint. The top layer of the flexprint or the separate flexprint is supported above the electronic element by a frame structure. When the cover comprises the top flexprint layer, the top layer is only partially bonded to the underlying flexprint during fabrication of the package. After circuit placement, the flap portion of the top flexprint layer is bonded to the flexprint to provide hermetic sealing of the underlying electronic elements. The frame structure provides support for the flexprint cover to prevent deformation of the cover and resulting damage to the underlying circuit. A cooling system is also disclosed for use in combination with the hermetic seal configuration to provide an electronic package which is protected from both contaminants and built-up heat.
    Type: Grant
    Filed: March 30, 1993
    Date of Patent: May 31, 1994
    Assignee: Hughes Aircraft Company
    Inventor: Mohi Sobhani
  • Patent number: 5315153
    Abstract: A ceramic package comprising an aluminum nitride substrate, an IC on the substrate, leads attached to the substrate, a metal cap covering the substrate, a resin layer for adhesion of the above elements, and a water-resistant coating on the inner surface of the resin layer.
    Type: Grant
    Filed: May 29, 1991
    Date of Patent: May 24, 1994
    Assignees: Toyo Aluminium Kabushiki Kaisha, Kabushiki Kaisha Enplas
    Inventors: Yuji Nagai, Eiki Tanikawa, Hisao Ohshima, Kazushige Kato
  • Patent number: 5302852
    Abstract: A semiconductor device includes a semiconductor element, a base, a cap, leads, and low-melting glass. The semiconductor element is mounted on the base, and the base consists of high-purity alumina and has a thickness of 0.5 mm or less. The cap is arranged on the base to cover the semiconductor element, consists of translucent alumina, and has a thickness of 0.4 mm or less. The leads extend out of the semiconductor device to be interposed between the base and the cap, and are electrically connected to the semiconductor element. The low-melting glass integrally and hermetically seals the base, the leads, and the cap.
    Type: Grant
    Filed: February 23, 1993
    Date of Patent: April 12, 1994
    Assignee: NEC Corporation
    Inventors: Kenichi Kaneda, Akio Tanda
  • Patent number: 5278429
    Abstract: A semiconductor device includes a package, a semiconductor chip provided on the package, an intermediate layer formed on the package, an adhesive layer formed on the intermediate layer, and a lid formed on the adhesive layer and sealing the semiconductor chip. The intermediate layer contains a major component which is the same as a major component of the package.
    Type: Grant
    Filed: April 20, 1993
    Date of Patent: January 11, 1994
    Assignee: Fujitsu Limited
    Inventors: Takeshi Takenaka, Toshio Hamano, Takekiyo Saito
  • Patent number: 5256901
    Abstract: A ceramic package for a memory semiconductor accommodates therein the memory semiconductor and is sealingly closed by an ultraviolet ray transmissible ceramic lid. The ceramic lid is made of a polycrystalline alumina and formed with at least one groove in a sealing portion with the ceramic package. With the arrangement, the ceramic package is superior in sealing strength, air-tightness and ultraviolet ray transmission and can easily accommodate any increase of memory amount of semiconductor elements.
    Type: Grant
    Filed: July 20, 1992
    Date of Patent: October 26, 1993
    Assignee: NGK Insulators, Ltd.
    Inventors: Toshio Ohashi, Masaki Wakayama
  • Patent number: 5250845
    Abstract: The hermetic module (10) has a frame 12 with an integral heat sink panel (20) extending thereacross between the side walls (14, 16). High-density integrated circuit electronics are mounted on the heat sink panel by hybrid assembly techniques. Covers (36, 38) are welded to the walls to achieve closure. Feedthrough 74 includes connector block (84) extending through an opening in front bulkhead (76). The front bulkhead is Kovar clad, and seal is achieved by means of a Kovar flexible seal extending between the Kovar side of the front bulkhead and the Kovar ring on the connector block.
    Type: Grant
    Filed: November 30, 1990
    Date of Patent: October 5, 1993
    Assignee: Hughes Aircraft Company
    Inventor: Michael D. Runyan
  • Patent number: 5230759
    Abstract: A process for hermetically sealing a cap (7) to a package base (1), on which a semiconductor chip (2) is mounted, by an adhesive resin. First, the base (1) is coated with a thermosetting silicone resin (10) along a frame-shaped abutting portion, then the silicone resin is completely hardened and becomes a silicone rubber, and thereafter, the silicone rubber is coated with a thermosetting sealing resin (11) having a good adhesion with the slicone rubber. The cap is then abutted against the base, and the base and cap are heated while a pressure is exerted thereon to press the base and the cap toward each other.
    Type: Grant
    Filed: August 17, 1992
    Date of Patent: July 27, 1993
    Assignee: Fujitsu Limited
    Inventor: Katsuro Hiraiwa