Abstract: A wiring structure for effectively reducing wiring capacitance, and a method of forming the wiring structure is disclosed. An underlying film having a dielectric constant lower than that of silicon oxide is formed on at least side surfaces of the wires of a wiring layer and a low dielectric constant film having an even lower dielectric constant is formed between the wires. Further, the surfaces of the underlying film are positively sloped. Because the low dielectric constants of the underlying film and the low dielectric constant film, wiring capacitance is effectively reduced. Further, the positively sloped surfaces facilitate the filling of narrow spaces between the wires by the low dielectric constant film.

Abstract: The present integrated chip package provides a low cost package that is suitable for high density semiconductors that have high power dissipation. The integrated chip package includes at least one semiconductor chip having a first surface and a second surface. The first surface of the semiconductor chip is electrically coupled to an intermediate substrate via conductive bumps. The intermediate substrate is also electrically coupled to a package substrate via a plurality of bonding wires. The second surface of the semiconductor chip is thermally coupled to a heat sink to increase the power dissipation capacity of the integrated chip package.

Abstract: A method is disclosed for applying a plurality of caps to a plurality of microfabricated devices at the wafer stage. A wafer is provided-having a plurality of microfabricated devices. The method requires forming a plurality of first hollow molded caps from a layer of thermoplastic material which is placed in a mold. The mold has first and second mold halves which are brought together to form the caps. Each cap has a central portion and a perimeter wall. The caps are formed first as an array of caps in the mold. Separated caps are applied simultaneously to one side of the wafer. The first caps are attached to the wafer, and then the wafer is then eventually separated into individual chips.

Abstract: A ball grid array (BGA) package that includes a central cavity for receiving a semiconductor die therein is disclosed. The die rests on a base laminate, the die side of which includes traces therein extending into the cavity, which is framed at least by an anisotropically conductive adhesive layer. Bond pads on the die are electrically connected, as by wire bonds or, in the case of a flip-chip configured die, solder balls or conductive adhesive elements, to the traces. The traces are, in turn, electrically connected through conductive vias to conductive element sites on the opposite side of the base laminate through a dielectric layer, the conductive element sites carrying solder balls or other discrete conductive bonding elements for connection to higher-level packaging.

Abstract: The present integrated chip package provides a low cost package that is suitable for high density semiconductors that have high power dissipation. The integrated chip package includes at least one semiconductor chip having a first surface and a second surface. The first surface of the semiconductor chip is electrically coupled to an intermediate substrate via conductive bumps. The intermediate substrate is also electrically coupled to a package substrate via a plurality of bonding wires. The second surface of the semiconductor chip is thermally coupled to a heat sink to increase the power dissipation capacity of the integrated chip package.

Abstract: A method is taught for applying and accurately locating a plurality of caps to a plurality of microfabricated devices at the wafer stage. The method involves using a two part mold to make a plurality of first hollow molded caps. The caps are made from a layer of thermoplastic material which is placed in the mold. Each cap having a central portion and a perimeter wall. The mold is opened so that the caps are carried by the first half. The caps are applied to a wafer using the first half. After the caps are applied, the wafer may be separated into individual chips.

Abstract: The present invention allows non-wafer form devices to be tested on a standard automatic wafer-probe tester or other automated test or measurement device commonly employed in semiconductor or allied industries (e.g., flat panel display, data storage, or the like) processes. The present invention accomplishes this by providing a low-profile carrier for temporarily mounting a non-wafer form device. The low-profile carrier holds the non-wafer form device (e.g., an integrated circuit chip, a thin film head structure, one or more molded array packages, etc.) magnetically into recesses which are machined or otherwise formed in the low-profile carrier.

Abstract: A semiconductor package has a printed circuit board, an integrated circuit chip on the printed circuit board with an exposed semiconductor die, and a rigid structure secured to the printed circuit board and enclosing the exposed semiconductor die. The exposed surface of the semiconductor die placed is in thermal contact with an inner surface of the rigid structure with a compressible material.

Abstract: An acceleration sensor which is inexpensive and accomplishes its small-size and light-weight structure, and a manufacturing method thereof. A sensor unit provided on a base is sealed by a cap joined to a frame portion of the base in an eutectic manner. The cap includes a cap main body made of a semiconductor material having a conductive property and a metal film provided on the circumferential edge of the cap main body. The frame portion includes a frame main body made of doped polysilicon, a diffusion preventive film selectively provided on the frame main body, and a joining layer. The joining layer has one area as a conductive portion made of a conductive material, and another area as a joining portion made of a semiconductor.

Abstract: A solder joint or seal attaching components having dissimilar coefficients of thermal expansion is made thin (e.g., less than 20 ?m and preferably about 5 ?m) and of a solder such as an indium-based solder that has a tendency to creep. The solder is toroidal or otherwise shaped to avoid tensile stress in the solder. Axial shearing stress in the solder causes reversible creep without causing failure of the joint or seal. In one embodiment, a toroidal solder seal has a diameter, a footprint, and a thickness in approximate proportions of 5000:200:1.

Abstract: In preferred embodiments, a compact a hybrid integrated circuit device 1 can be provided. A conductive pattern 12 is formed on the top surface of a circuit substrate 10, on the top surface of which an insulating layer 11 has been provided. Conductive pattern 12 is formed over the entirety of the top surface of the circuit substrate. Specifically, conductive pattern 12 is also formed at parts within 2 mm from the peripheral ends of circuit substrate 10. Also, a heat sink 13A or other circuit element 13 with some height can be positioned near a peripheral end part of circuit substrate 10. By arranging hybrid integrated circuit device 1, the degree of integration of hybrid integrated circuit is improved. Thus, in a case where the same circuit as a prior-art example is formed, the size of the entire hybrid integrated circuit device can be made small.

Abstract: Bumps are formed on electrodes of semiconductor elements, and moreover, the semiconductor elements with the bumps are electrically connected to metallic members having installation members, whereby wiring lines are eliminated. Stray inductance and conduction resistance resulting from wiring lines can be reduced. A conventional dented connector and a projecting connector are eliminated by connecting the installation members to a second circuit board, thereby enabling an electronic circuit device of a power control system to be made compact.

Abstract: A protective device is provided for subassemblies having a substrate and a component disposed thereon and needing to be protected. The component typically is a semiconductor component. The protective device includes a covering element, a spacer, and a guide. The covering element covers a subassembly. The spacer is disposed between the covering element and the substrate for maintaining a predefined spacing between the covering element and the component to be protected in the area of the spacer. The guide is used for fixing a free end of the spacer to the covering element and/or to the substrate in a predefined X and/or Y position.

Abstract: An integrated microwave module comprising a conductive ground plane, a non-conductive substrate on the ground plane, at least two microwave circuits mounted on the substrate, a microstrip line between the microwave circuits mounted on the substrate, and a conductive cover closing the integrated microwave module. The substrate comprises a line of metallized holes along both sides of the microstrip line, and a strip of conductive paste is disposed between the lines of metallized holes and the conductive cover.

Abstract: The present integrated chip package provides a low cost package that is suitable for high density semiconductors that have high power dissipation. The integrated chip package includes at least one semiconductor chip having a first surface and a second surface. The first surface of the semiconductor chip is electrically coupled to an intermediate substrate via conductive bumps. The intermediate substrate is also electrically coupled to a package substrate via a plurality of bonding wires. The second surface of the semiconductor chip is thermally coupled to a heat sink to increase the power dissipation capacity of the integrated chip package.

Abstract: A die has a part that is sealed with a cap. The seal can be hermetic or non-hermetic. If hermetic, a layer of glass or metal is formed in the surface of the die, and the cap has a layer of glass or metal at a peripheral area so that, when heated, the layers form a hermetic seal. A non-hermetic seal can be formed by bonding a cap with a patterned adhesive. The cap, which can be silicon or can be a metal paddle, is electrically coupled to a fixed voltage to shield the part of the die.

Abstract: The electrodes of a light emitting diode (LED) is coupled to the terminals of a package with solderless pressure contacts. Each package is housed in a module with a bed on which the bottom electrode of the LED rests, and a pressure plate which is coupled to the top electrode of the LED. The pressure plate slides along four vertical posts to exert pressure to an LED package against a bed to form solderless pressure contacts. A plurality of LED packages can be lined up in a row to form a light strip, with the top pressure plate extended to form the bed of an adjacent module. A plurality of LED packages can also be arranged a matrix array display panel, where a plurality of lower terminals rests on one row of common bed of a number of parallel horizontal common beds, and where a plurality of upper terminals are pressed under a column of parallel vertical common pressure plates, so that any individual LED at the cross-point of a common bed and a common pressure can be randomly accessed.

Abstract: A chip carrier plate. The chip carrier plate comprises a base, a protruding face, and a receiving face. The protruding face is disposed on the base. The receiving face is formed on another side of the base opposite to the protruding face. A plurality of recesses is formed on the protruding face. Each recess has a first spacer and a second spacer disposed on the bottom surface therein.

Abstract: There is provided an EL device which has sufficient strength to external pressure and is capable of effectively preventing moisture and oxygen from infiltrating into the EL device, thereby having a prolonged life. An organic EL device 200 is comprised of a substrate 1, an organic EL multilayer film 2 that is formed on the substrate 1, and a sealing plate 31 that is bonded onto the substrate 1 using an adhesive 4 so as to cover the organic EL multilayer film 2. The sealing plate 31 is of a flangeless type, wherein the width of peripheral projecting parts thereof is not less than the thickness at these peripheral projecting parts, and moreover is not less than 0.7 mm.

Abstract: Structures and methods for providing magnetic shielding for integrated circuits are disclosed. The shielding comprises a foil or sheet of magnetically permeable material applied to an outer surface of a molded (e.g., epoxy) integrated circuit package. The foil can be held in place by adhesive or by mechanical means. The thickness of the shielding can be tailored to a customer's specific needs, and can be applied after all high temperature processing, such that a degaussed shield can be provided despite use of strong magnetic fields during high temperature processing, which fields are employed to maintain pinned magnetic layers within the integrated circuit.

Abstract: An integrated sensor and electronics package wherein a micro-electromechanical sensor die is bonded to one side of the package substrate, one or more electronic chips are bonded to an opposite side of the package substrate, internal electrical connections run from the sensor die, through the package substrate, and to the one or more electronic chips, and input/output connections on the package substrate are electrically connected to one or more of the electronic chips.

Abstract: The invention provides a ceramic package, a ceramic package having such a sealing structure and a fabrication method of thereof. In the ceramic package, a wall layer made of a plurality of laminated ceramic sheets and having a cavity formed in a central portion thereof is stacked on a top of a base layer made of a plurality of laminated ceramic sheets. A metal layer is coated on the wall layer around the cavity to expose an outer peripheral portion of the wall layer. A glass layer is coated on the outer peripheral portion of the wall layer, which is not coated with the metal layer, to contact with the metal layer. A lid is attached on the metal layer to seal the cavity. The glass layer is coated around the metal layer, which is attached on the ceramic wall layer around the cavity, to reinforce the bonding force between the metal layer and the underlying ceramic wall layer thereby potentially preventing creation of cracks between the metal layer and the underlying ceramic wall layer.

Abstract: A thermally enhanced wirebond BGA package having a laminate substrate, an IC device mounted on the substrate, and a metal cap defining a cavity inside the package between the IC device and the metal cap. A substantial portion of the cavity is filled with a thermally enhanced epoxy encapsulant establishing a thermal conduction path between the IC device and the metal cap. The BGA package may be further enhanced by bonding a metal heat slug on the laminate substrate and mounting the IC device on the slug.

Abstract: A CF card (1) comprises: a casing constituted by two panel plates (2, 2) and a frame (3); and a printed wiring board (4) accommodated in the casing. A plurality of claw-like engaging parts (5) are provided to the peripheries of the panel plates (2). When the CF card (1) is assembled, the engaging parts (5) of the first panel plate (2) are inserted into through holes of a long groove (8) provided in the frame (3) and then the printed wiring board (4) is mounted on the panel plate (2) located at the inside of the frame (3). Thereafter, the engaging parts (5) of the second panel plate (2) are inserted into the through holes of the long groove (8) from the surface located in the opposite side of the frame (3). There are two types of engaging parts (5): one having lances and the other having holes. Inside the through holes, the lances of the engaging parts (5) of one panel plate (2) are inserted into the holes of the engaging parts (5) of the other panel plate (2).

Abstract: An LED module includes a substrate having good thermal conductivity and one or more radiation-emitting semiconductor components that fixed on the top side of the substrate. The underside of the substrate is fixed on a carrier body having a high thermal capacity, in which the component fixing between the semiconductor components and the substrate and the substrate fixing between the substrate and the carrier body are embodied with good thermal conductivity. Furthermore, the invention relates to a method for producing the LED module, in which metal areas that are suitable as an etching mask improve the impressing of the current required during the anodic bonding, and at the same time, are used as contact areas for contact-connecting the radiation-emitting semiconductor components. The LED module has the advantage that the semiconductor components can be subjected to higher energization as a result of the high thermal capacity of the carrier body.

Abstract: A composite lid for a semiconductor package, in which the lid includes at least two materials. The first material is disposed over and attached to the back surface of the die with a low-modulus thermal gel, and the second material is disposed towards the perimeter of the lid. The second material has a modulus of elasticity greater than the modulus of elasticity of the first material, and preferable, at least twice that of the first material.

Abstract: According to one embodiment, an apparatus is disclosed. The apparatus comprises an integrated circuit (IC) having a plurality of connection pins, a carrier socket configured to carry the IC. The carrier socket protects the pins of the IC from bending. In addition, the carrier socket straightens pins that have been bent prior to placing the IC into the carrier socket.

Abstract: A plasma display device which improves the adhesion rate of a thermal conductive medium. A chassis base is disposed substantially parallel to a plasma display panel. A thermally conductive medium is disposed between the plasma display panel and the chassis base and is closely adhered to both the plasma display panel and the chassis base. An adhesive pad is interposed between the plasma display panel and the chassis base along the edge of the thermally conductive medium and is adhered to both the plasma display panel and the chassis base. The thermally conductive medium includes a plurality of thermally conductive particles of high thermal conductivity.

Abstract: A semiconductor package has a printed circuit board, an integrated circuit chip on the printed circuit board with an exposed semiconductor die, and a rigid structure secured to the printed circuit board and enclosing the exposed semiconductor die. The exposed surface of the semiconductor die placed is in thermal contact with an inner surface of the rigid structure with a compressible material.

Abstract: An integrated circuit package includes a first or active substrate and a second or passive substrate. The active substrate includes at least one circuit that generates heat during circuit operation. The passive substrate does not include any heat-generating circuits, although the passive substrate may include passive, disabled or dormant circuitry. The two substrates are preferably fabricated of semiconductor material and have substantially equal coefficients of thermal expansion. The passive substrate is thermally coupled to the active substrate preferably using a thin layer of adhesive, such as an epoxy. The passive substrate serves to thermally conduct the heat generated by the circuits of the active substrate away from the active substrate. An internal metallic heat sink may be optionally thermally coupled to the passive substrate to further aid in the transfer of heat away from the active substrate.

Abstract: An electronic component package includes a case having a cavity portion including an electronic component therein, and a lid member which is fusion-welded to the case via a fusion-welding layer to hermetically seal the cavity portion. The case has a first metal layer laminated on the case so as to be exposed on the open side at the cavity portion. The lid member has a core portion, and a second metal layer laminated on a side of the core portion facing the case. The fusion-welding layer has a soldering material layer formed of a soldering material, and first and second intermetallic compound layers disposed on opposite sides of the soldering material layer as a result of diffusion of a major component of the soldering material into the first metal layer and the second metal layer.

Abstract: A heat sink and heat spreader assembly including a solid member of a conductive material and a layer of a low melting alloy having phase change properties bonded to at least one surface of the solid member such that a welded joint is formed there between possessing a thickness of from 0.0001 to 0.020 inches and having a composition consisting essentially of said low melting alloy with the welded joint having an exposed relatively flat surface suitable for direct attachment to an electronic heat source or heat sink respectively.

Abstract: A packaged semiconductor device that is fabricated with a plurality of conductive leads defined in a strip that beneficially includes a radio frequency shield box. The conductive contacts are located in a housing, beneficially by insert molding or by sandwiching between a bottom piece and a top piece. The housing can further include a cavity that receives a semiconductor device, and the radio frequency shield can receive another semiconductor device. Bonding conductors electrically connect at least one semiconductor device to another semiconductor device and/or to the conductive contacts. A conductive cover is disposed over the housing. The cavity beneficially includes a beveled wall and the conductive leads and the radio frequency shield are beneficially comprised of copper.

Abstract: A semiconductor device has an insulating substrate with conductor patterns bonded to and formed on both the top and bottom surfaces of a ceramic substrate. Soldering is provided between the conductor pattern on the top surface side and a heat developing chip component such as a power semiconductor element is mounted thereon. Between the conductor pattern on the bottom surface side and a heat dissipating metal base plate, each of four corners of the ceramic substrate is chamfered to form a chamfered section with a chamfered dimension of 2 to 10 mm. Alternatively, slits can be formed at the four corners on the bottom surface side. Moreover, the thickness of the conductor patterns can be controlled in relation to the ceramic substrate. These configurations relax the stress concentration created in the soldered section due to a thermal cycle.

Abstract: An apparatus includes a device chip having circuit elements fabricated on a substrate and a cap covering at least a portion of the device chip including the circuit elements such as thin film resonators. The placement of the cap on the device chip is sealed using a gasket having treaded surface for improved adhesion, cold weld deformation of gold, and decreased susceptibility to foreign particles resulting in a superior seal.

Abstract: Methods and structures for die packages are described. The die package includes an integrated circuit die connected to and elevated above a substrate. In an embodiment, wire bonds connects pads on the die to pads on the substrate. The substrate pads are closely adjacent the die due to the die support being positioned inwardly of the peripheral surface of the die. In an embodiment, the die support includes a paste that flows outwardly when connecting the die to the substrate. The outward paste flow extends from beneath the die support but does not extend outwardly of the die so as to not interfere or contact the substrate pads.

Abstract: A wafer-level package with a cavity includes a chip, a substrate, and a seal member. The chip has a micro device and a plurality of bonding pads electrically connected to the micro device. The substrate has a plurality of through conductive vias corresponding and electrically connected to the bonding pads. Each of the bonding pads on the chip is provided with a conductive bump for electrically connecting the bonding pad to the conductive via. The seal member surrounds the package to form a hermetical cavity. The present invention further provides a method for fabricating the wafer-level package with a cavity.

Abstract: A heat sink assembly having a retaining device includes a heat sink (30), a retention frame (10), a rectangular fastener (50), four pins (20), and four springs (40). The heat sink includes a base (32) defining four bores (38) therein. The frame is secured to a printed circuit board (60) around an electronic package (70), and defines a pair of through holes (16). A pair of posts (55) depends from opposite sides of the fastener. The pins are received through the bores of the base and in the fastener. The springs surround the pins respectively between the base and the fastener. The posts are deformably extended through the through holes thereby compressing the springs and sandwiching the base between the frame and the springs. The springs cooperatively provide evenly distributed pressing forces on the base. The heat sink is thus easily, firmly and evenly secured to the electronic package.

Abstract: A reliable new IC package structure comprises an IC package having a plurality fo grounding conductor plates provided around its surrounding, a first conductor plate for covering over the IC package has downwardly flexed edges at its both sides to form two lugs, and each grounding plate is upwardly camberred to wrap corresponding first conductor plates. A second conductor plate with similar shape to the first one for covering the former closely coupled first and grounding conductor plates, the both sides of the second conductor is also downwardly flexed to form two lugs. A press block having an inner cavity to shade the IC package, first and second conductor plates. Several elastic press bars are installed in said inner cavity and above grounding conductors.

Abstract: A method for producing a multi-layer device. The method initially providing a substrate which comprises a support region for supporting an electrical component, then forming an electrically conductive bond layer on a surface of the substrate. The bond is configured to surround the region for supporting the component. The next step in the method is to provide an encasing layer in contact with the bond layer, such that the component is encased between the substrate and the encasing layer. The final step involves bonding the encasing layer to the bond layer to form a sealed cavity which encloses the component.

Abstract: A semiconductor package with a heat sink is provided in which at least one chip is mounted on the substrate and covered by a heat sink. The heat sink is formed with a flange in contact with the substrate, allowing a plurality of clip members to clamp the flange of the heat sink and the substrate. Each of the clip members has a recess portion for receiving the flange of the heat sink and the substrate to thereby firmly position the heat sink on the substrate. The clip members are engaged with edges of the heat sink and the substrate, thereby not affecting trace routability on the substrate. Moreover, the heat sink is mounted on the substrate and would not be dislocated.

Abstract: A semiconductor device of the invention comprises a semiconductor element provided within a housing, a bonding wire, a sealing resin member covering the semiconductor element and bonding wire, and a sheet member. The sheet member is fixed in the housing and arranged out of contact with the bonding wire, and moreover buried in the sealing resin member. Because the sheet member restrains the sealing resin member from vibrating, the bonding wire is connected with improved reliability. In place of the sheet member, it is possible to use a pillar member fixed on an insulating substrate. The semiconductor device is suitable for use on a mobile body, such as a vehicle, which proceeds with vibrations.

Abstract: A semiconductor device of a surface-mounting type has a mount surface and includes a semiconductor chip having a first surface, a second surface, a heat-generating portion located nearer to the second surface than the first surface and that generates heat during operation, and at least one patterned electrode formed on the second surface. A resin covers the semiconductor chip and an electrode terminal is extracted from the first surface of the semiconductor chip. A mounting face of the electrode terminal and a surface of the at least one patterned electrode are exposed to be substantially flush with a plane of the mount surface, and a perimeter of the at least one patterned electrode is surrounded by the resin.

Abstract: There exist a need in the art for an IC package that prevents the popcorn effect through every process step in forming an electronic device, as well as during operation of the device. This need is met by an integrated circuit package and a method of manufacturing an integrated circuit package which, during dispensing of an adhesive layer includes at least one via formed by dispensing the adhesive layer in a pattern such that it enables the release of vapor trapped in the integrated circuit package after the attachment of the heat spreader.

Abstract: A polygonal nut 5 for receiving a clamping bolt 7 is securely inserted in a nut insertion hole 6 which is formed in the thin portion 1a of the resin case 1, and the polygonal nut is engaged with an inner surface 6a of the nut insertion hole 6. The inner surface 6a of the nut insertion hole 6 has a round-shaped notch concave portion 6b formed at a position confronting to a corresponding corner portion 5b of the polygonal nut 5 so that the corner portion 5b of the polygonal nut 5 is not in contact with a resin case member to thereby prevent the resin case from being cracked.

Abstract: A semiconductor integrated circuit card is disclosed in which such a semiconductor integrated circuit chip device comprising a substrate having a circuit pattern formed thereon, a semiconductor circuit chip bonded onto the substrate and having an electrode connected to the circuit pattern, a reinforcement metal plate, and a seal resin portion for covering a peripheral face of the semiconductor integrated circuit chip and sticking the reinforcement metal plate onto the semiconductor integrated circuit chip is mounted within a card substrate.

Abstract: A multilayered substrate for a semiconductor device, which has a multilayered substrate body formed of a plurality sets of a conductor layer and an insulation layer, and having a face for mounting a semiconductor element thereon and another face for external connection terminals, the face for mounting a semiconductor device being provided with pads through which the substrate is connected to a semiconductor element to be mounted thereon, and the face for external connection terminals being provided with pads through which the substrate is connected to an external electrical circuit, wherein a reinforcing sheet is respectively joined to the face for mounting a semiconductor element thereon and the face for external connection terminals of the multilayered substrate body.

Abstract: A method and structure to adhesively couple a cover plate to a semiconductor device. A semiconductor device is electrically coupled to a substrate. A stiffener ring surrounding the semiconductor device is adhesively coupled to the substrate. A cover plate is adhesively coupled to both a top surface of the semiconductor device and a top surface of the stiffener ring using a first and second adhesive, respectively. The modulus of the first adhesive is less than the modulus of the second adhesive.

Abstract: A ball grid array (BGA) package includes a central cavity for receiving a semiconductor die therein. The die rests on a base laminate, the die side of which includes traces therein extending into the cavity, which is framed at least by an anisotropically-conductive adhesive layer. Bond pads on the die are electrically connected, as by wire bonds or, in the case of a flip-chip configured die, solder balls or conductive adhesive elements, to the traces. The traces are, in turn, electrically connected through conductive vias to conductive element sites on the opposite side of the base laminate through a dielectric layer, the conductive element sites carrying solder balls or other discrete conductive bonding elements for connection to higher-level packaging.

Abstract: A package for an integrated circuit chip adapted to operate at microwave frequencies. The package includes an electrically conductive lead frame having electrical leads extending outwardly from an inner region. A base section is adhesively affixed to a bottom portion of the lead frame. The base section and a plastic cover are configured to provide a cavity when the cover and the base section are affixed with the integrated circuit chip being disposed with such provided cavity. With another integrated circuit chip package, an electrically conductive lead frame has electrical leads adapted for electrical connection to the integrated circuit chip. The base section includes a conductive member nd a dielectric member. The dielectric member has an aperture disposed in registration with an inner region of the lead frame. The conductive member is electrically to a bottom surface portion of the integrated circuit. The integrated circuit chip being disposed in registration with the aperture.