Abstract: Semiconductor electronic parts 1 comprises electrode pads 7 formed on the surface of a base 2 and adapted to be connected to respective electrode terminals 4 and a bare chip 3 adhesive bonded to the surface of the base 2, wherein adhesive flow-in preventing means 12 is provided between the bare chip 3 and each of the electrode pad 7 for preventing the adhesive 10 for adhesive bonding the bare chip 3 to the base 2 from flowing in the electrode pads 7. Therefore, in an underfill process of adhesive bonding the base 2 to the bare chip 3 placed on the upper part thereof and sealing a gap between both of them with the adhesive 10 during manufacturing semiconductor electronic parts, the adhesive 10 is prevented from flowing out of the outside edge of the bare chip 3 and from depositing on the electrode pads 7 formed on the base 2.

Abstract: A semiconductor clamped-stack assembly (32) has at least two clamped stacks, each of these clamped stacks having a plurality of power semiconductor components (8) and a plurality of heat sinks (6), which are arranged in series along a horizontally extending axial direction (A). According to the invention, power semiconductor components (8) from different clamped stacks are assigned to one another and are located in a common mounting plane, which is perpendicular to the axial directions (A) of the clamped stacks (31). Mutually associated power semiconductor components (8) can be removed from the clamped-stack assembly or, respectively, inserted into the clamped-stack assembly in a common mounting direction, which lies in the mounting plane. Mutually associated power semiconductor components (8) are preferably mounted on a common plate (14). As a result, they can be dismantled when the clamped-stack assembly (32) is loosened, without further power semiconductor components or heat sinks having to be dismantled.

Abstract: A conductive cap for use in an electronic component, has an opening at a bottom portion thereof, and is constructed to be fixed to the upper surface of a substrate of the electronic component at the opening portion of the cap so as to cover at least an electronic component element mounted on the upper surface of the substrate having terminal electrodes provided thereon. The end surface of the opening and the inner and outer surfaces thereof in connection to and in the vicinity of the end surface are provided with an insulating film disposed thereon.

Abstract: An improved heat dissipation module for BGA IC's is a thin metal module used for heat dissipation in an encapsulated IC device. It has an annular base with several supports extending from its inner rim upwards to support a top plate. At least one protruding annular ring is provided on the top surface of the top plate. This design can ensure the top plate and a mold match during the capsulation process, avoid the glue overflow problem, and increase its total dissipation area to facilitate heat dissipation.

Abstract: An electronic package which has a thermally conductive member encapsulated with the semiconductor chip; and which is adapted for chip-scale or near-chip-scale applications of both wire-bond and flip-chip packages. For adhesively bonding the semiconductor chip to a circuitized carrier or substrate on which the chip is positioned, and to concurrently form an encapsulating structure protecting the semiconductor chip, there is provided a mold compound, such as a thermosetting plastic resin or epoxy to not only extend between the surface of the circuitized substrate or carrier facing the semiconductor chip, and possibly about the peripheral sides of the carrier, but to also at least extend over and encompass the peripheral edge portions of the opposite surface of the carrier or circuitized substrate distal to or facing away from the chip.

Abstract: Integrated circuit packages having offset segmentation, or splitting, of package power and/or ground layers and methods for preventing delamination in package substrates having segmented power and/or ground layers are described. The package substrate includes a plurality of split power and/or ground plane layers that are isolated by split lines. The split lines from at least two of the split power and/or ground plane layers are offset relative to one another. In some embodiments, in addition to being offset, the split lines may be arranged to minimize their respective cross-over points, as well as convoluted to increase their effective length.

Abstract: The present invention relates to a capsule (1) for at least one high power transistor chip (17) for high frequencies, comprising an electrically and thermally conductive flange (10), at least two electrically insulating substrates (15), and at least two electrical connections (16), and a cover member, where the high power transistor chip (17) is arranged on the flange (10). The high power transistor chip (17) and the electrically insulating substrates (15) are arranged on the flange (10). The electrical connections (16) are arranged on electrically insulating substrates (15) and the electrically insulating substrates (15) are connected to the flange (10) and open and separate from the high power transistor chip (17).

Abstract: An electronic package which has a thermally conductive member encapsulated with the semiconductor chip; and which is adapted for chip-scale or near-chip-scale applications of both wire-bond and flip-chip packages. For adhesively bonding the semiconductor chip to a circuitized carrier or substrate on which the chip is positioned, and to concurrently form an encapsulating structure protecting the semiconductor chip, there is provided a mold compound, such as a thermosetting plastic resin or epoxy to not only extend between the surface of the circuitized substrate or carrier facing the semiconductor chip, and possibly about the peripheral sides of the carrier, but to also at least extend over and encompass the peripheral edge portions of the opposite surface of the carrier or circuitized substrate distal to or facing away from the chip.

Abstract: A sealed electronic circuit module includes a ceramic chip carrier with a top surface, a cover having a mating surface and a seal at the periphery of the carrier between the carrier and the cover. The seal includes a non-metallic soft lower frame, preferably polyimide, atop the carrier at the periphery of the carrier. There is an upper adhesion layer shaped as a matching an upper frame facing downwardly from the cover towards the lower frame. Above the soft lower frame is a lower metal adhesion layer. Between the upper frame and the lower adhesion layer is a solder layer which has been heated to seal the cover to the chip carrier. The soft frame can include a channel through which a metal to metal via-seal is formed by the lower metal adhesion layer and the solder through the channel through the soft layer or there can be a lateral extension of the lower metal adhesion layer to a distal location beyond the periphery of the soft lower frame.

Abstract: An integrated circuit package having an encapsulating body with a flanged portion and an encapsulating mold for molding the encapsulating body are proposed. It is a characteristic feature of the proposed encapsulating mold that the encapsulating-body cavity formed in the upper mold further includes a constricted cutaway portion in the rim thereof. The constricted cutaway portion can be either uniform in thickness or formed in a multi-step staircase-like shape. During the molding process, the resin used to form the encapsulating body would flow into this constricted cutaway portion; and within the constricted cutaway portion, the resin would more quickly absorb the heat of the upper mold, thus increasing its viscosity and retarding its flowing speed. As a result, the resin would less likely to flash onto those surface parts of the substrate beyond the encapsulating body.

Abstract: A semiconductor package including a semiconductor chip having bonding pads respectively arranged in a line adjacent to four sides of the upper surface; gold bumps formed on each bonding pad; a glass substrate which is made by forming metal patterns, the metal pattern including an inner pattern electrically connected to the bonding pad of the semiconductor chip through the gold bumps, an outer pattern, and a connecting pattern between the inner pattern and the outer pattern: a Dam having a frame-shape on the connecting pattern and surrounding the inner patterns; sealing material sealing the space between the glass substrate around the semiconductor chip and solder balls attached on the outer patterns of each metal pattern.

Abstract: This semiconductor surface mount package is relatively inexpensive to produce and has a footprint that is essentially the same size as the die. A conductive substrate is attached to the back side of a wafer and is in electrical contact with a terminal on the back side of each die in the wafer. A nonconductive overcoat is formed and patterned on the front side of the wafer, leaving a portion of the passivation layer and the connection pads for the dice exposed, each of the connection pads being coated with a solderable metal layer. The assembly is then sawed in perpendicular directions along the scribe lines between the dice, but the saw cuts do not extend all the way through the substrate, which remains intact at its back side. The parallel cuts in one direction are broken to produce die strips which are mounted, sandwich-like, in a stack, with one side of the strips exposed.

Abstract: A hermetically sealed wafer scale package for micro-electrical-mechanical systems devices. The package consists of a substrate wafer which contains a microstructure and a cap wafer which contains other circuitry and electrical connectors to connect to external applications. The wafers are bonded together, and the microstructure sealed, with a sealant, which in the preferred embodiment is frit glass. The wafers are electrically connected by a wire bond, which is protected by an overmold. Electrical connectors are applied to the cap wafer, which are electrically linked to the outputs and inputs of the microstructure. The final package is small, easy to manufacture and test, and more cost efficient than current hermetically sealed microstructure packages.

Abstract: A semiconductor package is provided that includes a substrate having a top surface, a cover, and at least one semiconductor device attached to the top surface of the substrate. The cover is secured to the substrate so as to create a space between the interior surface and the substrate such that the semiconductor device resides within the space. The cover has an interior surface comprising a plurality of micro-channels. A wick is positioned in confronting relation to the plurality of micro-channels and the semiconductor device, with a two-phase vaporizable liquid disposed within the space.

Abstract: A BGA semiconductor package having an embedded heat sink is proposed. The heat sink mounted on a substrate includes a flat portion and supporting members for supporting the flat portion to be positioned above a semiconductor chip. The flat portion is formed with at least one taper air vent for ventilating air in a gap between the flat portion and the chip during a molding process. This further helps prevent voids from forming in an encapsulant due to the air trapped in a molding resin as being flowing slowly through the gap, and avoid the occurrence of a popcorn effect on the encapsulant during a temperature cycle in subsequent processes. As a result, quality and yield for the packaged products can be significantly improved.

Abstract: Chip lead frames are made by disposing a die having terminals on a substrate surface to form a cavity between the die and the substrate and contacts between the terminals and the substrate. A compound is applied to the surface such that the compound enters that cavity and forms a layer on the upper substrate surface. The layer can impart sufficient rigidity to the assembly that the substrate can be etched to produce a lead frame. Also disclosed are devices that include a die, a lead frame, and a continuous network that can form a layer on the lead frame and fill the cavity between the die and the lead frame.

Abstract: A BGA semiconductor package having an embedded heat sink is proposed. The heat sink mounted on a substrate includes a flat portion and supporting members for supporting the flat portion to be positioned above a semiconductor chip. The flat portion is formed with at least one taper air vent for ventilating air in a gap between the flat portion and the chip during a molding process. This further helps prevent voids from forming in an encapsulant due to the air trapped in a molding resin as being flowing slowly through the gap, and avoid the occurrence of a popcorn effect on the encapsulant during a temperature cycle in subsequent processes. As a result, quality and yield for the packaged products can be significantly improved.

Abstract: A central portion of a main face of a package substrate 2 is mounted with a memory chip 1 using face down bonding by a flip chip bonding system. Further, a plurality of chip condensers 7 are mounted at vicinities of the memory chip 1. A clearance between a main face (lower face) of the memory chip 1 and a main face of the package substrate 2 is filled with underfill resin (seal resin) 10 constituting a seal member for achieving protection of connecting portions and for relaxation of thermal stress. An outer edge of the underfill resin 10 is extended to an outer side of the memory chip 1 and covers entire faces of the chip condensers 7 mounted at vicinities of the memory chip 1.

Abstract: A package for hermetically sealing a micro-electromechanical systems (MEMS) device in a hybrid circuit comprise a firewall formed on a substrate for the MEMS device and which has a height defining a cavity of the package in which the MEMS device will be sealed. A second substrate spaced from the first substrate hermetically seals the cavity when the second substrate is flip-chip bonded to the first substrate and soldered to the first substrate with a thin film metal material placed on at least a top portion of the firewall. The resulting firewall MEMS device package can be further packaged using conventional CMOS packaging techniques. By hermetically sealing the cavity, the enclosed MEMS device is protected from deleterious conditions found in the environment of conventional CMOS packaging techniques which is often detrimental to MEMS device function.

Abstract: An apparatus on a wafer, comprising; a first metal layer of a wall, a second metal layer of the wall, a third metal layer of the wall comprising; one or more base frames, a fourth metal layer of the wall comprising; one or more vertical frame pairs each on top of the one or more base frames and having a pass-thru therein, a fifth metal layer of the wall comprising; one or more top frames each over the pass-thru; and a metal lid.

Abstract: A semiconductor device is provided which includes an insulating substrate, a conductive terminal supported by the substrate, a semiconductor chip mounted on the substrate, and a protection coating for enclosing the chip. The protection coating is integrally formed with an anchoring portion. The substrate is formed with an engaging portion for engagement with the anchoring portion of the coating.

Abstract: An electronic assembly that incorporates a heat sink. The subassembly includes an integrated circuit package that is mounted to a substrate. The substrate is mounted to a spacer block which includes a pin field that contains a plurality of pins. The heat sink is coupled to the integrated circuit package by a clip that wraps around the sink and is attached to the spacer block.

Abstract: A semiconductor device with a BGA package includes a substrate made of a resin and having one side on which a number of solder ball terminals are formed and the other side on which a chip mounting portion electrically connected to the solder ball terminals is formed, and a cover plate made of a metal and attached to a semiconductor chip so as to cover and come into contact with it under a condition where the semiconductor chip is connected to the resin substrate by a flip-chip process. The cover plate includes a base brought into contact with the semiconductor chip and a peripheral portion formed with a plurality of bonding portions where the cover plate is bonded to the substrate. The bonding portions are discontinuous to each other.

Abstract: The present invention is concerned with a miniature microdevice package and a process of making thereof. The package has a miniature frame substrate made of a material selected from the group including: ceramic, metal and a combination of ceramic and metal. The miniature frame substrate has a spacer delimiting a hollow. The package also includes a microdevice die having a microdevice substrate, a microdevice integrated on the microdevice substrate, bonding pads integrated on the microdevice substrate, and electrical conductors integrated in the microdevice substrate for electrically connecting the bonding pads with the microdevice. The microdevice die is mounted on the spacer to form a chamber. The microdevice is located within the chamber. The bonding pads are located outside of the chamber.

Abstract: A contactless interconnecting system is provided between a computer chip package and a circuit board. The system includes a computer chip package having a silicon wafer mounted on a support structure which includes a wall with a substantially planar upper surface. The wall is fabricated of a dielectric material. A pattern of discrete terminal lands are disposed on the upper surface of the wall and are electrically coupled to the silicon wafer. A circuit board is juxtaposed below the wall of the chip package and includes a substantially planar upper surface having a pattern of discrete circuit pads aligned with the terminal lands.

Abstract: In a magnetic random access memory has a memory device portion (33, 34, 35) using magnetic material, a high-frequency current suppressor (26) is arranged in the vicinity of the magnetic material to suppress a high-frequency current which flows in the memory device portion. The memory device and the high-frequency current suppressor may be collectively molded in a mold body (25) of a plastic resin. It is preferable that the high-frequency current suppressor is made by a thin film of a granular magnetic material which has a composition represented by M-X-Y where M is a magnetic metal element, Y is one element selected from oxygen, nitrogen, and fluorine, and X is an element other than M and Y.

Abstract: 1.

Abstract: An electronic package and/or package lid includes at least one connection slot for receiving a line, such as an optical fiber. The package and/or package lid also includes at least one sealant slot proximate the connection slot. Optical fibers are connected to a component, such as an opto-electronic component, through the connection slot. A sealant provided via the sealant slot hermetically seals the optical fibers within the connection slot.

Abstract: A method and apparatus for encapsulating microelectronic devices. In one embodiment, a microelectronic device is engaged with a support member having a first edge, a second edge opposite the first edge, and an engaging surface with at least a portion of the engaging surface spaced apart from the first and second edges. The first edge of the support member is positioned proximate to a wall of a mold and an aligning member is moved relative to the wall of the mold to contact the engaging surface of the support member and bias the first edge of the support member against the wall of the mold. The microelectronic device is then encapsulated by disposing an encapsulating material in the mold adjacent to the microelectronic device. By biasing the first edge of the support member against the wall of the mold, the method can prevent encapsulating material from passing between the first edge of the support member and the wall of the mold, where the encapsulating material would otherwise form flash.

Abstract: An electronic chip assembly having the following components: a substrate having electrical conductors therein; an electronic circuit chip affixed face down to the substrate so as to make electrical connection to the conductors; a male framing member, compliantly adhered to the substrate; a lid having a female channel, the channel having sidewalls, the channel being disposed on or within said lid for receiving said male framing member; and sealant material disposed within the channel between the sidewalls of said channel and the female lid sealing member.

Abstract: A method for producing reliable contacts in microelectronic devices and contacts produced thereby are provided. In one embodiment of the invention, a first conductive layer is formed over a first dielectric layer. The first conductive layer contains a pattern etched therein. A second dielectric layer is deposited over the first conductive layer and a via is etched therein over the pattern, thus exposing a portion of the pattern and the first conductive layer. The structure is then further etched to remove a portion of the first dielectric layer using the exposed portions of the first conductive layer as a mask. The structure is then subject to an isotropic etch to create undercuts in the first dielectric layer underneath the exposed portions of the first conductive layer. A conductive material can then be deposited into the via to fill the undercut, thus contacting the first conductive material on the exposed top, sides, and underside of the layer to produce a highly reliable contact.

Abstract: A hollow package includes a package body composed of an epoxy resin having a low thermal coefficient of linear expansion, wherein the package body includes a recess for receiving an electronic component, and leads, for extracting electrodes of the electronic component, extending from the inner surface of the recess, via the upper surface of the package body, to the peripheral surface, and a transparent sealing plate bonded onto the upper surface of the package body with an ultraviolet-curable resin.

Abstract: Solder compositions are introduced to interface between an IC chip and its associated heat exchanger cover. The solder compositions have a solidus-liquidus temperature range that encompasses the IC chip operational temperature range. The solder composition has the desired property of absorbing and rejecting heat energy by changing state or phase with each temperature rise and decline that result from temperature fluctuations associated with the thermal cycles of the integrated circuit chips. A path for high thermal conduction (low thermal resistance) from the IC chip to the heat exchanger to the ambient air is provided by an electronic module cover, configured as a cap with a heat exchanger formed or attached as a single construction, and made of the same material as the substrate, or made with materials of compatible thermal coefficients of expansion to mitigate the effects of vertical displacement during thermal cycling.

Abstract: A package for an integrated circuit device having an optical cell is disclosed. A method of making the package also is disclosed. The package includes a base of molded encapsulant material. A metal leadframe is embedded in the plastic base at the upper surface of the base. Encapsulant material covers the lower and side surfaces of the die pad and the leads of the leadframe, but does not cover the upper surfaces of the die pad and leads. The side surfaces of the die pad and leads have locking features for engaging the encapsulant material. An optical integrated circuit device is attached to the exposed surface of the die pad. An adhesive bead is applied around the optical device on the exposed upper surface of the leads. An optically clear cover is placed on and, in some embodiments, pressed into the still-viscous adhesive bead. When hardened, the bead supports the cover above the optical device.

Abstract: A package for an integrated circuit is described, as are methods of making the package. The package includes a substrate having a generally planar first surface on which a metal die pad is formed. An integrated circuit die is attached to the metal die pad. An adhesive head surrounds the integrated circuit die and covers the exposed periphery of the metal die pad. A generally planar lid is in a press-fitted interconnection with the bead. An adhesive material covers conductive structures on the die, such as bonding pads, to prevent corrosion. Optionally, the package has vertical peripheral sides. The methods of making the package include methods for making packages individually, or making a plurality of packages simultaneously. Where a plurality of packages are made simultaneously, integrated circuit die are placed on each of a plurality of physically-joined package substrates on a generally planar sheet of substrate material. An adhesive bead is applied around each die.

Abstract: An electronic apparatus of the present invention comprises an electronic circuit board; an electrically conductive casing for encasing the electronic circuit board; a semiconductor element module electrically connected to the electronic circuit board; and a resin fixture intervening between the electrically conductive casing and the semiconductor element module, the resin fixture mounted with the semiconductor element module and fitted to the electrically conductive casing. As a result, the resin fixture can suppress a transfer of heat generated in the electronic circuit board to the semiconductor element module.

Abstract: An improved die edge contacting socket incorporates particles of a thermally conducting material into an elastomeric compression pad disposed in the sealing cap of the socket. The elastomeric compression pad is preferably composed of an electrically insulating material, such as a silicone-based gel. The thermally conducting material is preferably either diamond, beryllium oxide, silicon nitride, or a like material.

Abstract: An electrical contact, preferably made from a gold-plated, beryllium-copper flat stock which allows radio-frequency signal to pass with low noise, is provided within a housing. The electrical contact has two arms for contact with two external circuits. The electrical contact further has a pivot for allowing the electrical contact to adjust within the housing. The housing supports the electrical contact and is provided with a pivot point, such as a non-conducting rubber tip, for meeting the pivot of the electrical contact. The housing combined with one or more of the electrical contacts results in a testing port especially suited for providing high frequency communication between an electrical testing fixture and a device under test, such as a high-frequency hybrid integrated circuit.

Abstract: The present invention relates to a power transistor module for radio frequency applications, particularly for use in an amplifier stage in a radio base station or in a ground transmitter for TV or radio, wherein said power transistor module comprises a support plate, a power transistor chip arranged thereon, outer electrical connections projecting from the module for external connection and inner electrical connections connected between said transistor chip and said outer connections, at least one of said inner electrical connections comprising a first conductor pattern arranged on a flexible foil. The invention further comprises a power amplifier comprising said module, a method in the fabrication of said module, a method in the fabrication of a power amplifier, where said module is electrically connected to a circuit board mounted at a heat sink and to be mounted at said heat sink, and finally to a power amplifier manufactured according to the method.

Abstract: An integrated circuit package with a fully-exposed heat sink is provided. The integrated circuit package includes a substrate having a first side being formed with first conductive traces and a second side being formed with second conductive traces. At least one chip is mounted on the substrate and electrically connected to the first conductive traces. A plurality of solder balls are provided at the terminal ends of the second conductive traces to allow external connection of the chip. The fully-exposed heat sink is mounted on the substrate. The heat sink is formed with a plurality of supportive legs arranged in such a manner as to allow a bottom surface of the heat sink to be separated from the chip and a top surface of the heat sink to be tightly attached to a cavity in a mold used to form an encapsulant for enclosing the chip. A plurality of positioning tongues are formed on the heat sink for securing the heat sink in position when performing a molding process for forming the encapsulant.

Abstract: The semiconductor device includes a substrate, a semiconductor component, and a cap covering the semiconductor component and attached to the substrate. The cap has a top wall, a plurality of side walls 14 extending downward from the top wall and a bottom wall. Opening are provided in the side walls of the cap at corners thereof. Due to the provision of openings, the cap can be manufactured without deformation thereof. Air or liquid can flow into, or out of, the interior of the cap, after the semiconductor deviced is completed.

Abstract: Large size multi-chip module packages are fitted with a new lid (1) formed of a Kovar™ (5) framed sheet of Alumina (3) no less than 0.04 inches thick to form a new “postless” MCM package 2 (FIG. 4 and FIG. 6) that is tolerant of differential pressures of at least one atmosphere and is reworkable. The rigidity of the Alumina sheet avoids the problem of excess deflection found in the prior lids for the package. It also permits elimination of internal lid support posts, freeing internal area within the MCM package that may be used to seat additional electronic circuitry and/or components.

Abstract: In a direct lid attach structure incorporating thermally conductive material between a lid and an electronic circuit chip, there are provided a number of apertures in the lid. These apertures are provided directly opposite disks or pads disposed on the substrate to which the chip is attached. A hardenable adhesive such as an epoxy is disposed through the apertures and hardened in place so as to provide a bond between the lid and the underlying pad which has been previously affixed to the substrate to which the chip is attached with a compliant adhesive. There is thus provided an electronic chip assembly which allows bonded chip-to-lid thermal interfaces to be used with LGA interconnection techniques. The support structure mitigates the mechanical loads associated with LGA socketing which could otherwise damage the substrate and affect the integrity of the bonded thermal interface.

Abstract: Tolerances in chip, substrate and hardware dimensions are accommodated by means of a floating sealing structure to insure that compliant thermally conductive paste disposed between the chip and its lid is as trim as possible in order to reduce thermal resistance of the paste so as to be able to run the chip at a cooler temperature. Standoffs are also preferably employed to insure proper paste gap thickness.

Abstract: An image taking element has a plurality of pins on one side thereof and a substrate is provided with a plurality of pads which are to be brought into electrical contact with the pins. The side of the image taking element is bonded to the substrate with each pin opposed to one of the pads by way of an anisotropic conductive adhesive layer which exhibits electrical conductivity only in a direction substantially perpendicular to the side of the image taking element.

Abstract: A printed circuit board thermal conductive structure comprises a thermal spreader layer having an embossed pattern formed on its surface, an adhesive glue layer formed over the thermal spreader, and a surface metallic layer attached to the thermal spreader and the glue layer. A portion of the surface metallic layer is in direct contact or almost direct contact with the thermal spreader. Furthermore, an additional external heat sink can be attached to thermal conductive structure to increase the efficiency of heat dissipation.

Abstract: A module mount for use in electrically and mechanically mounting an encapsulated power rectifier module, having a plurality of rigid leads protruding from a major mounting surface thereof, in an orientation in which the major mounting surface is substantially normal with respect to a substantially planar circuit board. In one embodiment, the module mount includes (1) a substantially planar substrate having a plurality of apertures located to register with the plurality of rigid leads and (2) a plurality of power conductors, associated with the plurality of apertures, that electrically couple the plurality of rigid leads to an edge interface on the substrate, the edge interface adapted to be coupled to the circuit board.

Abstract: A memory module having a packaging cover to encapsulate a board having multiple separate chips, which dynamically generate varying amounts heat. The packaging cover provides localized heat dissipation among the multiple separate memory chips. The separate chips are interconnected to the board via a set of solder balls. The packaging cover further provides a rigid encapsulation of the board and chips. In one embodiment, the memory module includes a thermally conductive substance displaced within the packaging cover to conduct heat from the separate chips to the packaging cover. In one embodiment, the packaging consist of a two separate metal covers. In one embodiment, a first cover of the packaging cover includes a first set of finger wraps and a second cover of the packaging cover includes a second set of finger wraps that interlace with the first set of finger wraps to secure a coupling between the first cover and a second cover of the packaging cover.

Abstract: An ultra-thin composite package for integrated circuits including a metal base with a cavity to support a die with a molded plastic cap cooperating with the base to encapsulate the die. A lead frame having a thinned inner portion or lead tip areas may also be used to further reduce the package thickness. Package thicknesses of about 20 mils (0.5 mm) or less can be readily achieved using this structure combination.

Abstract: An interconnected apparatus for producing a low loss, reproducible electrical interconnection between a semiconductor device and a substrate includes a rod and rod receptor. The rod, generally cylindrically shaped, is attached to the semiconductor device and includes an outer circumferential wall which comes into contact with the rod receptor during a bonding process. A lip portion is formed on one end of the rod receptor for interlocking engagement with the rod. The rod receptor is plated on the substrate and includes a generally circularly shaped body which forms a centrally disposed well for receiving the rod. A lip portion is formed on one end or mouth of the rod receptor for interlocking engagement with the rod. When the rod and corresponding receptor are aligned and brought together, the rod deforms and interlocks with its corresponding rod receptor. A thermo-compression bonding process is utilized to bond the rod to the rod receptor, thereby producing a strong interlocking bond.