Abstract: An electronic device includes a ceramic chip carrier having an opening, a SAW element chip housed in the opening, a Kovar sealing ring, which is bonded to the ceramic chip carrier by using an Ag brazing material or other suitable material such that the Kovar sealing ring encircles the opening, and a Kovar metal cap, which is placed on the Kovar sealing ring, wherein the Kovar metal cap is coated with Ni-plating which is used as a brazing material for seam-welding and bonding the Kovar metal cap to the Kovar sealing ring and the hermeticity between the metal cap and the sealing ring increases when the thickness of the Ni-plating is about 1 &mgr;m to about 2 &mgr;m.

Abstract: A semiconductor package including a conical or pyramidal vapor chamber body coupled to a package bottom to enclose a vapor chamber within which are disposed a semiconductor die and working fluid. A matching conical or pyramidal heatsink is coupled to the vapor chamber body. The conical or pyramidal shape allows a tight fit and good thermal performance, without undue force being applied to the package bottom, and further allows a variety of heatsinks to be used with a standardized shape vapor chamber body.

Abstract: An integrated circuit heat dissipation system for reducing the number of junctions in packaged integrated circuits thereby decreasing thermal impedance and increasing thermal dissipation efficiency. The integrated circuit heat dissipation system includes a lid attached to a substrate, a cap attached about the lid creating a heat dissipation chamber, and a semiconductor chip attached to the lid by a thermally conductive adhesive. The lid may or may not form a cavity about the semiconductor chip depending upon the substrate utilized. The lid preferably includes a plurality of fins extending from thereof defining a plurality of channels or a plurality of grooves thereby increasing the heat flux of the lid.

Abstract: An improved structure of heat dissipation fin for prevention of glue-overflowing in semiconductor packaging includes a substrate and a chip bonding module, wherein the heat dissipation fin is a thin housing structure having a bottom flat section and the center position is provided with a protruded section, forming into a covering body to cover the chip and the bonding body, the top section of the protruded section is provided with a first stepped platform and the inner edge of the platform is further formed into bottom recess structure and the wall thereof is then formed vertically into a raised second stepped protruded ring, and the center at the inner edge of the second stepped protruded ring is formed into a top recessed face, thereby the first stepped ring platform and the second stepped ring platform urge the top face of the top edge of the mold to form into a structure to block the packaging adhesive such that the adhesive will not overflow into the center position of the heat dissipation fin.

Abstract: The present invention is concerned with a miniature microdevice package and a process of making thereof. The package has a miniature frame substrate made of a material selected from the group including: ceramic, metal and a combination of ceramic and metal. The miniature frame substrate has a spacer delimiting a hollow. The package also includes a microdevice die having a microdevice substrate, a microdevice integrated on the microdevice substrate, bonding pads integrated on the microdevice substrate, and electrical conductors integrated in the microdevice substrate for electrically connecting the bonding pads with the microdevice. The microdevice die is mounted on the spacer to form a chamber. The microdevice is located within the chamber. The bonding pads are located outside of the chamber.

Abstract: A non-ceramic image sensor semiconductor package with improved moisture resistance, lower cost, and higher reliability is provided. A semiconductor chip with a vision chip active area is attached to a multi-layer resin mask organic substrate. A plurality of bonding wires are attached between parts of the semiconductor chip and the multi-layer resin mask organic substrate to create selective electrical connections. A castellation is formed to create a riser surrounding the semiconductor chip. The height of the castellations can be made to a desired height so that proper clearance of the semiconductor chip and the glass window is achieved. A transparent window is placed on the top of the castellations. A liquid encapsulant is formed to protectively seal the non-ceramic image sensor semiconductor package thereby shielding the semiconductor chip and vision chip active area from the external environment.

Abstract: An electronic component having recesses on side faces of its package for housing an electric element therein. A metal layer that does not reach the bottom end of the package is formed on the surface of the recess. The metal layer has excellent wettability to a brazing material and helps extra material flow into the recess easily. In addition, the interface between the top end face of the recess and the side face is curved to make the brazing material flow into the recess easily. When the opening of the package is sealed with a lid using the brazing material, the extra brazing material flows into the recess. This prevents the brazing material from protruding outside of the package and thus improves dimensional accuracy of the electronic component. Therefore, mounting accuracy of the electronic component can be improved and short circuit can be prevented.

Abstract: A source electrode, a gate electrode, and a drain electrode formed on a front face active region of a semiconductor substrate in a shape of teeth of a comb are covered with an insulating film such as polyimede etc., as well as all of the upper surface and the side surfaces of the insulating film are covered with a metal protective film. Via hole receiving pads connected to the source electrode, the gate electrode, and the drain electrode are respectively connected to bonding pads on a reveres face of the semiconductor substrate through via holes.

Abstract: In one embodiment, an integrated circuit packaging structure includes a first metal adhesion layer formed under a lid and a second metal adhesion layer formed over a substrate. The lid includes a free surface that may move a small amount without cracking. The second metal adhesion layer is configured such that its outer end does not extend past the free surface of the lid to minimize crack formation.

Abstract: In a magnetic random access memory having a memory device portion (33,34,35) using magnetic material, a high-frequency current suppressor (26) is arranged in the vicinity of the magnetic material to suppress a high-frequency current which flows in the memory device portion. The memory device and the high-frequency current suppressor may be collectively molded in a mold body (25) of a plastic resin. It is preferable that the high-frequency current suppressor is made of a thin film of a granular magnetic material which has a composition represented by M-X-Y where M is a magnetic metal element, Y is one element selected from oxygen, nitrogen, and fluorine, and X is an element other than M and Y.

Abstract: A composition for sealing a semiconductor device contains polyphenylene sulfide wherein a line expansion coefficient at 150° C. to 200° C. is 4.75×10−5 [1/° C.] or less, a line thermal expansion coefficient at 80 to 130° C. is 6.0×10−5 [1/° C.] or less, and a line expansion coefficient ratio between the flow direction and a normal direction of the flow direction is 0.55 or more.

Abstract: A personalized circuit module package and method for packaging circuit modules provides graphical packaging for memory modules and other circuit modules. A removable housing is attached to a circuit module containing one or more integrated circuits bonded to a carrier and covered with an encapsulant. Graphics may be printed on the removable housing, or may be printed on an insert that is either inserted into a pocket within the removable housing, or is inserted between a removable housing having a window and the circuit module. Alternatively, the housing itself may be used to personalize the circuit module, by providing a colored or textured removable housing for the circuit module.

Abstract: A modularly expandable semiconductor component includes at least one carrier layer, at least one intermediate layer, at least one coverlayer, at least one semiconductor chip, external contacts and a conductor configuration. The intermediate layer is provided with at least one opening, into which the at least one semiconductor chip is inserted. The carrier layer, the intermediate layer and the coverlayer are connected one above another and form a submodule. If a plurality of submodules are installed above one another, a semiconductor component is provided in which the semiconductor chips are located in several mutually overlying planes. The semiconductor chips can be interconnected. A method for producing a semiconductor component is also provided.

Abstract: An electronic component includes a substrate (210, 1510), a device (221, 222) supported by the substrate and including a first bond pad (223, 224, 225, 226), and a cap (231, 232, 631, 731, 732, 1531, 1532) overlying the substrate. The cap includes a second bond pad (241, 242, 243, 244) at an outside surface of the cap, a third bond pad (245, 246, 247, 248) at an inside surface of the cap and electrically coupled to the first bond pad, and an electrically conductive via (251, 252, 254, 751, 752, 753, 754) extending through the cap and electrically coupling together the second and third bond pads.

Abstract: A microelectronic package and a method of forming the same comprising a microelectronic device attached by an active surface to a substrate. A heat dissipation device having a base portion is positioned over a back surface of the microelectronic device and having at least one lip portion extending from the base portion which is attached to the substrate. An inlet extends through the heat dissipation device base portion and is positioned to be over the microelectronic device back surface. A thermal interface material is dispensed through the inlet and by capillary action is drawn between the microelectronic device back surface and the heat dissipation device base portion.

Abstract: A sealed ceramic package for a semiconductor device and a method of fabricating the same are disclosed. In one embodiment, a ceramic substrate has a set of cavities each having an opening at a substrate top surface. A semiconductor die is disposed within each cavity, and is electrically connected through the substrate to input/output terminals of the substrate. The substrate has a metal film on the top surface thereof around the opening of the respective the cavities. A metal lid panel, covering the cavity openings, is soldered to the metal film by reflowing a layer of solder disposed over a lid panel bottom surface, thereby sealing the die in each cavity. Subsequently, individual packages are singulated from the ceramic substrate.

Abstract: The present invention relates to an integrated circuit packages having a thermally conductive element thermally coupled to a heat sink and semiconductor die, and a method of manufacturing said integrated circuit package.

Abstract: A structure of a heat spreader substrate. A first heat spreader has a first upper surface, a corresponding first lower surface and an opening. A second heat spreader has a second upper surface and a corresponding second lower surface. The second heat spreader is fit tightly into the opening. The second lower surface and the first lower surface are coplanar. A thickness of the second heat spreader is smaller than that of the first heat spreader. A chip is located on the second upper surface. A substrate is located on the first upper surface of the first heat spreader, and the opening is exposed by the substrate.

Abstract: A window is mounted directly to an upper surface of a micromirror device chip. More particularly, the window is mounted above a micromirror device area on the upper surface of the micromirror device chip by a bead. The window in combination with the bead form a hermetic enclosure about the micromirror device area thus protecting the micromirror device area from moisture and contamination.

Abstract: An electronic package and a method for packaging an electronic component, particularly a shock-sensitive component such as a yaw rate sensor or an accelerometer mounted to a circuit board. The package includes a case having an opening through which the circuit board is placed within the case, so that a peripheral edge of the circuit board is adjacent but spaced apart from a wall of the case. A thixotropic gel is present in the space between the peripheral edge of the circuit board and the wall of the case, so as to separate and control the mechanical decoupling of the circuit board and case. An optional spacer can be used to space the circuit board from the shelf. Alternatively, the gel may be filled with a polymer particulate material. A potting material preferably fills an upper cavity within the case to encapsulate and secure the circuit board within the case.

Abstract: A semiconductor package having a molded body and a plurality of conductive pins that extend from the bottom of the molded body. The semiconductor package further includes a RF shield around a protected cavity that holds a first integrated circuit. The molded body can further include an unprotected plastic cavity for holding a second integrated circuit. The conductive pins form bonding pads that are used to electrically interconnect the first and second semiconductor devices to the external environment. A cover, beneficially comprised of copper, is disposed over the molded body. The plastic cavity beneficially includes a beveled wall that improves the routing of electrical conductors between the first integrated circuit and the second integrated circuit.

Abstract: A method and structure to adhesively couple a cover plate to a semiconductor device. A semiconductor device is electrically coupled to a substrate. A stiffener ring surrounding the semiconductor device is adhesively coupled to the substrate. A cover plate is adhesively coupled to both a top surface of the semiconductor device and a top surface of the stiffener ring using a first and second adhesive, respectively. The modulus of the first adhesive is less than the modulus of the second adhesive.

Abstract: A semiconductor device package is comprised of a metal base for receiving a semiconductor device, a metal frame joined at its lower face to the metal base, a seal ring joined at its lower face to an upper face of the metal frame, and a metal lid joined to an upper face of the seal ring. The upper face of the seal ring is formed, at its at least two sides facing each other, into a concavely warped shape as viewed in vertical cross section, and the maximum warpage of the upper face of the seal ring is not more than 0.2% of the length of the side of the upper face.

Abstract: A semiconductor device having: a wiring substrate; a semiconductor chip disposed thereon; and a heat radiating plate for radiating the heat generated from the semiconductor chip. A highly elastic member made of a synthetic resin is so disposed as to surround the semiconductor chip between the wiring substrate and the heat radiating plate.

Abstract: A multi-layer device with a lid, a core, and a base. The lid has a first terminal and a second terminal, and an inner surface with a first insulator. The core has a first surface bonded to the first insulator and a second surface bonded to a second insulator, and includes a pillar electrically connected to the second terminal. The base has an inner surface bonded to the second insulator and a portion being electrically connected to the pillar. The first terminal of the lid and the base are adapted for electrically connecting to an interior electrical unit positioned within the core so that there are conductive paths from the electrical unit to the first and second terminals. The lid can include a third terminal in electrical contact with a portion of the core, and the portion of the core can be adapted for electrically connecting to the electrical unit.

Abstract: A semiconductor device which includes: a semiconductor chip bonded to a surface of a solid device; and a stiffener surrounding the periphery of the semiconductor chip. A surface of the stiffener opposite from the solid device is generally flush with a surface of the semiconductor chip opposite from the solid device.

Abstract: A semiconductor device module includes one or a plurality of semiconductor devices, each including a semiconductor element having first and second surfaces, pads formed on the first surface on which electrode terminals are also formed and curved, flexible wires having first ends fixed to the pads. The semiconductor devices are mounted on a mounting board such that second ends of the wires are connected to terminals on the mounting board. A heat spreader has a recessed inner wall and a peripheral edge which is adhered to or engaged with the mounting board in such a manner that the second surfaces of the semiconductor elements face a bottom interior surface of the recessed inner wall. A thermal conductive resin layer of a substantially constant thickness is disposed between the second surface of the semiconductor element and the bottom interior surface of the recessed inner wall of the heat spreader.

Abstract: An encapsulation for a device is disclosed. Spacer particles are randomly located in the device region to prevent a cap mounted on the substrate from contacting the active components, thereby protecting them from damage. The spacer particles are fixed to one side of the substrate to prevent any movement.

Abstract: A semiconductor chip package with cooling arrangement includes a heat sink adapted for covering at least a semiconductor chip, characterized in that said heat sink has an inverted U-shaped cross section thereby forming a recess at an inner bottom thereof adapted for covering at least a semiconductor chip and a plurality of pins extending downwardly from a circumferential lower edge of said heat sink, each of said pins being formed with a neck, an enlarged head, and an open slot separating said neck and said enlarged head into two portions, whereby the package can rapidly remove heat from the semiconductor chip, filter noise and reduce inductance.

Abstract: A sealing package for an integrated circuit chip including a lead structure with first lead members and second lead members. The first lead members are located proximate the corners of the sealing package and have two lead portions external to the sealing package and one lead portion internal to the sealing package. The second lead members are fanned out along the sides of the sealing package and have one lead portion internal to the sealing package and one lead portion external to the sealing package. Each first lead member adapted to provide a connection to ground for at least two sides of the sealing package. Each second lead member adapted to provide a connection between an integrated circuit chip internal to the sealing package and external circuitry.

Abstract: A semiconductor structure includes a semiconductor substrate and a compliant interconnect element disposed on a first surface of the substrate. The compliant interconnect element defines a chamber between the first surface of the substrate and a surface of the compliant interconnect element. The compliant interconnect element can be a compliant layer. The compliant layer can be formed of a polymer, such as silicone. A conductive layer can be disposed on the compliant layer, in contact with a contact pad on the semiconductor substrate. A method for forming a semiconductor structure includes providing a semiconductor substrate and providing a compliant interconnect element on a first surface of the substrate, so that the compliant interconnect element defines a chamber between the compliant interconnect element and the first surface of the substrate.

Abstract: An apparatus and method for hermetically sealing, EMI shielding integrated circuits for high-speed electronic devices using a combination of microstrip to buried stripline interface for signal transmission from the integrated circuit. The packaging provided comprises a first plurality of microstrips interconnecting the integrated circuit to a plurality of buried striplines exposed on a surface of the main substrate. A ceramic interposer placed over the main substrate “buries” a portion of the exposed striplines on the main substrate to thereby insulate these signal paths from a hermetically sealing, and EMI shielding metal lid placed over the integrated circuit. The metal lid and the seal ring brazed over the ceramic interposer thus provide both a hermetic seal and an electric radiation block. A reduction in dispersion due to the buried striplines is also achieved, as well as improving jitter performance.

Abstract: Arrangements are used to increase the structural rigidity of a semiconductor package.

Abstract: An electronic device includes a ceramic chip carrier having an opening, a SAW element chip housed in the opening, a Kovar sealing ring, which is bonded to the ceramic chip carrier by using an Ag brazing material or other suitable material such that the Kovar sealing ring encircles the opening, and a Kovar metal cap, which is placed on the Kovar sealing ring, wherein the Kovar metal cap is coated with Ni-plating which is used as a brazing material for seam-welding and bonding the Kovar metal cap to the Kovar sealing ring and the hermeticity between the metal cap and the sealing ring increases when the thickness of the Ni-plating is about 1 &mgr;m to about 2 &mgr;m.

Abstract: In accordance with the present invention, a method is described which facilitates heat transfer from a silicon die after the silicon die is bonded to a substrate. An alignment tool is used to align the spacer with the silicon die. A thermal conductor can be placed on the silicon layer after the silicon layer has been bonded to the substrate layer. A die interface is not necessarily applied between the silicon die and the thermal conductor. A spacer is used between the substrate and the thermal conductor. The spacer can facilitate heat transfer from the die. The spacer can facilitate force transfer from the thermal lid to the die. The spacer allows a thermal conductor to be affixed to the silicon die without use of a die interface. An alignment tool is used to align the spacer with the silicon die.

Abstract: The invention relates to a semiconductor chip having a fracture sidewall (4) running at a lateral edge region, and having an electrically active layer (2) ending at the fracture sidewall, in which case at least one fracture-sidewall section which is assigned to the end of the active layer is provided with a passivation layer (10) covering said section. The invention furthermore relates to a method for fabricating such a semiconductor chip.

Abstract: In connection with a semiconductor device which adopts the face down mounting method, it is intended to provide a technique which can check the state of continuity between electrode pads formed on a semiconductor chip and electrode pads formed on a wiring substrate.

Abstract: Ultrasonically formed seals, their use in semiconductor packages, and methods of fabricating semiconductor packages. A brittle center member (such as glass) has a molded edge member. That edge member is ultrasonically welded to a body. The molded edge member and body are comprised of ultrasonically weldable materials. A hermetically sealed semiconductor package includes a lid with a brittle center plate and a molded edge. The molded edge is ultrasonically welded to a body. Locating features that enable accurate positioning of the lid relative to the body, and energy directors can be included. Pins having a relieved portion and a protruding portion can also be hermetically sealed to the body. Such pins can have various lengths that enable stadium-type pin rows. The pins can be within channels, which can hold a sealant. The body can include a device that is electrically connected to the pins.

Abstract: A vacuum sealed package for a semiconductor chip, such as a micro-electromechanical (MEM) chip, is disclosed, along with a method of making such a package. In an exemplary embodiment, the package includes a ceramic substrate and a lid that together define a cavity wherein the chip is mounted. The substrate includes a conductive (e.g., metal) interconnect pattern that extends, at least in part, vertically through the substrate. I/O terminals are provided on an external surface of the substrate. A vent hole, at least partially lined with a metal coating, extends through the substrate into the cavity. A metal plug seals the vent hole. The vent hole is sealed by placing the package in a vacuum chamber, evacuating the chamber, and heating the chamber so as to cause a metal preform on the substrate to flow into the vent hole and form the plug.

Abstract: A natural-resource-conservative, environmentally-friendly, cost-effective, leadless semiconductor packaging apparatus, having superior mechanical and electrical properties, and having an optional windowed housing which uniquely seals and provides a mechanism for viewing the internally packaged integrated semiconductor circuits (chips/die). A uniquely stamped and/or bent lead-frame is packaged by a polymeric material during a unique compression-molding process using a mold, specially contoured to avoid the common “over-packaging” problem in related art techniques. The specially contoured mold facilitates delineation of the internal portions from the external portions of the lead-frame, as the external portions are the effective solderable areas that contact pads on a printed circuit board, thereby avoiding a laborious environmentally-unfriendly masking step and de-flashing step, streamlining the device packaging process.

Abstract: An electronic device is described that has a sheet strip for packaging bonding wire connections of the electronic device and a method for producing it. To that end, the sheet strip, has at least two preformed, opposite edge regions which cover the edge regions of the bonding channel in an overlapping manner. Furthermore, the sheet strip has a preformed central region situated between the edge regions, which central region has a bulge and thickened portion and has two convexly curved contour lines in cross section.

Abstract: An electronic package and/or package lid includes at least one connection slot for receiving a line, such as an optical fiber. The package and/or package lid also includes at least one sealant slot proximate the connection slot. Optical fibers are connected to a component, such as an opto-electronic component, through the connection slot. A sealant provided via the sealant slot hermetically seals the optical fibers within the connection slot.

Abstract: A semiconductor package includes a wiring board, a semiconductor chip flip-chip bonded to the wiring board, an adhesive coated on the wiring board, a stiffener ring attached to the wiring board, and a heat spreader attached to the stiffener ring and the semiconductor chip. The stiffener ring includes-a window through which the semiconductor chip is exposed and multiple through holes. A thermal interface material (TIM) coated on the back surface of the semiconductor chip. The stiffener ring is attached to the heat spreader by portions of the adhesive squeezed onto the upper surface of the stiffener ring via the through holes, and the semiconductor chip is attached to the heat spreader by the TIM. A method for manufacturing a semiconductor package includes: flip-chip bonding a semiconductor chip to a wiring board; coating an adhesive on the wiring board; and attaching a stiffener ring to the wiring board. The stiffener ring includes a window through which the semiconductor chip is exposed and through holes.

Abstract: A semiconductor device having oppositely facing first and second sides. The semiconductor device has a support exposed at the first side of the semiconductor device, a semiconductor device mounted on the support, and a plurality of leads connected to the semiconductor device. A lead identifier on the support is visible at the first side of the semiconductor device, and assists identification of a specific lead in the plurality of leads.

Abstract: An IC (Integrated Circuit) package includes a package body having a cavity formed for receiving an IC chip therein. A terrace protrudes from at least part of the edges defining the cavity into the cavity. Discrete devices can be mounted on the terrace, i.e., inside the IC package. With this configuration, the IC package insures the stable operation of a high-frequency IC circuit.

Abstract: A photosensitive semiconductor package with a lid is proposed, in which a chip carrier is formed with an encapsulant thereon, and the encapsulant is formed with a cavity for exposing a semiconductor chip mounted on the chip carrier. A top of the encapsulant is structured with a groove and at least a beveled portion that descends toward the groove and is associated with the groove. When a lid is attached onto the encapsulant by using an adhesive, the groove can temporarily retain excess adhesive with its flow being directed toward the groove by the beveled portion, so that undersirable adhesive loss and adhesive flash can both be prevented from occurrence, allowing the appearance of the semiconductor package to be well maintained.

Abstract: AS conductive patterns 11A to 11D are formed burying in a insulating resin 10 and a conductive foil 20 is formed being half-etched, thickness of the device is made thin. As an electrode for radiation 11D is provided, a semiconductor device superior in radiation is provided.

Abstract: A semiconductor package with an embedded heat-dissipating device is proposed. The heat-dissipating device including a heat sink and a plurality of connecting bumps attached to connecting pads formed on the heat sink is mounted on a substrate by reflowing the connecting bumps to ball pads of the substrate. The connecting bumps and the ball pads help buffer a clamping force generated during the molding process, so as to prevent a packaged semiconductor chip from being cracked. Moreover, the reflowing process allows the connecting bumps to be self-aligned on the substrate, so as to assure the toning and planarity of the heat sink mounted thereon. Accordingly, during molding, the precisely-positioned beat sink can have its upper side closely abutting an upper mold, allowing a molding resin to be prevented from flashing on the upper side thereof i.e.

Abstract: In order to provide a semiconductor device which has a bonding layer capable of providing electrical continuity between the cap and the semiconductor substrate, the semiconductor device comprises a semiconductor substrate whereon an element is formed on one principal plane thereof and a cap which hermetically seals the element so that a space is formed over the element, while the element is sealed by bonding a laminated bonding layer, which is formed around the element provided on the principal plane, and an Ni layer formed on the cap, wherein the laminated bonding layer is constituted from a first polysilicon layer which is doped with an impurity, an insulation layer and a second polysilicon layer which is not doped with an impurity, while the first polysilicon layer and the second polysilicon layer contact with each other in a part thereof so that the impurity diffuses through the contact area from the first polysilicon layer into the second polysilicon layer.

Abstract: In a molding process, a hybrid integrated circuit substrate is fixed the position of the substrate in a thickness direction. A leadframe is connected, with an upward inclination, to a hybrid integrated circuit substrate and transported into a mold cavity. By horizontally fixing the leadframe by mold dies, the hybrid integrated circuit substrate inclined upward is urged downward by a pushpin. This can fix the position of the hybrid integrated circuit substrate within the mold cavity and integrally transfer-molded.