Abstract: A method of making a semiconductor chip assembly includes providing a post and a base, mounting an adhesive on the base including inserting the post through an opening in the adhesive, mounting a substrate on the adhesive including inserting the post into an aperture in the substrate, then flowing the adhesive between the post and the substrate in the aperture, solidifying the adhesive, then grinding the post and the adhesive, then mounting a semiconductor device on a heat spreader that includes the post and the base, electrically connecting the semiconductor device to the substrate and thermally connecting the semiconductor device to the heat spreader.

Abstract: A method of making a semiconductor chip assembly includes providing first and second posts, first and second adhesives, first and second conductive layers and a dielectric base, wherein the first post extends from the dielectric base in a first vertical direction into a first opening in the first adhesive and is aligned with a first aperture in the first conductive layer, the second post extends from the dielectric base in a second vertical direction into a second opening in the second adhesive and is aligned with a second aperture in the second conductive layer and the dielectric base is sandwiched between and extends laterally from the posts, then flowing the first adhesive in the first vertical direction and the second adhesive in the second vertical direction, solidifying the adhesives, then providing a conductive trace that includes a pad, a terminal and selected portions of the conductive layers, wherein the pad extends beyond the dielectric base in the first vertical direction and the terminal extends

Abstract: A package for use in encapsulating an electronic device is disclosed. The package includes a dielectric frame having first and second sides with a pair of apertures extending through the dielectric frame. These apertures are separated by a raised shelf span extending inwardly from an internal perimeter of the dielectric frame. The raised shelf span defines a first thickness of the dielectric frame and a raised sidewall extending outwardly from the second side along an external perimeter of said dielectric frame defines a second thickness of said frame, with the second thickness being greater than the first thickness. Also provided is a metallic component having a flange and a pedestal that extends perpendicularly from the flange. The flange is bonded to the first side of the dielectric frame and extends across one of the pair of apertures with the pedestal extending into that aperture. A gap between the pedestal and the dielectric frame having a width of at least 0.015 inch.

Abstract: A dual wavelength laser device including a cap, a header, a first laser chip and a second laser chip. The cap includes a cap body and a lens embedded on the cap body. The header forms an accommodating space with the cap. The first laser chip is arranged in the accommodating space and emitting a first laser beam toward the lens. The second laser chip is arranged in the accommodating space and emitting a second laser beam toward the lens.

Abstract: A package for use in encapsulating an electronic device is disclosed. In some embodiments, the package includes the following: a dielectric frame having first and second sides, an aperture, a raised shelf portion defined along an internal perimeter of the dielectric frame and extending outwardly from the second side, the raised shelf portion defining a first thickness of the dielectric frame, and a raised sidewall extending outwardly from the second side along an external perimeter of the dielectric frame, the raised sidewall defining a second thickness of the frame, the second thickness being greater than the first thickness; a metallic component bonded to the dielectric frame and extending across the aperture; and a seam weldable, low-profile metallic seal ring bonded to the raised sidewall of the dielectric frame.

Abstract: A technique to fabricate a package. A thin wafer supported by a wafer support substrate (WSS) is formed. The WSS-supported thin wafer layer is diced into a plurality of WSS-supported thin dice. A WSS-supported thin die is bonded to a first heat spreader (HS) to form a HS-reinforced thin die.

Abstract: The present invention integrates a shield on a flat, no-lead (FN) semiconductor package, which has multiple rows of contact pads along any side. The FN semiconductor package will have at least one inner row and one outer row of contact pads on at least one side. The inner and outer rows of contact pads and a die attach pad form the foundation for the FN semiconductor package. A die is mounted on the die attach pad and connected by wirebonds to certain contact pads of the inner rows of contact pads. An overmold body is formed over the die, die attach pad, wirebonds, and inner row of contact pads, and substantially encompasses each contact pad of the outer row of contact pads. A conformal coating is applied over the overmold body, including the exposed surfaces of the contact pads of the outer row of contact pads, providing a shield.

Abstract: This invention includes a heat sink structure for use in a semiconductor package that includes a ring structure with down sets and a heat sink connected to the ring structure. The down sets can be slanted or V-shaped. The invention also includes a method of manufacturing a semiconductor package that includes inserting a substrate with an attached semiconductor chip in a first mold portion, placing a heat sink structure on top of a portion of the substrate, placing a mold release film onto a second mold portion, clamping a second mold portion onto a portion of the heat sink structure, injecting an encapsulant into a mold cavity, wherein the encapsulant surrounds portions of the substrate, semiconductor chip and heat sink structure, curing the encapsulant, whereby the heat sink structure adheres to the encapsulant and singulating the encapsulated assembly to form a semiconductor package.

Abstract: According to one embodiment, a sensor-securing apparatus has a frame having a sensor-mount region to hold an image sensor that generates heat while operating. The frame has a first adhesive-applying hole and a plurality of second adhesive-applying holes. The first adhesive-applying hole opens in the sensor-mount region and faces the center part of the image sensor. The second adhesive-applying holes are smaller than the first adhesive-applying hole, open in the sensor-mount region and are arranged around the first adhesive-applying hole. Adhesive is filled in the first adhesive-applying hole and the second adhesive-applying holes. The adhesive secures the image sensor to the frame.

Abstract: According to one embodiment, a power transistor package includes an electrically conductive flange configured to be connected to a source of a power transistor device. The package further includes a first terminal mechanically fastened to the flange and configured to be electrically connected to a gate of the power transistor device and a second terminal mechanically fastened to the flange and configured to be electrically connected to a drain of the power transistor device. The package also includes a bus bar mechanically fastened to the flange which extends between and connects at least two different DC bias terminals mechanically fastened to the flange. The bus bar is configured to be electrically connected to the drain via one or more RF grounded connections.

Abstract: A premold housing for accommodating a chip structure includes a first part of the housing which is connected to the chip structure as well as connected in an elastically deflectable manner to an additional part of the housing which is fastened to the support structure bearing the entire housing. A mechanism is provided for damping the deflection of the first part of the housing which is connected to the chip structure.

Abstract: Packaged microelectronic elements are provided. In an exemplary embodiment, a microelectronic element having a front face and a plurality of peripheral edges bounding the front face has a device region at the front face and a contact region with a plurality of exposed contacts adjacent to at least one of the peripheral edges. The packaged element may include a plurality of support walls overlying the front face of the microelectronic element such that a lid can be mounted to the support walls above the microelectronic element. For example, the lid may have an inner surface confronting the front face. In a particular embodiment, some of the contacts can be exposed beyond edges of the lid.

Abstract: A composite multi-layer substrate comprising a flat plate-like core member formed of a material having an excellent electric conductivity, an excellent heat conductivity, and a high rigidity, a front resin layer and a rear resin layer covering at least the front and rear surfaces of the core member, and a bottomless hole formed in the core member through the front and rear sides of the core member, wherein an electronic component is installed in the bottomless hole, whereby since the strength of the composite multi-layer substrate can be assured by the rigidity of the core member, conventional prior art glass cloth can be eliminated, deterioration in the electric characteristics caused by ion migration can be avoided and will result in reduced production cost.

Abstract: An electronic circuit arrangement includes a heat sink and a first circuit carrier which is thermally coupled to the heat sink, lies flat on the latter and is intended to wire electronic components of the circuit arrangement. Provided for at least one electronic component is a special arrangement which is associated with a considerably increased heat dissipation capability for the relevant component and, in addition, also affords further advantages in connection with changes in the population and/or line routing which might occur in practice. The important factor for this is that the component is arranged under a second circuit carrier which is held in a recess in the first circuit carrier. The recess passes through to the top side of the heat sink.

Abstract: A method and apparatus for packaging semiconductor dies for increased thermal conductivity and simpler fabrication when compared to conventional semiconductor packaging techniques are provided. The packaging techniques described herein may be suitable for various semiconductor devices, such as light-emitting diodes (LEDs), central processing units (CPUs), graphics processing units (GPUs), microcontroller units (MCUs), and digital signal processors (DSPs). For some embodiments, the package includes a ceramic substrate having an upper cavity with one or more semiconductor dies disposed therein and having a lower cavity with one or more metal layers deposited therein to dissipate heat away from the semiconductor dies. For other embodiments, the package includes a ceramic substrate having an upper cavity with one or more semiconductor dies disposed therein and having a lower surface with one or more metal layers deposited thereon for efficient heat dissipation.

Abstract: A semiconductor package with enhanced mobility of ball terminals is revealed. A chip is attached to the substrate by a die-attaching material where the substrate has at least a stepwise depression on the covered surface to make the substrate thickness be stepwise decreased from a central line of the die-attaching area toward two opposing sides of the substrate. The die-attaching material is filled in the stepwise depression. Therefore, the thickness of the die-attaching material under cross-sectional corner(s) of the chip becomes thicker so that a row of the ball terminals away from the central line of the die-attaching area can have greater mobility without changing the appearance, dimensions, thicknesses of the semiconductor package, nor the placing plane of the ball terminals. Accordingly, the row of ball terminals located adjacent the edges or corners of the semiconductor package can withstand larger stresses without ball cracks nor ball drop.

Abstract: The semiconductor device includes a substrate, a first semiconductor element, a second semiconductor element, a first heat sink and a second heat sink. The first and the second semiconductor elements are provided on the substrate. The maximum power consumption of the first semiconductor element is lower than that of the second semiconductor element. The first heat sink is fixed to the first semiconductor element. The second heat sink is fixed to the second semiconductor element. The first heat sink is spaced apart from the second heat sink.

Abstract: A ball grid array package system comprising: forming a package base including: fabricating a heat spreader having an access port, attaching an integrated circuit die to the heat spreader, mounting a substrate around the integrated circuit die, and coupling an electrical interconnect between the integrated circuit die and the substrate; and coupling a second integrated circuit package to the substrate through the access port.

Abstract: A package structure includes a substrate; a die over and flip bonded on the substrate; a heat sink over the die; and one or more spacer separating the heat sink from the substrate.

Abstract: The invention provides a heat radiating structure which reduces a mechanical stress applied to an electronic part mounted on a printed circuit board including a semiconductor package. The heat radiating structure is constructed by a semiconductor package mounted on a printed circuit board, a thermal conduction sheet arranged on an upper surface of the semiconductor package, and a metal case provided with a heat radiating fin for receiving a heat transmitted form the thermal conduction sheet so as to discharge to an atmospheric air, and the metal case is provided with a concavo-convex structure in a contact portion with the thermal conduction sheet.

Abstract: A lead frame with downset baffle paddles and a semiconductor package utilizing the same are revealed. The lead frame primarily comprises a plurality of leads formed on a first plane, a baffle paddle formed on a second plane in parallel, and an internal tie bar formed between the first plane and the second plane. The internal tie bar has at least two or more windings such as “S” shaped to flexibly connect the baffle paddle to an adjacent one of the leads. Therefore, the internal tie bar can reduce the shifting and twisting of the connected lead during the formation of the downset of the baffle paddle.

Abstract: A composite multi-layer substrate comprising a flat plate-like core member formed of a material having an excellent electric conductivity, an excellent heat conductivity, and a high rigidity, a front resin layer and a rear resin layer covering at least the front and rear surfaces of the core member, and a bottomless hole formed in the core member through the front and rear sides of the core member, wherein an electronic component is installed in the bottomless hole, whereby since the strength of the composite multi-layer substrate can be assured by the rigidity of the core member, conventional prior art glass cloth can be eliminated, deterioration in the electric characteristics caused by ion migration can be avoided and will result in reduced production cost.

Abstract: A process for fabricating a cavity-type integrated circuit includes supporting a leadframe strip in a mold. The leadframe strip includes a die attach pad and a row of contact pads circumscribing the die attach pad. A package body is molded in the mold such that opposing surfaces of the die attach pad and of the contact pads are exposed. A semiconductor die is mounted to the die attach pad. Various ones of the contact pads are wire bonded to the semiconductor die and a lid is mounted on the package body to thereby enclose the semiconductor die and the wire bonds in a cavity of the integrated circuit package.

Abstract: A power module with low thermal resistance buffers the stress put on a substrate during a package molding operation to virtually always prevent a fault in the substrate of the module. The power module includes a substrate, a conductive adhesive layer formed on the substrate, a device layer comprising a support tab, a power device, and a passive device which are formed on the conductive adhesive layer, and a sealing material hermetically sealing the device layer. The support tab is buffers the stress applied by a support pin to the substrate, thereby virtually always preventing a ceramic layer included in the substrate from cracking or breaking. As a result, a reduction in the isolation breakdown voltage of the substrate is virtually always prevented and the failure of the entire power module is do to a reduction in the breakdown voltage of the substrate is virtually always prevented.

Abstract: A semiconductor switching module includes a power semiconductor element that is embodied in planar technology. In at least one embodiment, the power semiconductor element is provided with a base layer, a copper layer, and at least one power semiconductor chip that is mounted on the copper layer, and another electrically conducting layer which covers at least one load terminal of the power semiconductor chip. According to at least one embodiment of the invention, devices are provided for safely connecting the load terminal to a load circuit. The devices are configured such that a contact area thereof presses in a planar manner onto the electrically conducting layer.

Abstract: An apparatus, method, and system for providing a mechanical divider adapted to shield at least a portion of an active surface of an integrated circuit from out-gassing from underfill material. The mechanical divider is attached to a mounting substrate. The underfill material is dispensed on the mounting substrate. The integrated circuit is placed on both the mechanical divider and on the underfill material after the mechanical divider has been at least partially cured. The mechanical divider may include a base surface adapted to contact the mounting substrate, a lower wall surface extending upwardly from the base surface, an upper wall surface adapted to abut a side wall of the integrated circuit, and a ledge surface extending between the lower wall surface and the upper wall surface, the ledge surface adapted to contact at least a portion of the active surface of the integrated circuit.

Abstract: Disclosed is a printed circuit board (PCB) comprising at least one light emitting diode (LED) element and a PCB body. The LED comprises a heat sink, a light emitting body and two base feet, each base foot comprising a support portion for supporting the light emitting body, an engaging portion and a connecting portion for connecting the support portion to the engaging portion, and the heat sink is disposed under the support portion. The PCB body comprises a first recess portion for disposing the heat sink to increase heat dissipation of the heat sink and two second recess portions for receiving the engaging portions of the base feet to increase heat dissipation of the base feet.

Abstract: A power semiconductor module having an integral circuit board with a metal substrate electrode, an insulation substrate and a heat sink joined is disclosed. A SiC semiconductor power device is joined to a top of the metal substrate electrode of the circuit board. A difference in average coefficients of thermal expansion between constituent materials of the circuit board in a temperature range from room to joining time temperatures is 2.0 ppm/° C. or less, and a difference in expansion, produced by a difference between a lowest operating temperature and a joining temperature, of the circuit-board constituent materials is 2,000 ppm or less.

Abstract: A package for a semiconductor chip or other heat producing device has a supporting substrate to which the devices mount and electrically connect. An enclosure is formed over the heat producing devices and filled with a supercritical fluid that transports heat from the devices to a heat sink in thermal contact with the enclosure.

Abstract: In some embodiments, an alternative to desmear for build-up roughening and copper adhesion promotion is presented. In this regard, a substrate in introduced having a dielectric layer, a plurality of polyelectrolyte multilayers on the dielectric layer, and a copper plating layer on the polyelectrolyte multilayers. Other embodiments are also disclosed and claimed.

Abstract: Various integrated circuit packages, lids therefor and methods of making the same are provided. In one aspect, a method of manufacturing is provided that includes providing an integrated circuit package lid that has a surface adapted to face towards an integrated circuit, and forming a wetting film on the surface. The wetting film has at least one void where the surface of the lid is exposed. The void inhibits bonding so that a stress reduction site is produced.

Abstract: A multi-lid semiconductor package includes one or more die disposed on a substrate, an interconnect disposed on the substrate, one or more die lids, a die thermal interface between the one or more die and the corresponding die lid or lids, one or more substrate lids, and a substrate interface between the substrate and the corresponding substrate lid or lids. The multi-lid semiconductor package may include one or more discrete surface mount components disposed on the substrate. The multi-lid semiconductor package may include a sealant between the one or more die lids and the one or more substrate lids and the substrate. The one or more die lids and the one or more substrate lids may differ in construction, design, placement, and/or thermal performance.

Abstract: A compound heat sink for the removal of thermal energy useful for, inter alia, electronic devices or other components. The compound heat sink includes a die cast base element; an extruded dissipation element having a thermal conductivity of at least about 150 W/m-K; and a thermal connection material positioned between and in thermal contact with each of the base element and the dissipation element, wherein the thermal connection material having an in-plane thermal conductivity greater than the thermal conductivity of the dissipation element.

Abstract: A thin semiconductor device difficult to cause breakage of a semiconductor chip is disclosed.

Abstract: Disconnection and deterioration in step coverage of wirings are prevented to offer a semiconductor device having higher reliability. A pad electrode is formed on a surface of a silicon die. A via hole penetrating the silicon die is formed from a back surface of the silicon die to the pad electrode. A wiring layer disposed on the back surface of the silicon die runs through the via hole and is electrically connected with the pad electrode. The wiring layer covers a convex portion of silicon on the back surface of the silicon die. A solder ball is formed on the wiring layer on the convex portion of silicon.

Abstract: An assembly structure of an electronic element and a heat sink is disclosed. An assembly structure of an electronic element and a heat sink comprises a fastening element, an electronic element having a first through hole, and an insulating piece having a second through hole, an insulating element disposed in the first through hole of the electronic element and having a channel therein, and a heat sink. The second through hole is disposed correspondingly to the first through hole of the electronic element, the electronic element and the insulating piece are secured on the heat sink by inserting the fastening element through the channel of the insulating element, so as to insulate the electronic element from the heat sink by the insulating element.

Abstract: Systems and methods for forming an encapsulated device include a hermetic seal which seals an insulating environment between two substrates, one of which supports the device. The hermetic seal is formed by an alloy of two metal layers, one deposited on a first substrate and the other deposited on the second substrate, along with a raised feature formed on the first or the second substrate. At least one of the metal layers may be deposited conformally over the raised feature. The raised feature penetrates the molten material of the first or the second metal layers during formation of the alloy, and produces a spectrum of stoichiometries for the formation of the desired alloy, as a function of the distance from the raised feature. At some distance from the raised feature, the proper ratio of the first metal to the second metal exists to form an alloy of the preferred stoichiometry.

Abstract: A power semiconductor module according to the present invention includes: a planar base plate having a plurality of insulated substrates soldered on the top surface, the insulated substrates each having power semiconductor elements to be cooled mounted thereon; a plurality of radiation fins projecting from the bottom surface side of the base plate; and a peripheral wall projecting from the bottom surface side of the base plate so as to surround the radiation fins, the projecting length of the radiation fins is less than or equal to that of the peripheral wall, and the peripheral wall has end surfaces present in the same plane.

Abstract: A semiconductor package having improved adhesiveness between the chip paddle and the package body and having improved ground-bonding of the chip paddle. A plurality of through-holes are formed in the chip paddle for increasing the bonding strength of encapsulation material in the package body. A plurality of tabs are formed in the chip paddle may also be used alone or in conjunction with the through-holes to further increase the bonding strength of the encapsulation material in the package body. The tabs provide additional area for the bonding site to ground wires from the semiconductor chip by increasing the length of the chip paddle.

Abstract: Integrated circuit chip cooling methods and systems are disclosed. A method for cooling an integrated circuit chip may comprise: providing a cooling mechanism; positioning an interface medium between the cooling mechanism and the integrated circuit chip; and interfacing the cooling mechanism and the integrated circuit chip through the interface medium; wherein at least one of the cooling mechanism, the integrated circuit chip, or the interface medium includes a convex portion on an interface surface thereof.

Abstract: A semiconductor device includes: a substrate; a semiconductor element mounted on the substrate; a sealing structure for sealing the semiconductor element, the sealing structure being mounted on the substrate; and an adhesive for bonding the sealing structure and the substrate, wherein the sealing structure has a groove for storing the adhesive.

Abstract: An apparatus comprises a plurality of logically independent processors, a system bus, and a cache control and bus bridge device in communication with the plurality of processors such that the cache control and bus bridge device is logically interposed between the processors and the system bus, and wherein the processors and cache control and bus bridge device are disposed in a module form factor such that the apparatus is a drop-in replacement for a standard single processor module.

Abstract: A semiconductor package substrate with embedded chip and a fabrication method thereof are provided. A first insulating layer is applied on a metallic board, and formed with at least one opening for exposing a portion of the metallic board. At least one semiconductor chip is mounted on the exposed portion of the metallic board. A support plate is mounted on the first insulating layer, and formed with a through cavity at a position corresponding to the opening of the first insulating layer, for receiving the chip in the through cavity. A second insulating layer is applied on the chip and the support plate. Insulating materials of the insulating layers fill a gap between the chip and the support plate. A circuit layer is formed on the second insulating layer, wherein the circuit layer is electrically connected to the chip by conductive structures formed in the second insulating layer.

Abstract: An electronic device is provided using wiring comprising aluminum to prevent hillock or whisker from generating, wherein the wiring contains oxygen atoms at a concentration of 8×1018 atoms·cm?3 or less, carbon atoms at a concentration of 5×1018 atoms·cm?3 or less, and nitrogen atoms at a concentration of 7×1017 atoms·cm?3 or less; furthermore, a silicon nitride film is formed on the aluminum gate, and an anodic oxide film is formed on the side planes thereof.

Abstract: A semiconductor device includes a first surface faced to a mounting board when the semiconductor device is placed over the mounting board and a second surface opposed to the first surface. The semiconductor device also includes a position reference portion which is provided in an area including sides of the second surface and which has an optical reflection factor different from that of the mounting board.

Abstract: A stiffener molded to a semiconductor substrate, such as a lead frame, and methods of molding the stiffener to the substrate are provided. The stiffener is molded to the substrate to provide rigidity and support to the substrate. The stiffener material can comprise a polymeric material molded to the substrate by a molding technique such as transfer molding, injection molding, and spray molding, or using an encapsulating material. One or more dies, chips, or other semiconductor or microelectronic devices can be disposed on the substrate to form a die assembly. The stiffener can be molded to a substrate comprising one or more dies, over which an encapsulating material can be applied to produce a semiconductor die package.

Abstract: A semiconductor package and a fabrication method thereof are provided in which a dielectric material layer formed with a plurality of openings is used and a solder material is applied into each of the openings. A first copper layer and a second copper layer are in turn deposited over the dielectric material layer and solder materials, and the first and second copper layers are patterned to form a plurality of conductive traces each of which has a terminal coated with a metal layer. A chip is mounted on the conductive traces and electrically connected to the terminals by bonding wires, with the dielectric material layer and solder materials being exposed to the outside. This package structure can flexibly arrange the conductive traces and effectively shorten the bonding wires, thereby improve trace routability and quality of electrical connection for the semiconductor package.

Abstract: A hermetically sealed package includes: a first plate including inside and outside surfaces; a second plate including inside and outside surfaces; frit material disposed on the inside surface of the second plate; and at least one dielectric layer disposed directly or indirectly on at least one of: (i) the inside surface of the first plate at least opposite to the frit material, and (ii) the inside surface of the second plate at least directly or indirectly on the frit material, wherein the frit material forms a hermetic seal against the dielectric layer in response to heating.

Abstract: A plasma display module, which can effectively dissipate heat, is disclosed. In one embodiment, the plasma display module includes i) a plasma display panel that displays images using gas discharge, ii) a chassis located on one surface of the plasma display panel to support the plasma display panel and iii) a driving circuit unit which is located on a surface of the chassis opposite to the plasma display panel to generate electrical signals for driving the plasma display panel, and includes at least one integrated circuit, wherein the chassis includes at least one convex unit, and the at least one integrated circuit is located on the convex unit of the chassis.

Abstract: A chip scale package has a semiconductor MOSFET die which has a top electrode surface covered with a layer of a photosensitive liquid epoxy which is photolithographically patterned to expose portions of the electrode surface and to act as a passivation layer and as a solder mask. A solderable contact layer is then formed over the passivation layer. The individual die are mounted drain side down in a metal clip or can with the drain electrode disposed coplanar with a flange extending from the can bottom. The metal clip or drain clip has a plurality, a parallel spaced fins extending from its outwardly facing surface.