Abstract: A semiconductor chip package having a non-planar chip therein, to reduce the stress concentrations between the chip and cover plate. In particular, a chip and method of forming a chip having a non-planar or “domed” back surface, wherein the thickness of the non-planar chip is greatest substantially near the center of the chip. Further, a method of rounding the edges or corners of the chip to reduce crack propagation originating at the edges of the chip.

Abstract: A semiconductor plastic package excellent in heat diffusibility and free of moisture absorption, is structured by fixing a semiconductor chip on one surface of a printed circuit board, connecting a semiconductor circuit conductor to a signal propagation circuit conductor formed on a printed circuit board surface in the vicinity thereof by wire bonding, at least connecting the signal propagation circuit conductor on the printed circuit board surface to a signal propagation circuit conductor formed on the other surface of the printed circuit board or a connecting conductor pad of a solder ball with a through-hole conductor, and encapsulating the semiconductor chip with a resin. The printed circuit board has a metal sheet of nearly the same size as the printed circuit board and is nearly in the center in the thickness direction of the printed circuit board.

Abstract: A semiconductor chip module and forming method is provided. The module includes a support member having at least one well being open to receive a semiconductor chip. Each well depth is substantially equal to the thickness of a chip. The support member has a planar region surrounding each well. A chip is in each well. A dielectric sheet of material is laminated over each chip and extends onto the planar area surrounding the wells and has a face oriented away from the chip. Electrical circuitry including capture pads is formed on the face of the dielectric sheet and extends onto the sheet that overlies the planar region. Conducting vias are formed in the dielectric sheet connecting the electrical circuitry on the dielectric sheet with the contact pads on the chip. A multilayer, circuitized laminate having a fan-out pattern is laminated to the dielectric sheet.

Abstract: A high density interconnect device which creates a thin, electrically and thermally high performance package for semiconductor devices having a mechanically stable and high thermal conductivity substrate. Cavities in the substrate accommodate semiconductor devices attached directly to the substrate. The semiconductor devices include at least one optical receiver and/or transmitter. A thin film overlay having multiple layers interconnects the semiconductor devices to an array of pads on a surface of the thin film overlay facing away from the substrate. Connectors are attached to the pads to provide direct electrical and mechanical attachment to other system hardware. In one embodiment, the optical receiver and/or transmitter receives and/or transmits light signals through the thin film overlay. In another embodiment, the optical receiver and/or transmitter receives and/or transmits light signals through holes formed through the thin film overlay. The holes may be back filled with an optical quality material.

Abstract: In order to manufacture a stem in a semiconductor laser device from a thin sheet metal by a pressing operation, a base is formed with an annular wall by pressing the thin sheet metal. Outer leads are disposed in a space which is formed within the annular wall. The leads are fixed by charging and curing an insulating thermosetting resin. A mounting for mounting a silicon sub-mount on said base is formed integrally with said base by a pressing operation. Lacking of strength and heat dissipation due to the fact that the stem is formed of a thin metal plate is compensated for by the formation of said continuous wall.

Abstract: A modular semiconductor die package is provided. The semiconductor die package includes a polymer base for mounting at least one semiconductor die. A polymer cap is operatively secured over the base forming a cavity. The cap includes a light transmissive member operatively positioned to allow light of predetermined wavelengths to pass between at least a portion of the surface of the die and the light transmissive member. A plurality of conductive leads extend through the base to form connections with the semiconductor die(s) positioned in the cavity.

Abstract: The present invention relates to a manufacturing method of a semiconductor device having a lid implemented on a semiconductor chip. The semiconductor device and the semiconductor device unit are capable of maintaining high thermal dissipation efficiency as well as the semiconductor chip having improved reliability. Specifically, upon manufacturing the above semiconductor device having a semiconductor chip mounted on a substrate and a lid thermally connected to this semiconductor chip, a stiffener, which controls the deformation of the semiconductor chip, is implemented on the side of the semiconductor chip that accommodates the lid; after which heating is performed so as to bond the semiconductor chip accommodating the stiffener to the substrate; followed by the bonding of the lid to the stiffener.

Abstract: A source electrode, a gate electrode, and a drain electrode formed on a front face active region of a semiconductor substrate in a shape of teeth of a comb are covered with an insulating film such as polyimede etc., as well as all of the upper surface and the side surfaces of the insulating film are covered with a metal protective film. Via hole receiving pads connected to the source electrode, the gate electrode, and the drain electrode are respectively connected to bonding pads on a reveres face of the semiconductor substrate through via holes.

Abstract: An object of the present invention is forming a concave portion (including a penetration hole) in a semiconductor substrate by a sandblast method without causing electrostatic breakdown. In order to achieve the object, in a wafer in which at least two chips are formed, metal films are formed at least in the vicinity of circumferential portions of regions in which the concave portions (including penetration holes) of the respective chips are to be formed. In addition, the metal films are extended from the vicinity of the circumferential portions to ends of the respective corresponding chips. Further, the metal films are connected with each other through regions between the chips. The entire surface of the wafer including the metal films is masked, except for the regions in which the concave portions of the respective chips are to be formed. At least a portion of the metal films is grounded and then the concave portions are formed in the respective chips formed on the wafer by the sandblast method.

Abstract: A MEMS product, particularly an optical MEMS product, and seal therefor. A housing member forms a cavity; a MEMS device is disposed in the cavity; a cap member (which may be an optical window) is dimensioned and configured to substantially cover the cavity; and a sealing member is sealingly attached to and between the housing member and the cap member. The sealing member may have a first attachment portion operatively attached by a first hermetic seal to the housing member and a second attachment portion operatively attached to the cap member by a second hermetic seal and the sealing member is impermeable to gas flow, whereby the cavity is hermetically sealed from ambient atmosphere external to the product.

Abstract: An IC chip package is constructed to comprise a substrate, a chip, adhesive means, and a cover. The substrate comprises a top side and a receiving chamber, the receiving chamber having an opening disposed in the top side. The top side of the substrate is provided with a plurality of connecting pads arranged around the opening of the receiving chamber. The chip is fixedly mounted in the receiving chamber and is provided with a plurality of connecting pads respectively electrically connected to the connecting pads of the substrate by means of bonding wires. The adhesive means is applied on the connecting area between the bonding wires and the connecting pads of the substrate. The cover is fixedly fastened to the adhesive means to close the opening of the receiving chamber.

Abstract: A structure of a heat spreader substrate. A first heat spreader has a first upper surface, a corresponding first lower surface and an opening. A second heat spreader has a second upper surface and a corresponding second lower surface. The second heat spreader is fit tightly into the opening. The second lower surface and the first lower surface are coplanar. A thickness of the second heat spreader is smaller than that of the first heat spreader. A chip is located on the second upper surface. A substrate is located on the first upper surface of the first heat spreader, and the opening is exposed by the substrate.

Abstract: In one embodiment, a heat sink apparatus that provides electrical isolation for an integrally shielded, electronic circuit. The heat sink apparatus comprises a substrate having a first hole extending between a first and second sides of the substrate, a conductive layer attached to the second side, an electrically and thermally conductive heat sink having a protrusion, wherein the heat sink is attached to the first side of the substrate, and an electrically conductive plate having a second hole extending through the plate. The protrusion extends through the first hole and has a surface located at substantially the same level as that of the conductive layer. An electronic component is attachable to the protrusion surface. The plate is electrically coupled to the conductive layer and to the protrusion surface such that open space between the protrusion and the conductive layer is covered by electrically conducting area of the plate.

Abstract: Electronic equipment is composed of a circuit board with a surface-printed circuit layer, an electronic part with a terminal, an under-fill provided between the electronic part and the surface-printed circuit layer. The terminal is electrically connected to the surface-printed circuit layer so that the electronic part is mounted on the circuit boarding an area, in which the circuit board faces the bottom face of the electronic part except for the terminal. The under-fill directly contacts the electronic part and the surface-printed circuit layer so that the under-fill fixes the electronic part to the circuit board.

Abstract: Suspended semiconductor packages and methods of fabricating such semiconductor packages are disclosed. An embodiment of a suspended semiconductor package comprised of at least a bridging element having at least an upper surface and a lower surface; at least a chip having a first surface and a second surface, wherein at least a surface is the active surface, with at least a portion of the active surface conjoined to the bridging element lower surface; at least a foundational element having at least an upper surface and at least a lower surface, the foundational element being situated around the chip; and at least a conductive element electrically connecting the chip to the foundational element.

Abstract: A semiconductor device provided with one or more semiconductor pellets arranged on the bottom surface of a recess produced along a surface of a semiconductor plate having wirings arranged on the surface thereof, wirings extending toward the surface of the recess, and the recess being buried with a layer of a resin which is inclined to inflate, while it is hardened, resultantly producing a stress in the resin layer to expand toward the side wall of the recess engraved in the semiconductor plate, resultantly preventing breakage from happening for an interface between the side wall of the recess engraved in the semiconductor plate and the surface of the resin layer contacting the side wall, and remarkably improving the thermal conductivity efficiency to reduce the magnitude of a temperature rise of the semiconductor device, resultantly preventing a delay from happening for the operation speed of the semiconductor device.

Abstract: A structure and method of mounting semiconductor devices which can cope with miniaturization and high-speed transmission by embedding a semiconductor device within a wiring layer or transmission path formed between opposite sides of a substrate even when a plurality of semiconductor devices are mounted on the substrate. A semiconductor device is interposed between wiring layers or transmission paths formed on opposite sides of a substrate, thereby shortening the distance between the wiring layers and rendering a structural body compact oerall. As a result of shortening of the distance between the wiring layers, the electrical resistance value of the structural body can also be diminished. Consequently, the electrical characteristic of the mount structural body can be improved, and high-speed transmission becomes feasible. Alternatively, a semiconductor device is cylindrically formed so as to enclose a conductive wire, thereby realizing a high electrical characteristic.

Abstract: A flexible chip carrier with contact pads on its upper surface matching those of the chip with said pads conductively connected to land grid array (LGA) pads on its lower surface matching the those of a card or PCB. The chip carrier is provided with a stiffening layer at the LGA interface. The stiffening layer is mechanically attached to the lower surface of the chip carrier. Holes are formed in the stiffening layer to expose the LGA pads. The holes are then filled with a conductive adhesive material. Compliant LGA bumps are applied to the uncured conductive adhesive material which material is then cured.

Abstract: A mold (1) for a semiconductor chip (9) has two mold halves (2, 3). One mold half (3) includes sealing means (10) adapted to exert a sealing pressure between a surface of the mold and a surface (18) of a substrate (8) located in the mold (1) during a molding operation.

Abstract: An integrated circuit package manufacturing process is described which reduces or eliminates the formation of voids in a molding compound between a die and an underlying substrate. The process includes providing the substrate, which has an upper surface and an air space above the upper surface. Electrically conductive vias are formed through the upper surface of the substrate which extend at least partially through the substrate, and fluid communication is provided between the vias and the overlying air space. The process includes attaching the integrated circuit die to the upper surface of the substrate over at least a portion of the vias, while leaving a gap between the die and the upper surface of the substrate. The process further includes flowing the molding compound into the gap between the die and the upper surface of the substrate while maintaining fluid communication between the vias and the air space.

Abstract: A hermetically sealed wafer scale package for micro-electrical-mechanical systems devices. The package consists of a substrate wafer which contains a microstructure and a cap wafer which contains other circuitry and electrical connectors to connect to external applications. The wafers are bonded together, and the microstructure sealed, with a sealant, which in the preferred embodiment is frit glass. The wafers are electrically connected by a wire bond, which is protected by an overmold. Electrical connectors are applied to the cap wafer, which are electrically linked to the outputs and inputs of the microstructure. The final package is small, easy to manufacture and test, and more cost efficient than current hermetically sealed microstructure packages.

Abstract: A lead frame includes a die pad including a die pad main portion having a large thickness and a die pad peripheral portion having an intermediate thickness smaller than that of the die pad main portion, provided on at least one side of the die pad main portion, at least one support lead connected to the die pad, and at least two first inner leads having a small thickness smaller than that of the die pad peripheral portion, arranged such that end portions thereof are opposed to the die pad peripheral portion. The thick die pad provides good heat release properties, and reducing the thickness of the leads allows fine pitched leads to be produced. Such a lead frame can be manufactured easily by press stamping after belt-shaped regions having different thickness are formed by rolling.

Abstract: A semiconductor clamped-stack assembly (32) has at least two clamped stacks, each of these clamped stacks having a plurality of power semiconductor components (8) and a plurality of heat sinks (6), which are arranged in series along a horizontally extending axial direction (A). According to the invention, power semiconductor components (8) from different clamped stacks are assigned to one another and are located in a common mounting plane, which is perpendicular to the axial directions (A) of the clamped stacks (31). Mutually associated power semiconductor components (8) can be removed from the clamped-stack assembly or, respectively, inserted into the clamped-stack assembly in a common mounting direction, which lies in the mounting plane. Mutually associated power semiconductor components (8) are preferably mounted on a common plate (14). As a result, they can be dismantled when the clamped-stack assembly (32) is loosened, without further power semiconductor components or heat sinks having to be dismantled.

Abstract: A metal base substrate for mounting a plurality of bare semiconductor chip devices thereon has first and second main surfaces. The first main surface has formed thereon at least one projection, and at least two recesses in which the bare semiconductor chip devices are to be mounted. The depth of these recesses is smaller than the length of said projection, and the recesses have a higher surface smoothness than said main surfaces of said metal substrate. The metal base substrate is partially chemically etched to form the projection, and the first main surface of the substrate is mechanically worked to form at least the recesses. The conductive projection is isolated from the portion on which the bare semiconductor chip devices are mounted, of the base substrate, and the conductive projection acts as a terminal that can be electrically connected to the outside on the first and second main surfaces of the base substrate.

Abstract: A sealed symmetric multilayered package with integral windows for housing one or more microelectronic devices. The devices can be a semiconductor chip, a CCD chip, a CMOS chip, a VCSEL chip, a laser diode, a MEMS device, or a IMEMS device. The multilayered package can be formed of a low-temperature cofired ceramic (LTCC) or high-temperature cofired ceramic (HTCC) multilayer processes with the windows being simultaneously joined (e.g. cofired) to the package body during LTCC or HTCC processing. The microelectronic devices can be flip-chip bonded and oriented so that the light-sensitive sides are optically accessible through the windows. The result is a compact, low-profile, sealed symmetric package, having integral windows that can be hermetically-sealed.

Abstract: A semiconductor device exhibiting a lower incidence of burrs forming on its contacts during the singulation process. The semiconductor device includes a die which is electrically connected to a set of contacts wherein each contact has a contact surface and a non-contact surface. Each contact surface of the contacts contains a recessed region filled with a first deposit of molding material. The die and the non-contact surfaces of the contacts are encapsulated with a second deposit of molding material. The semiconductor device is singulated from a molded lead frame by guiding a saw blade through recessed regions formed on the contact surface of the contacts. The molding material in the recessed regions creates a “buffer zone” which separates the path of the saw blade from the contact surface of the contacts.

Abstract: A power device compatible with an SOT 227 package standard. The device includes a substrate including a first conductive layer, a second dielectric layer, and a third conductive layer. The first conductive layer is bonded to the second dielectric layer, and the second dielectric layer is bonded to the third conductive layer. The first and third conductive layers are electrically isolated from each other. The first conductive layer has been patterned to provide at least first and second conductive blocks. A semiconductor die is bonded to the first block of the first conductive layer of the substrate. A terminal lead is coupled to the second block of the first conductive layer of the substrate.

Abstract: The present invention relates to a capsule (1) for at least one high power transistor chip (17) for high frequencies, comprising an electrically and thermally conductive flange (10), at least two electrically insulating substrates (15), and at least two electrical connections (16), and a cover member, where the high power transistor chip (17) is arranged on the flange (10). The high power transistor chip (17) and the electrically insulating substrates (15) are arranged on the flange (10). The electrical connections (16) are arranged on electrically insulating substrates (15) and the electrically insulating substrates (15) are connected to the flange (10) and open and separate from the high power transistor chip (17).

Abstract: A semiconductor device having a molded sealing resin for sealing a semiconductor chip on a circuit board thereof reduces resin burrs resulting from the leakage of the sealing resin, and also restrains the occurrence of disconnection caused by a wiring layer being crushed. In the semiconductor device, the sealing resin for sealing the semiconductor chip is molded on the circuit board that has a plurality of wiring patterns and a solder resist for insulatively covering the wiring patterns formed on the front surface thereof, the interval of the wiring patterns is set to range from 50% to 200% of its adjacent interval in a molding line area of the sealing resin. When the sealing resin is molded, among the plurality of wiring patterns, a gap will not be produced between the circuit board and a metal mold abutted against the front surface of the circuit board.

Abstract: A hermetically sealed wafer scale package for micro-electrical-mechanical systems devices. The package consists of a substrate wafer which contains a microstructure and a cap wafer which contains other circuitry and electrical connectors to connect to external applications. The wafers are bonded together, and the microstructure sealed, with a sealant, which in the preferred embodiment is frit glass. The wafers are electrically connected by a wire bond, which is protected by an overmold. Electrical connectors are applied to the cap wafer, which are electrically linked to the outputs and inputs of the microstructure. The final package is small, easy to manufacture and test, and more cost efficient than current hermetically sealed microstructure packages.

Abstract: An LDMOS power package includes a mounting substrate having a surface with one or more alignment pedestals extending therefrom. Each alignment pedestal has a mounting surface facing away from the substrate surface to provide for uniform positioning of various semiconductor elements, e.g., a transistor die or impedance matching capacitors, relative to the substrate surface. The respective pedestal mounting surfaces are preferably conductive, and are electrically coupled to the flange surface, so as to electrically couple the respective capacitor and electrode ground terminals to the flange.

Abstract: A packaged semiconductor device having high reliability that allows for a large number of pins and that provides good heat removal properties, and that can discharge the high pressure moisture in a gas state from the inside thereof to the exterior. The device includes a strengthening ring arranged around a semiconductor chip that includes a process type electrode and that is mounted on an isolated substrate; a resin to fill spaces between the semiconductor chip and the isolated substrate; and a cap on the semiconductor chip and the strengthening ring, wherein at least one vent is formed perpendicular to the direction of the thickness of the semiconductor chip.

Abstract: A semiconductor plastic package excellent in heat diffusibility and free of moisture absorption, is structured by fixing a semiconductor chip on one surface of a printed circuit board, connecting a semiconductor circuit conductor to a signal propagation circuit conductor formed on a printed circuit board surface in the vicinity thereof by wire bonding, at least connecting the signal propagation circuit conductor on the printed circuit board surface to a signal propagation circuit conductor formed on the other surface of the printed circuit board or a connecting conductor pad of a solder ball with a through-hole conductor, and encapsulating the semiconductor chip with a resin. The printed circuit board has a metal sheet of nearly the same size as the printed circuit board and is nearly in the center in the thickness direction of the printed circuit board.

Abstract: A power semiconductor module, a metal terminal for the power semiconductor module, and methods of fabricating a power semiconductor module and the metal terminal are disclosed. In the power semiconductor module, the metal terminal improves the adhesive strength between the metal terminal and a substrate of the module by increasing the surface area of the metal terminal that contacts an adhesive. A hole and a protrusion formed in an attachment plate of the terminal provide more surface area contacting the adhesive, thereby increasing the adhesive strength between the metal terminal and a metal substrate.

Abstract: An integrated circuit arrangement having an integrated circuit package contains an integrated circuit device mounted to a surface of the package. A flat frame is placed on the package surface and substantially surrounds the device. The flat frame has a central opening that receives the integrated circuit device. The height of the flat frame is relative to the height of the circuit device. A heat sink is mounted to the circuit device such that the bottom of the heat sink contacts the upper surface of the integrated circuit device but, does not contact the flat frame.

Abstract: The package-side land 3a of a semiconductor package P1 is wholly exposed into the opening 5a of a solder resist layer 5. The board-side land 12a of the mount board B1 is also wholly exposed into the opening 13a of a solder resist layer 13. When the semiconductor package P1 and the mount board B1 are joined to each other through a soldering layer 14a, the soldering layer 14a is brought into contact to both the lands 3a and 12a while extending to the side wall surfaces thereof so that the joint strength can be enhanced by the increasing contact area and the shape. When the lands 3a and 12a are set to be equal to each other in dimension and shape, the soldering layer 14a is shaped into a pillar having a substantially uniform section, thereby preventing local concentration of stress.

Abstract: In the present invention, an insulating film adhesive material is attached onto the wirings in the form of a tent so that an empty space communicating with a vent hole is provided. Use of this chip-supporting substrate makes it possible to produce small-sized semiconductor packages preventive of package cracking and having a high reliability, because the function of the vent hole is not damaged and also gases and water vapor which are generated from the insulating film adhesive material at the time of reflowing can be driven off surely outside the package.

Abstract: A semiconductor mounting package includes at least one diamond member having a first surface on which at least one semiconductor chip is mounted and a second surface opposite the first surface, and a high thermal conductivity metal member adhered to the second surface of the diamond member.

Abstract: A chip module has a contact area disposed on its outer side formed of a plurality of essentially flat contact elements of electrically conductive material insulated from one another. At least one semiconductor chip having one or more integrated semiconductor circuits that are electrically connected to the contact elements of the contact area via bonding wires. The contact elements of the chip module are formed by a prefabricated lead frame for supporting the at least one semiconductor chip and have on two opposing sides of the chip module outwardly offset terminals arranged in rows next to one another. The outwardly offset terminals are provided for surface mounting the chip module on the mounting surface of an external printed circuit board or an external circuit board substrate.

Abstract: The present invention provides a mounted structure of circuit board which can be prepared by a simple method and exhibits a good heat dissipation from chip and undergoes relaxed heat stress and a multi-layer circuit board to be incorporated in the mounted structure. A novel mounted structure of circuit board is provided comprising a core material embedded in an insulating layer, said core material having a metal layer with a heat conductivity of not less than 100 W/m·K provided on at least one side of an Ni—Fe alloy foil, said insulating layer comprising a wire conductor provided and a semiconductor element mounted on at least one side thereof, characterized in that a solder metal member for heat conduction is provided interposed between said semiconductor element and said core material so that said semiconductor element and said core material are connected to each other.

Abstract: According to the present invention, for a multi-layer plastic package having bonding pads at multiple levels, a plurality of electrically independent side wall conductive layers can be provided by forming side wall conductive layer on the side wall of an opening in each insulating layer. In particular, when the insulating layer forms a multi-layer structure, side wall conductive layers are formed on each of the individual side walls of the multi insulating layers, and a pre-impregnated layer is inserted between each two insulation layers, so that a plurality of electrically independent side wall conductive layers can be provided. Even for an insulating layer having a single layer structure, side wall conductive layers are formed so as to be electrically separated from each other, so that a plurality of side wall conductive layers can be provided.

Abstract: An assembly that has an insert that fits onto a back plate. The back plate receives a circuit board that covers at least a portion of the insert. A components attaches to the circuit board and to the insert. The insert is made out of a material having a thermal expansion coefficient that is close to the thermal expansion coefficient of the bottom surface of the component, which allows the component to be securely soldered to the insert and therefore to the assembly. Preferably the insert is also made out of a good conductor to provide a good electrical conduction path between the component and the ground plane of the circuit board that contact the insert. The insert either fits into a recessed area in the back plate or attaches to the top of the back plate. In an alternative embodiment, the assembly has a circuit board with a contact opening and a back plate with a raised area that fits into the contact opening. The contact opening exposes a portion of ground plane on the circuit board.

Abstract: Packages for an integrated circuit device and methods and leadframes for making such packages are disclosed. The package includes a die, a die pad, leads, bond wires, and an encapsulant. The lower surfaces of the die pad and leads are provided with a stepped profile by an etching step that etches partially through the thickness of a peripheral portion of the die pad, and also etches partially through the thickness of portions of the leads. Encapsulant material fills in beneath the recessed, substantially horizontal surfaces of the die pad and leads formed by the above-described etching step, and thereby prevents the die pad and leads from being pulled vertically from the package body. Other portions of the die pad and leads are exposed at the lower surface of the package for connecting the package externally. A metal leadframe for making an encapsulated package includes an outer frame. A die pad is within and connected to the frame.

Abstract: A semiconductor device including (a) a base plate, (b) an insulation substrate including of an insulator plate with a front electrode and a back electrode bonded thereon and fixed onto the base plate by the back electrode, (c) a semiconductor element fastened onto the insulation substrate by the front electrode, (d) an insulating cover covering the semiconductor element, and (e) electrodes that are led from the semiconductor element to the outside of the insulating cover. The back electrode is larger than the insulator plate, and the base plate has a through hole that is smaller than the back electrode and larger than the insulator plate. The insulation substrate is positioned in the through hole and is fastened onto the back surface of the base plate by the periphery of the back electrode. The insulation substrate can make direct contact with a heat sink without the base plate intervening therebetween, and thereby thermal resistance between the semiconductor element and the heat sink is decreased.

Abstract: A process for forming a thermally enhanced Chip On Board semiconductor device with a heat sink is described. In one aspect, a thermally conducting filled gel elastomer material or a silicon elastomeric material or elastomeric material, if the material is to be removed, is applied to the die surface to which the heat sink is to be bonded. During the subsequent glob top application and curing steps, difficult-to-remove glob top material which otherwise may be misapplied to the die surface adheres to the upper surface of the elastomer material. The elastomer material is removed by peeling prior to adhesion bonding of the heat sink to the die. In another aspect, the thermally conducting filled gel elastomer material is applied between a die surface and the inside attachment surface of a cap-style heat sink to eliminate overpressure on the die/substrate interface.

Abstract: A printed wiring board assembly includes a pallet that is coupled to the bottom surface of a printed wiring board. An insert is provided having a first portion that is slidably mounted to the pallet and a second portion that is bonded to the bottom surface of the printed wiring board so that the insert is movable, relative to the pallet, in a plane parallel to the PWB. In one embodiment, the pallet includes an opening having a first portion and a second portion that is larger than the first portion, and the first and second portions of the insert fit at least partially in the respective first and second portions of the pallet opening. In another embodiment, the insert has a thickness that is equal to or greater than the thickness of the pallet.

Abstract: A ball grid array package with conductive leads comprising a silicon chip, a heat sink, a plurality of conductive leads, bonding wires, and solder balls, a substrate and a molding compound. The conductive leads and the substrate are positioned below the heat sink such that the conductive leads are sandwiched between one surface of the substrate and the heat sink. The heat sink has a die-attach region for attaching the silicon chip. The silicon chip is electrically connected to contact points on another surface of the substrate and the conductive leads by bonding wires. The conductive leads are directly mounted to a printed circuit board. The contact points on the other surface of the substrate are electrically connected to the printed circuit board through trace lines inside the substrate and the solder balls attached to some of the contact points. The bonding wires, a portion of the conductive leads, and the silicon chip are enclosed by the molding compound for better protection.

Abstract: An interconnected apparatus for producing a low loss, reproducible electrical interconnection between a semiconductor device and a substrate includes a rod and rod receptor. The rod, generally cylindrically shaped, is attached to the semiconductor device and includes an outer circumferential wall which comes into contact with the rod receptor during a bonding process. A lip portion is formed on one end of the rod receptor for interlocking engagement with the rod. The rod receptor is plated on the substrate and includes a generally circularly shaped body which forms a centrally disposed well for receiving the rod. A lip portion is formed on one end or mouth of the rod receptor for interlocking engagement with the rod. When the rod and corresponding receptor are aligned and brought together, the rod deforms and interlocks with its corresponding rod receptor. A thermo-compression bonding process is utilized to bond the rod to the rod receptor, thereby producing a strong interlocking bond.

Abstract: A layer-type ball grid array (BGA) semiconductor package, module and methods of manufacturing same is provided that expands the capability of the package in a limited area. The BGA semiconductor package and method of manufacturing same includes a substrate having a cavity formed therein and an interconnection pattern layer that has a plurality of conductive interconnections forming electric channels between or electrically coupling upper and lower surfaces of the substrate is attached to an external surface of the substrate. The interconnection pattern layer extends from the upper surface to the lower surface of the substrate. A semiconductor chip is provided in bottom of the cavity and a plurality of conductive wires electrically couple the semiconductor chip to one of the conductive interconnections. A molding part fills in the cavity for sealing the semiconductor chip and wires.

Abstract: A semiconductor device includes a semiconductor pellet (1), and a package having a pellet mount portion (21) on which a semiconductor pellet (1) is mounted. The semiconductor pellet (1) is mounted on the pellet mount portion (21) of the package through a joint material (6). The area of the surface of the pellet mount portion (21) on which the semiconductor pellet (1) is mounted is set to be smaller than the area of the surface of the semiconductor pellet (1) which is mounted on the pellet mount portion (21), thereby preventing the climb-up of the joint material (6) along the side surface of the semiconductor pellet (1).